Patent Application
20250218898
As advanced packaging is enabling more aggressive computation capability, high power and high quality power delivery is needed to support all of the overlying chiplets. Accordingly, the ability to embed passive components (e.g., capacitors, inductors, resistors, etc.) into the package substrate will enable improved performance compared to placing the passive components on the land side of the package. Embedding components in the core is beneficial because there is less routing in the core compared to overlying and underlying buildup layers. As such, space within the package substrate is more fully utilized.
However, substrate core thickness is defined by the total package thermomechanical stress level. This required thickness can be significantly different than the thickness of the passive component. For example, in the case of a deep trench capacitor (DTC), the DTC is fabricated on a silicon wafer. The wafer will have a thickness that is potentially hundreds of microns different than the thickness of the core, which can be approximately 1.0 mm or greater. Placing such passive components in deep cavities through the core can be problematic. For example, the passive components may shift or rotate during embedding.
Described herein are electronic systems, and more particularly, components embedded in a deep cavity with dummy structures, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Various embodiments or aspects of the disclosure are described herein. In some implementations, the different embodiments are practiced separately. However, embodiments are not limited to embodiments being practiced in isolation. For example, two or more different embodiments can be combined together in order to be practiced as a single device, process, structure, or the like. The entirety of various embodiments can be combined together in some instances. In other instances, portions of a first embodiment can be combined with portions of one or more different embodiments. For example, a portion of a first embodiment can be combined with a portion of a second embodiment, or a portion of a first embodiment can be combined with a portion of a second embodiment and a portion of a third embodiment.
As noted above, introducing passive components (e.g., inductors, capacitors, resistors, etc.) into the package substrate is desirable to improve power delivery and performance for the overlying chiplets compared to placing the passive components on the land side of the package substrate. This is due, at least in part, to the passive components being physically closer to the chiplets when they are integrated into the package substrate. One suitable location in the package substrate for the passive components is the core. The core has underutilized space that can be leveraged to house the passive components. However, the thickness of the passive components is usually smaller than a thickness of the core. This can lead to integration and manufacturing issues. Examples of these drawbacks can be seen in
Referring now to
In an embodiment, a component 120 is provided in the cavity 107. The component 120 may have a thickness that is smaller than a thickness of the core 105. For example, the component 120 may have a thickness that is hundreds of microns thinner than the core 105. The component 120 is secured within the cavity 107 through the use of a fill layer 125. The fill layer 125 may be a dielectric material, such as a mold layer, an epoxy, an adhesive, or the like. However, during the filling process, the component 120 may shift and/or rotate. The movement of the component 120 may be due, at least in part, to the introduction of pressure to the component 120 during the filling process. As shown, the component 120 has tilted so that one side is raised up from the bottom of the core 105. This may make it difficult to make electrical contact to the pads 122 that are at the bottom of the component 120 in subsequent processing operations.
Accordingly, embodiments disclosed herein reduce movement of the component 120 by providing components 120 that have a dummy structure (sometimes referred to as a spacer, a layer, a pillar, a support structure, or the like). The dummy structure is provided over the component 120 in order to substantially equalize the thickness of the component with the thickness of the core 105. Individually forming and attaching dummy structures to components 120 may be impracticable in some instances. As such, embodiments disclosed herein may include assembling a plurality of components 120 together in a reconstituted substrate. That is, a plurality of individual components 120 can be overmolded to form a single substrate. The dummy structure can then be manufactured over all components at substantially the same time. The dummy structures may be formed with a plating process, such as a blanket plating process. Alternatively, a semi-additive process (SAP) may be used to form the dummy structures. Etching processes may also be used in some embodiments.
In addition to providing thickness adjustments to the components 120, the dummy structures may also provide additional benefits. In one instance, dummy pillars can be coupled to pads and vias within the component 120. As such, the dummy pillars may actually be part of the electrical circuitry of the device. Dummy structures may also be used to improve thermal performance. For example, when a material with a high thermal conductivity (e.g., copper) is used for the dummy structure, more thermal energy can be withdrawn from the component 120 during operation.
Referring now to
In an embodiment, the component 220 may comprise a substrate 221. The substrate 221 may include any suitable material that provides a solid base on which (or into which) passive structures can be fabricated. In some embodiments, the substrate 221 may comprise a semiconductor material, such as silicon. For example, a silicon wafer may be processed to produce a plurality of passive devices. After processing, the silicon wafer is singulated in order to provide individual components 220. While silicon can be used in some embodiments, other embodiments may include a substrate 221 that comprises a ceramic, a glass, an insulator, or the like.
In an embodiment a routing layer 223 may be provided over the substrate 221. The routing layer 223 may be a different material than the substrate 221. For example, the routing layer 223 may include a dielectric material, such as one comprising silicon and oxygen (e.g., SiO2) or silicon and nitrogen (e.g., Si3N4). Organic dielectrics may also be used in some embodiments. The routing layer 223 may include electrical routing (not shown), such as pads, traces, and the like. In some embodiments, the routing layer 223 is omitted, or the electrical routing is otherwise provided in the substrate 221.
In an embodiment, a liner 224 is provided along a sidewall of the substrate 221. The liner 224 may be provided around a perimeter of the substrate 221. That is, all sidewalls of substrate 221 may be contacted by the liner 224. In a particular embodiment, the liner 224 covers the entire height of the sidewall of the substrate 221. The liner 224 may also contact the routing layer 223. That is, a height of the liner 224 may be substantially equal to a combined height of the substrate 221 and the routing layer 223. As used herein, “substantially equal” may refer to two values that are within ten percent of each other. For example, liner 224 with a height between 450 μm and 550 μm may be considered as being substantially equal to a combined height of the substrate 221 and the routing layer 223 that is 500 μm. The liner 224 may comprise a molding material. For example, an organic dielectric material, such as an epoxy, a polymer, or the like, may be used for the liner 224. The liner 224 may include filler particles that allow for tailoring a coefficient of thermal expansion (CTE) of the liner 224. This allows for improved CTE matching with the substrate 221 in order to limit warpage, stress generation, or the like.
In an embodiment, a dummy structure 226 is provided on the substrate 221. The dummy structure 226 may be provided in direct contact with the substrate 221. The dummy structure 226 may also directly contact the liner 224. That is, a width of the dummy structure 226 may be greater than a width of the substrate 221 in some embodiments. In an embodiment, the dummy structure 226 may comprise any suitable material or materials, such as one that is rigid and includes a CTE comparable to that of the substrate 221. In an embodiment, the dummy structure 226 may comprise copper or another metallic material. The dummy structure 226 may also include epoxies, polymers, ceramics, glass, or the like. The dummy structure 226 may be disposed over the substrate 221 with any suitable process. For example, a plating process or other deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like may be used.
In an embodiment, the component 220 may have a total thickness that is substantially equal to a thickness of the core (not shown) in which the component 220 will be embedded. For example, the component 220 may have a total thickness that is approximately 1.0 mm or greater. In the illustrated embodiment, the substrate 221 is thicker than the dummy structure 226. Though, in other embodiments the dummy structure 226 may be thicker than the substrate 221.
Referring now to
In some embodiments, dicing through the dummy structure 226 is not practical. As such, an etching process may be used in order to create gaps between dummy structures 226 on the reconstituted substrate. The etching process may be an isotropic etching process (e.g., a wet etch). As such, the sidewalls 227 may have some degree of curvature, or the sidewalls 227 may be sloped. That is, the sidewalls 227 may have a non-vertical profile. It is to be appreciated that the profile of the sidewalls 227 shown in
Referring now to
Similar to the embodiment shown in
Instead of providing a solid bock or layer over the substrate 321, the dummy layer comprises one or more dummy pillars 326. For example, a first dummy pillar 326A and a second dummy pillar 326B are shown in
In an embodiment, the dummy pillars 326A and 326B may comprise a material similar to the material used for the dummy structure 226 described above. For example, the dummy pillars 326A and 326B may comprise copper or the like. In an embodiment, the dummy pillars 326A and 326B may be formed with any suitable patterning or deposition process. In one embodiment, a solid layer (similar to dummy structure 226) may be formed, and the solid layer may then be etched to form the dummy pillars 326A and 326B. In other embodiments, an SAP operation may be used to form the dummy pillars 326A and 326B.
The dummy pillars 326A and 326B may have any suitable dimensions. For example, an aspect ratio (e.g., height:width) may be approximately 0.5:1 or greater, 1:1 or greater, or 5:1 or greater. Though, smaller aspect ratios may also be used in some embodiments. Typically, an SAP process can form higher aspect ratio feature compared to an etching process. Though, etching processes may be more cost effective.
The use of dummy pillars 326A and 326B may provide several benefits for the components 320. For example, reducing the volume of the dummy structure can decrease warpage. That is, warpage due to CTE mismatch is reduced since there is less copper (or other material) directly interfacing with the substrate 321. Additionally, the configuration of the dummy pillars 326A and 326B may provide direct access to the liner 324. As such, singulation of the reconstituted substrate is made easier since the singulation or dicing does not need to pass through copper (or other material of the dummy pillars 326A and 326B).
Referring now to
Additionally, the dummy pillars 326A and 326B may be electrically coupled to the vias 327 through pads 328. Though, the dummy pillars 326A and 326B may also be directly coupled to the vias 327 in other embodiments. As such, electricity (e.g., electrical signals, power, etc.) may pass up through the dummy pillars 326A and 326B in order to pass electricity through at least a portion of a thickness of the substrate 321. That is, while referred to as being a “dummy” structure, the dummy pillars 326A and 326B may actually be part of the electrical circuitry of the component 320. This allows for a multi-functionality approach which can lead to improved performance, decreased footprints, and/or other benefits.
Referring now to
Referring now to
In an embodiment, the components 420 are placed on a carrier substrate 440. The carrier substrate 440 may comprise glass, silicon, metal, ceramic, or the like. The carrier substrate 440 is a temporary structure used to support the components 420 during the generation of the reconstituted substrate 450 shown in a subsequent processing operation. In an embodiment, the components 420 may be oriented so that the routing layers 423 are contacting the carrier substrate 440. Though, the routing layers 423 may also face away from the carrier substrate 440 in other embodiments.
Referring now to
In an embodiment, the liner 424 may be formed to a thickness that is greater than a thickness of the components 420. After molding, a polishing or planarizing process (e.g. chemical mechanical planarization (CMP)) may be used in order to recess the liner 424. The recessing may result in a top surface of the liner 424 being substantially coplanar with a top surface of the substrate 421.
Referring now to
In the illustrated embodiment, two dummy pillars 426A and 426B are shown on each component 420. Though, fewer or more dummy pillars 426 may be provided on each component 420. Further, a single dummy structure or layer (e.g., similar to dummy structure 226 in
Referring now to
In the illustrated embodiment, the resulting sidewalls of the liner 424 are substantially vertical. Though, different dicing methods may result in sidewalls that have profiles that are non-vertical and/or non-planar. While the dicing is shown in one direction (i.e., along each side of the components 420), it is to be appreciated that dicing also occurs in front of the components 420 and behind the components (as viewed in
Referring now to
The glass core 405 may have any suitable dimensions. In a particular embodiment, the glass core 405 may have a thickness that is approximately 50 μm or greater. For example, the thickness of the glass core 405 may be between approximately 50 μm and approximately 1.4 mm. Though, smaller or larger thicknesses may also be used. The glass core 405 may have edge dimensions (e.g., length, width, etc.) that are approximately 10 mm or greater. For example, edge dimensions may be between approximately 10 mm to approximately 250 mm. Though, larger or smaller edge dimensions may also be used. More generally, the area dimensions of the glass core 405 (from an overhead plan view) may be between approximately 10 mm×10 mm and approximately 250 mm×250 mm. In an embodiment, the glass core 405 may have a first side that is perpendicular or orthogonal to a second side. In a more general embodiment, the glass core 405 may comprise a rectangular prism volume with sections (e.g., vias) removed and filled with other materials (e.g., metal, etc.).
The glass core 405 may comprise a single monolithic layer of glass. In other embodiments, the glass core 405 may comprise two or more discrete layers of glass that are stacked over each other. The discrete layers of glass may be provided in direct contact with each other, or the discrete layers of glass may be mechanically coupled to each other by an adhesive or the like. The discrete layers of glass in the glass core 405 may each have a thickness less than approximately 50 μm. For example, discrete layers of glass in the glass core 405 may have thicknesses between approximately 25 μm and approximately 50 μm. Though, discrete layers of glass may have larger or smaller thicknesses in some embodiments.
The glass core 405 may be any suitable glass formulation that has the necessary mechanical robustness and compatibility with semiconductor packaging manufacturing and assembly processes. For example, the glass core 405 may comprise aluminosilicate glass, borosilicate glass, alumino-borosilicate glass, silica, fused silica, or the like. In some embodiments, the glass core 405 may include one or more additives, such as, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. More generally, the glass core 405 may comprise silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In an embodiment, the glass core 405 may comprise at least 23 percent silicon (by weight) and at least 26 percent oxygen (by weight). In some embodiments, the glass core 405 may further comprise at least 5 percent aluminum (by weight).
In an embodiment, one or more vias 408 may pass through a thickness of the core 405. In the illustrated embodiment, the vias 408 have a rectangular cross-section. Though, other embodiments may include vias 408 with tapered sidewalls. In some embodiments, an insulating plug (not shown) may be provided inside the vias 408.
In an embodiment, a cavity 407 may pass through at least a portion of a thickness of the core 405. In the illustrated embodiment, the cavity 407 passes entirely through the core 405. Sidewalls of the cavity 407 may be substantially vertical. Other embodiments may include sidewalls that are sloped, tapered, or the like.
In an embodiment, a carrier or tape 410 may be provided below the core 405. The tape 410 may span the opening of the cavity 407 in order to provide a support surface for the component 420. In an embodiment, the component 420 may be placed into the cavity 407 with a pick-and-place tool, manually, or with any other suitable process. In an embodiment, component 420 is placed onto the tape 410 so that the routing layer 423 contacts the tape 410. In an embodiment, the core 405 may have a first thickness T1, and the component 420 may have a second thickness T2. The first thickness T1 may be substantially equal to the second thickness T2.
Referring now to
Referring now to
In an embodiment, the process 470 may continue with operation 472, which comprises providing a liner between the component substrates to form a reconstituted substrate. The operation 472 may include a structure and process similar to what is illustrated and described with respect to
In an embodiment, the process 470 may continue with operation 473, which comprises forming dummy pillars over the component substrate. The operation 473 may include a structure and process similar to what is illustrated and described with respect to
In an embodiment, the process 470 may continue with operation 474, which comprises singulating the reconstituted substrate to form a plurality of components. The operation 474 may include a structure and process similar to what is illustrated and described with respect to
In an embodiment, the process 470 may continue with operation 475, which comprises embedding one of the plurality of components in a core. The operation 475 may include a structure and process similar to what is illustrated and described with respect to
Referring now to
In an embodiment, a cavity 507 may be provided through a thickness of the core 505. A plurality of components 520 may be embedded in the cavity 507 by a layer 525. For example, a first component 520A and a second component 520B are shown in
Referring now to
Referring now to
In an embodiment, a first cavity 607A and a second cavity 607B may be provided through a thickness of the core 605. A components 620A or 620B may be embedded in each of the cavities 607A and 607B by a layer 625. For example, a first component 620A may be provided in the first cavity 607A, and a second component 620B may be provided in the second cavity 607B. The first component 620A and the second component 620B may be substantially similar to each other. For example, both may include a substrate 621 with a routing layer 623. Liners 624 may surround both components 620A and 620B. Additionally, dummy pillars 626A and 626B may be provided over the substrate 621 for each component 620.
Referring now to
Referring now to
In an embodiment, the package substrate 700 may be similar to any of the package substrates described herein. For example, the package substrate 700 may include a core 705 (e.g., a glass core 705 or an organic core 705) with buildup layers 760 above and below the core 705. The core 705 may comprise vias 708. In
In an embodiment, the component 720 may be similar to any of the components described in greater detail herein. For example, the component 720 may be a passive component such as one or more of an inductor, a capacitor, a resistor, or the like. The component 720 may have a total thickness that is substantially equal to a thickness of the core 705. In an embodiment, the component 720 may comprise a substrate 721 and a routing layer 723, both of which may be surrounded by a liner 724. Dummy pillars 726 (or other spacer or standoff structures) may be provided on the substrate 721 to increase the thickness of the component 720.
In an embodiment, one or more dies 795 may be coupled to the package substrate 700 by interconnects 794. The interconnects 794 may comprise first level interconnects (FLIs), such as solder balls, copper bumps, hybrid bonding interfaces, or the like. The die 795 may be any type of die, such as a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a communications die, a memory die, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. In an embodiment, the component 720 is electrically coupled to the one or more dies 795 in order to control and/or improve power delivery that is provided to the die 795.
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 806 enables wireless communications for the transfer of data to and from the computing device 800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the disclosure, the integrated circuit die of the processor may be part of an electronic package that includes a component with dummy pillars or other spacer structures that are embedded in a cavity that passes through a core of the package substrate, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip may be part of an electronic package that includes a component with dummy pillars or other spacer structures that are embedded in a cavity that passes through a core of the package substrate, in accordance with embodiments described herein.
In an embodiment, the computing device 800 may be part of any apparatus. For example, the computing device may be part of a personal computer, a server, a mobile device, a tablet, an automobile, or the like. That is, the computing device 800 is not limited to being used for any particular type of system, and the computing device 800 may be included in any apparatus that may benefit from computing functionality.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1: an apparatus, comprising: a substrate with a first material composition; a liner on a sidewall of the substrate; and a layer on the substrate, wherein the layer has a second material composition that is different than the first material composition, and wherein the layer directly contacts at least a portion of a surface of the substrate.
Example 2: the apparatus of Example 1, wherein the layer directly contacts the liner.
Example 3: the apparatus of Example 1 or Example 2, wherein the liner surrounds an entire perimeter of the first layer.
Example 4: the apparatus of Examples 1-3, wherein the layer comprises a first pillar and a second pillar.
Example 5: the apparatus of Example 4, wherein the substrate comprises a via, and wherein the first pillar or the second pillar is electrically coupled to the via.
Example 6: the apparatus of Examples 1-5, wherein the substrate comprises silicon, and wherein the layer comprises copper.
Example 7: the apparatus of Examples 1-6, wherein the substrate comprises a passive component including one or more of a capacitor, an inductor, or a resistor.
Example 8: the apparatus of Examples 1-7, wherein a sidewall of the layer is non-planar.
Example 9: the apparatus of Examples 1-8, wherein the substrate comprises: a first portion comprising a semiconductor material; and a second portion comprising electrical routing embedded in a dielectric layer.
Example 10: the apparatus of Example 9, wherein the liner covers the first portion and the second portion.
Example 11: an apparatus, comprising: a first substrate with a first thickness; a cavity through the first substrate; a component in the cavity, wherein the component has a second thickness that is substantially equal to the first thickness, and wherein the component comprises: a second substrate; a liner around a perimeter of the second substrate; and a first layer on the second substrate; and a second layer in the cavity around the component.
Example 12: the apparatus of Example 11, wherein the component comprises one or more of an inductor, a capacitor, or a resistor.
Example 13: the apparatus of Example 11 or Example 12, wherein the first layer comprises a first pillar and a second pillar.
Example 14: the apparatus of Examples 11-13, wherein the liner comprises a first material composition, and wherein the second layer comprises a second material composition that is different than the first material composition.
Example 15: the apparatus of Examples 11-14, wherein the second substrate comprises silicon.
Example 16: the apparatus of Examples 11-15, wherein the first layer comprises copper.
Example 17: the apparatus of Examples 11-16, wherein the first substrate comprises a solid glass layer with a rectangular prism form factor or an epoxy layer.
Example 18: an apparatus, comprising: a board; a package substrate coupled to the board, wherein the package substrate comprises: a core with a cavity through the core; a component in the cavity; and a spacer on the component, wherein a combined thickness of the spacer and the component is substantially equal to a thickness of the core; and a die coupled to the package substrate.
Example 19: the apparatus of Example 18, wherein the component comprises a liner around a semiconductor substrate, wherein the liner comprises a dielectric, a mold material, or a polymer.
Example 20: the apparatus of Example 18 or Example 19, wherein the apparatus is part of a personal computer, a server, a mobile device, a tablet, or an automobile.
