Patent Application
20100258949
The present disclosure generally relates to semiconductor device assembly. More specifically, the present disclosure relates to reducing electrostatic discharge susceptibility in stacked IC device assembly.
A 3D semiconductor device (or stacked IC device) can contain two or more semiconductor devices stacked vertically so they occupy less space than two or more conventionally arranged semiconductor devices. The stacked IC device is a single integrated circuit built by stacking silicon wafers and/or ICs and interconnecting them vertically so that they behave as a single device.
Conventionally, the stacked semiconductor devices are wired together using input/output ports either at the perimeter of the device or across the area of the device or both. The input/output ports slightly increase the length and width of the assembly. In some new 3D stacks, through-silicon vias (TSVs) completely or partly replace edge wiring by creating vertical connections through the body of the semiconductor device. By using TSV technology, stacked IC devices can pack a great deal of functionality into a small footprint. This TSV technique is sometimes also referred to as TSS (Through Silicon Stacking). Furthermore, critical electrical paths through the device can be drastically shortened, reducing capacitance and resistance and therefore improving power dissipation, and performance.
Assembly and packaging of semiconductor devices should take into account the adverse affects of electrostatic discharge. Conventionally, there are several ways of reducing ESD. One is to provide proper grounding of assembly equipment parts to prevent charge buildup that may result in discharge capable of destroying circuit components, such as transistors. A second is use of ionized air-flow to reduce charge build-up on the ICs and the assembly fixtures. Another way is to eliminate or reduce ESD damage by providing ESD protection circuitry on the semiconductor device.
However, in stacked IC device assembly and connection, to maximize the density of connections and reduce electrical parasitics, circuit-level ESD protection is reduced or eliminated. The semiconductor devices may then be more susceptible to damage from ESD during assembly. The same ESD susceptibility concerns apply whether the assembly process is chip-to-chip (i.e., IC-to-IC) or chip to wafer (i.e., IC-to-wafer) or wafer to wafer. Therefore, there is a need to develop methods and structures to enable the assembly of stacked IC devices with reduced sensitivity to ESD when protection circuitry is not included in every individual IC or wafer.
A method to reduce electrostatic discharge when assembling a stacked IC device includes coupling a voltage reference plane, usually the ground plane or body, of a first semiconductor device and a voltage reference plane, usually the ground plane or body of a second semiconductor device to substantially the same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates an electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.
A system to assemble stacked IC devices with reduced electrostatic discharge (ESD) susceptibility includes a movable pick-and-place (PnP) chuck configured to carry at least a first semiconductor device containing one or more integrated circuits. The first semiconductor device includes a ground plane and active circuitry. A movable PnP head is configured to carry a second semiconductor device. The second semiconductor device includes a ground plane and active circuitry. The system is configured to electrically couple the ground planes of the first and second semiconductor devices to substantially a same electrical potential prior to electrically coupling the active circuitry of the first and second semiconductor devices.
A first semiconductor device for assembly with a second semiconductor device to create a stacked IC device includes a conductive pad coupled to a ground plane of the first semiconductor device. The conductive pad enables placing the ground plane of the first semiconductor device and the ground plane of the second semiconductor device at substantially a same electrical potential before electrical coupling the active circuitry of the first and second semiconductor devices.
In another embodiment, a first semiconductor device for assembly with a second semiconductor device to create a stacked IC device includes at least one conductive pad. The pad(s) is coupled to a ground plane of the first semiconductor device enabling placing the ground plane of the first semiconductor device and the ground plane of the second semiconductor device at substantially a same electrical potential before coupling an active circuit on the first semiconductor device to an active circuit on the second semiconductor device of the stacked IC device.
In still another embodiment, a first semiconductor device for assembly with a second semiconductor device to create a stacked IC device includes means for reducing susceptibility to electrostatic discharge (ESD) coupled to a ground plane of the first semiconductor device. The reducing means enables placing of the ground plane of the first semiconductor device and a ground plane of the second semiconductor device at substantially a same electrical potential before coupling active circuitry of the first semiconductor device to active circuitry of the second semiconductor device.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other embodiments for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
In
In either alternative arrangement, at least one conductive pad 225 (e.g., a micro-bump) can be placed on the side of the first semiconductor device 210 not facing the carrier 205. The conductive pad 225 is in electrical contact with the ground plane of the semiconductor device 210. The ground plane and the conductive pad 225 provide low resistance paths to reduce an electrical potential that may occur, thus reducing the likelihood of electrostatic discharge damage to active circuitry. In one embodiment, the conductive pad 225 is provided in a scribe line.
The first semiconductor device 210 may have additional low resistance conductive pads 220 for electrical connections to the active circuitry. In case the ground plane and/or active circuitry are located on the opposite sides of the first semiconductor device 210 from the conductive pads 220, 225, optional through silicon vias (TSVs 290) can be used to provide low resistance electrical connections between the conductive pads 220, 225 to the respective ground plane and active circuitry on the opposite side of the first semiconductor device 210. Although the terminology “through silicon via” includes the word silicon, it is noted that through silicon vias are not necessarily constructed in silicon. Rather, the material can be any device substrate material.
The carrier 205 can be placed on a movable pick-and-place (PnP) chuck 230 (i.e., PnP chuck 230), which is electrically conductive, i.e., is a low resistance path. Furthermore, the PnP chuck 230 can be connected to a common electrical ground 201.
In an embodiment, the system 200 can further include a conductive movable PnP head 235 electrically connected to provide a low resistance path to the same common electrical ground 201 as the PnP chuck 230. The PnP head 235 carries a second semiconductor device 240 having a ground plane (not shown) and active circuitry 244. The second semiconductor device 240 may be an IC. The orientation of the second semiconductor device 240 can result in an active face 244 facing the first semiconductor device 210 (as shown in
The second semiconductor device 240 has low resistance conductive pads 245 electrically connected to active circuitry that are brought into electrical connection with active circuitry on the first semiconductor device 210 when contacted to the corresponding conductive pads 220 during assembly.
The PnP head 235 head includes a low resistance electrical contact probe 250 to electrically couple to the conductive pad 225 on the first semiconductor device 210 as the PnP head 235 is moved to position the second semiconductor device 240 for assembly to the first semiconductor device 210. The contact probe 250 contacts the conductive pad 225 before the conductive pads 245 contact the corresponding conductive pads 220, reducing susceptibility to ESD. The contact probe 250 may be, for example, a spring loaded pogo pin, or an equivalent. This ensures that the ground planes of the first semiconductor device 210 and the second semiconductor device 240 achieve substantially the same electrical potential before the active circuitry of the first semiconductor device 210 and the second semiconductor device 240 are brought into electrical communication. Various combination of the conductive pad 225, optional TSVs 290 (depending on the first semiconductor device orientation), the grounded PnP chuck 230, the grounded PnP head 235 and the contact probe 250 may be used in suitable embodiments to ensure that the first semiconductor device ground plane is at substantially the same electrical potential as the ground plane of the second semiconductor device 240 prior to final chip-to-wafer or chip-to-chip assembly.
As shown in
In some embodiments, for example where the first semiconductor device 210 is a wafer, the ground plane conductive pad 225 may be disposed in a scribe lane.
The system 300 differs from the system 200 because the system 300 includes a PnP head 335 holding a second semiconductor device 340 that differs from the PnP head 235 of the system 200 by not including the contact probe 250. Instead, a low resistance wafer conductive edge clip 365 makes an electrical connection between a PnP chuck 330 and a conductive pad 360 on the upward facing surface of a first semiconductor device 310, shown as a back face 314 in
When the ground plane of the first semiconductor device 310 is on the same surface as the conductive pad 360, a TSV 390 is not used. When the ground plane of the first semiconductor device 310 is on the opposite side, at least one TSV 390 may be used to couple the conductive pad 360 to the ground plane. As in the system 200, all conductive pads, ground planes and TSVs are low resistance paths.
When contact is made between the wafer conductive edge clip 365 and the conductive pad 360, the ground plane of the first semiconductor device 310 is then substantially grounded to the PnP chuck 330, which is also at the same potential as the PnP head 335, similar to the PnP head 235 of the embodiment of the system 200. When contact is made between the conductive edge clip 365 and the conductive pad 360, there is a reduced susceptibility to ESD. In case the semiconductor device 310 is placed on a carrier 305 with the active face 312 downward, i.e., toward the carrier 305, the conductive pads 320 may be in electrical communication with the active circuitry on the active face 312 via at least one TSV 390.
The structure of the system 300 thus establishes electrical communication between the ground planes of both the first semiconductor device 310 and the second semiconductor device 340 to place them at substantially the same electrical potential before electrical contact is actually made between the active circuitry of the first semiconductor device 310 and the second semiconductor device 340.
It can be appreciated that, from geometrical considerations, the system 300 is appropriate for a chip-to-wafer configuration (i.e., where the first semiconductor device 310 is a wafer, and the second semiconductor device 340 is an IC, i.e., a chip, or die). Two wafers of the same dimensions may not be stacked in this manner, due to the location of the wafer conductive edge clip 365. Alternatively, the first semiconductor device 310 may be an IC of larger dimension than the second semiconductor device 340 in order to provide an exposed location for the wafer conductive edge clip 365 to contact the conductive pad 360.
The system 300 has a common electrical ground 301, a temporary adhesive 315, an active face 344, and active circuit conductive pads 345, in correspondence with similar structures shown in
The system 400 differs from the system 200 and/or the system 300 in the following respects: The system 400 may not include the wafer conductive edge clip 365 and the conductive pad 360 of the system 300 of
As shown in
The system 500 is adapted to assemble a second semiconductor device 540 to a first semiconductor device 510. Active circuitry conductive pads 520 in electrical communication with active circuitry on an active face 514 and ground plane conductive pads 525 in electrical communication with a ground plane on the first semiconductor device 510 may be micro-bumps, for example. Similarly, the second semiconductor device 540 includes active circuitry conductive pads 545 (that may also be micro-bumps) in electrical communication with active circuitry on an active face 544 of the second semiconductor device 540. The active circuitry conductive pads 545 come in contact with the corresponding active circuitry conductive pads 520 (or micro-bumps) on the first semiconductor device 510 in the course of assembly.
The second semiconductor device 540 also includes ground plane conductive pads 575 in electrical communication with the ground plane of the second semiconductor device 540. The ground plane conductive pads 575 may be low resistance micro-bumps that are larger (e.g., taller if the dies are stacked in a horizontal configuration, as shown) than the active circuitry conductive pads 545. The ground plane conductive pads 575 will come in physical and electrical contact with the ground plane conductive pads 525 before the active circuitry conductive pads 520 and 545 make contact to reduce the susceptibility to ESD. That is, the ground planes of both semiconductor devices 510, 540 are electrically coupled to substantially the same potential before the active circuitry conductive pads 520 and 545 make electrical contact between the active circuitry on the first semiconductor device 510 and the active circuitry of the second semiconductor device 540. Alternatively, the ground plane conductive pads 525 may be larger (e.g., taller) micro-bumps, or both the ground plane conductive pads 575 and 525 may be larger (e.g., taller) micro-bumps than the active circuitry conductive pads 520, 545.
A PnP chuck 530 and a PnP head 535 are coupled to a common ground 501, as described above for systems 200, 300 and 400. The ground plane of the second semiconductor device 540 is in electrical communication with the PnP head 535, and is therefore at substantially the same common ground 501, i.e., electrical potential. TSVs 590 are used in the second semiconductor device 540 if the ground plane is on the opposite side of the second semiconductor device 540 that is facing the PnP head 535. A carrier 505 and a temporary adhesive 515 may be conductive or, alternatively, either or both may be non-conductive. Regardless, it may be appreciated that the ground planes of the first semiconductor device 510 and the second semiconductor device 540 can be brought to substantially the same electrical potential before active circuitry on the first semiconductor device 510 and the second semiconductor device 540 are electrically connected as a result of the assembly.
The various paths connecting wafers, carrier, head, chuck, etc. may result in the ground planes of the stacked semiconductor devices being assembled so that electrical potentials vary because of finite resistance. In that case, a threshold potential difference may be selected as a limit above which an unacceptable amount of damage to the active circuitry may potentially occur.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the intent of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
