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6512680 | Harada et al. | Jan 2003 | B2 |
6535398 | Moresco | Mar 2003 | B1 |
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Entry |
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David A. Baranauskas and Douglas E. Wallace, Jr., “Capacitive Structure for Via Impedance Tuning”; Sep. 14, 1999, Ser. No. 09/395,788. |
Doreen S. Fisher and Thad McMillian, “Printed Circuit Assembly Having Conductive Pad Array With In-Line Via Placement”, Jun. 28, 2000, Ser. No. 09/605,905. |