Reducing or eliminating pre-amorphization in transistor manufacture

Abstract

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Description

TECHNICAL FIELD

Integrated circuit processes and structures to allow for improved semiconductor substrate treatment are disclosed.

BACKGROUND

Placement of dopants in MOSFET transistors is increasingly difficult as transistor size is reduced. Misplaced dopants can reduce transistor performance and increase transistor variability, including variability of channel transconductance, capacitance effects, threshold voltage, and leakage. Such variability increases as transistors are reduced in size with each misplaced dopant atom having a greater relative effect on transistor properties consequent to the overall reduction in number of dopant atoms. One common source of misplaced dopants occurs as a result of damage to crystal structure of a transistor during manufacture, which increases defect pathways and creates excess silicon interstitials that allow enhanced dopant movement in undesired regions of the transistor.

A pre-amorphizing implant (PAI) can be used in semiconductor processing as a way to set up for dopant substitutionality. A PAI process generally involves introducing a dopant species using a high energy ion implantation to impart damage and thereby amorphize the implanted region. The damage and amorphization are important so that dopants from a previous or subsequent ion implantation can more easily move into substitutional sites. If PAI is used, then a subsequent anneal is performed to render the substrate crystalline again.

However, with the typical anneal process that is used, which is either a solid phase epitaxy (SPE) or high temperature anneal such as RTA, there remains residual damage from PAI which can create a pathway for leakage current by acting as localized generation/recombination sites.

BRIEF DESCRIPTION OF THE FIGURES

For a more complete understanding of the present disclosure, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

FIG. 1 illustrates an embodiment of an NMOS transistor incorporating germanium pre-amorphization implants and a screen layer;

FIG. 2 illustrates an embodiment of a PMOS transistor incorporating a screen layer and formable along with a structure according to FIG. 1;

FIG. 3 illustrates an embodiment of an NMOS transistor having no incorporated germanium pre-amorphization implants, but with an in-situ carbon doped silicon substrate to limit boron screen diffusion;

FIG. 4 illustrates an embodiment of a PMOS transistor having no incorporated germanium pre-amorphization implants, along with an in-situ carbon doped silicon substrate formable along with a structure in accordance with FIG. 4;

FIG. 5 illustrates an embodiment of an NMOS transistor having no incorporated germanium pre-amorphization implants, but with an in-situ carbon doped silicon epitaxial layer epitaxially grown above the screen;

FIG. 6 illustrates an embodiment of a PMOS transistor having no incorporated germanium pre-amorphization implants, but with an in-situ carbon doped silicon epitaxial layer formable along with a structure in accordance with FIG. 5;

FIG. 7 illustrates an embodiment of an NMOS transistor having no incorporated germanium pre-amorphization implants, but with two separately formed carbon doped regions to limit boron screen layer diffusion;

FIG. 8 illustrates an embodiment of an NMOS transistor having no incorporated germanium pre-amorphization implants, but with three separately formed carbon doped regions to limit boron screening layer diffusion;

FIG. 9 illustrates process steps for transistor manufacture that can be used to produce embodiments in accordance with the present disclosure;

FIG. 10 illustrates process steps for transistor manufacture for several alternative process embodiments that use selective epitaxial layers;

FIG. 11 illustrates process steps for transistor manufacture that can be used to limit the carbon species to the NMOS transistors only.

DETAILED DESCRIPTION

Unwanted transient enhanced diffusion (TED) resulting from defects and injected silicon interstitials from defect clusters can easily reduce or destroy transistor functionality, particularly for nanometer scale transistors having complex dopant profiles such as disclosed, for example, in embodiments of various transistor structures and manufacturing processes more completely described in U.S. application Ser. No. 12/708,497 titled “Electronic Devices and Systems, and Methods for Making and Using the Same”, U.S. application Ser. No. 12/971,884 titled “Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof”, U.S. application Ser. No. 12/971,955 titled “Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof”, and U.S. application Ser. No. 12/895,785 titled “Advanced Transistors With Threshold Voltage Set Dopant Structures”, the disclosures of which are hereby incorporated herein by reference in their entirety.

As shown in FIGS. 1 and 2, a transistor 100 is built on a substrate 102 and includes an isolation structure 104, a gate electrode 142, a gate dielectric 140, source/drain 106, a gate spacer 144 separating the source/drain 106 from the gate electrode 142, lightly doped drains (LDD) 108, and a substantially undoped silicon channel layer 110 that can be epitaxially grown/deposited. Typically, the LDD 108 are implanted following the formation of the gate stack, followed by gate spacer 144 formation and then implant or, alternatively, selective epitaxial deposition of deep source/drain regions 106. The transistor 100 shown in FIG. 1 is an NMOS deeply depleted channel (DDC) transistor, while FIG. 2 illustrates a complementary PMOS DDC transistor 101 supported on the same substrate. Each transistor 100 and 101 has a substantially undoped channel formed in a common blanket epitaxial layer 110, but differing in dopant types and implant energies. With suitable changes to account for differences in dopants, structures and processes for the NMOS and PMOS transistors 100 and 101 are similar and are discussed together in the following where appropriate.

With reference to FIG. 1, the NMOS transistor 100 includes a screen layer 120. In certain embodiments, the screen layer 120 is formed by implanting dopants into a P-well (not shown) formed on the substrate 102. In alternative embodiments, the screen layer 120 is formed on the P-well using methods such as in-situ doped epitaxial silicon deposition or epitaxial silicon deposition followed by dopant implantation. The screen layer 120 formation step occurs preferably before shallow trench isolation (STI) formation, but can be implemented after STI. Boron (B), Indium (I), or other P-type materials may be used for P-type screen implants (as shown with reference to the screen layer 120 in FIG. 1). Arsenic (As), antimony (Sb), phosphorous (P), and other N-type materials can be used for N-type screen implants (as shown with reference to the screen layer 120 in FIG. 2). In certain embodiments, the screen layer 120 has a dopant concentration between about 1×10¹⁹ to 5×10²⁰ dopant atoms/cm³, with the selected dopant concentration dependent on the desired threshold voltage as well as other desired transistor characteristics.

As shown in FIG. 1, an anti-punchthrough (APT) suppression layer 122 may optionally be formed beneath the screen layer 120. The APT suppression layer 122 can help reduce junction leakage. The APT suppression layer 122 can be separated from the screen layer 120 (e.g., the screen layer 120 as shown in FIG. 1) or it may contact the screen layer 120 (e.g., the screen layer 120 as shown in FIG. 2). Typically, the APT suppression layer 122 can be formed by direct implant into a lightly doped well, by out-diffusion from the screening layer 120, in-situ growth, or other known process. The APT suppression layer 122 has a dopant concentration less than the screening layer 120, typically set between about 1×10¹⁷ dopant atoms per cm³ and about 1×10¹⁹ dopant atoms per cm³. In addition, the APT suppression layer 122 dopant concentration is set higher than the overall dopant concentration of the substrate 102 or the well in which the transistor is formed.

In certain embodiments, an optional threshold voltage set layer is formed above the screen layer 120, typically formed as a thin doped layer. The threshold voltage set layer can be either adjacent to, incorporated within, or vertically offset from the screen layer 120. In certain embodiments, the threshold voltage set layer is formed by implantation prior to the formation of the undoped epitaxial layer 110. In alternative embodiments, the threshold voltage set layer can be formed by way of controlled out-diffusion of dopant material from the screen layer 120 into an undoped epitaxial layer, controlled in-situ doped epitaxial deposition either as part of screen layer 120 formation or separate from the formation of the screen layer 120, controlled formation before the substantially undoped epitaxial layer 110 is formed, or by implant after the substantially undoped epitaxial layer 110 is formed. Setting of the threshold voltage for the transistor is implemented by suitably selecting dopant concentration and depth of the threshold voltage set layer as well as maintaining a separation of the threshold voltage set layer from the gate dielectric 140, leaving a substantially undoped channel layer 110 directly adjacent to the gate dielectric. In certain embodiments, the threshold voltage set layer has a dopant concentration between about 1×10¹⁷ dopant atoms/cm³ and about 1×10¹⁹ dopant atoms per cm³. In alternative embodiments, the threshold voltage set layer has a dopant concentration that is approximately less than half of the concentration of dopants in the screen layer 120.

The channel layer 110 contacts and extends between the source/drain 106 and supports movement of mobile charge carriers between the source and the drain. In certain embodiments, the channel layer 110 is formed above the screen layer 120 and threshold voltage set layer (the screen layer 120, threshold voltage set layer, and APT suppression layer 122 are also referred to as well implant layers) by way of a blanket or selective silicon EPI deposition, resulting in an intrinsic substantially undoped channel layer 110 of a thickness tailored to the technical specifications of the device. As a general matter, the thickness of the substantially undoped channel layer 110 ranges from approximately 5-30 nm, with the selected thickness based upon the desired threshold voltage and other transistor performance metrics for the transistor and transistor design node (i.e. a 20 nm gate length transistor may typically have a thinner channel thickness than a 45 nm gate length transistor). Preferably, the substantially undoped channel region 110 has a dopant concentration less than 5×10¹⁷ dopant atoms per cm³ adjacent or near the gate dielectric 140. In some embodiments, the substantially undoped channel layer 110 may have a dopant concentration that is specified to be approximately less than one tenth of the dopant concentration in the screen layer 120. In still other embodiments, depending on the transistor characteristics desired, the substantially undoped channel layer 110 may contain dopants so that the dopant concentration is elevated to above 5×10¹⁷ dopant atoms per cm³ adjacent or near the gate dielectric 140. Preferably, the substantially undoped channel layer 110 remains substantially undoped by avoiding the use of halo or other channel implants. In one embodiment, the channel layer 110 is formed by a blanket (or selective) epitaxial deposition step that is performed after forming the screen layer 120.

The isolation structure 104 of FIGS. 1 and 2 can be formed through STI structures that are etched and filled with a dielectric material. In certain embodiments, STI structures are preferably formed after the blanket EPI deposition step, using a process that remains within a thermal budget that effectively avoids substantial change to the dopant profiles of the previously formed screen layer 120 and threshold voltage set layer.

In operation, when gate electrode 142 voltage is applied to the transistor 100 at a predetermined level, a depletion region formed in the substantially undoped channel layer 110 may extend to the screen layer 120. The screen layer 120, if fabricated according to specification, effectively pins the depletion region to define the depletion zone depth.

The threshold voltage (Vt) in conventional field effect transistors (FETs) can be set by directly implanting a “threshold voltage implant” into the channel, raising the threshold voltage to an acceptable level that reduces transistor off-state leakage while still allowing speedy transistor switching. Alternatively, the threshold voltage in conventional FETs can also be set by a technique variously known as “halo” implants, high angle implants, or pocket implants. Such implants create a localized graded dopant distribution near a transistor source and drain that extends a distance into the channel. Halo implants are often required by transistor designers who want to reduce unwanted source/drain leakage conduction or “punch through” current and other short channel effects, but have the added advantage of adjusting the threshold voltage. Unfortunately, halo implants introduce additional process steps, thereby increasing the manufacturing cost. Also, halo implants can introduce additional dopants in random unwanted locations in the channel. These additional dopants increase the variability of the threshold voltage between transistors and decrease mobility and channel transconductance due to the adverse effects of additional and unwanted dopant scattering centers in the channel. Eliminating or greatly reducing the halo implants is desirable for reducing manufacture time and making more reliable wafer processing. By contrast, the techniques for forming the transistor 100 use different threshold voltage setting techniques that do not rely on halo implants (i.e. haloless processing) or channel implants to set the threshold voltage to a desired range. By maintaining a substantially undoped channel near the gate, these transistors further allow for greater channel mobility for electron and hole carriers with reduced variation in threshold voltage from device to device.

As will also be appreciated, position, concentration, and thickness of the screen layer 120 are important factors in the design of the DDC transistor 100. In certain embodiments, the screen layer 120 is located above the bottom of the source and drain junctions 106 and below the LDD junctions 108. To dope the screen layer 120 so as to cause its peak dopant concentration to define the edge of the depletion width when the transistor is turned on, methods such as delta doping, conventional dopant implants, or in-situ doping is preferred, since the screen layer 120 should have a finite thickness to enable it to adequately screen the well while avoiding creating a path for excessive junction leakage. With such a screen layer 120, the transistor 100 can simultaneously have good threshold voltage matching, low junction leakage, good short channel effects, and still have an independently controllable body due to a strong body effect. In addition, multiple transistors having different threshold voltages can be easily implemented by customizing the position, thickness, and dopant concentration of the threshold voltage set layer and/or the screen layer 120 while at the same time achieving a reduction in the threshold voltage variation.

In one embodiment, the screen layer 120 is positioned such that the top surface of the screen layer 120 is located approximately at a distance of Lg/1.5 to Lg/5 below the gate dielectric 140 (where Lg is the gate length). In one embodiment, the threshold voltage set layer has a dopant concentration that is approximately 1/10 of the screen layer 120 dopant concentration. In certain embodiments, the threshold voltage set layer is thin so that the combination of the threshold voltage set layer and the screen layer 120 is located approximately within a distance of Lg/1.5 to Lg/5 below the gate dielectric 140.

Modifying threshold voltage by use of a threshold voltage set layer positioned above the screen layer 120 and below the substantially undoped channel layer 110 is an alternative technique to conventional threshold voltage implants for adjusting threshold voltage. Care must be taken to prevent dopant migration into the substantially undoped channel layer 110, with the use of low temperature anneals and dopant anti-migration techniques being recommended for many applications. More information about the formation of the threshold voltage set layer is found in pending U.S. application Ser. No. 12/895,785, the entirety of which is hereby incorporated herein by reference.

Dopant migration resistant implants or layers of carbon, pre-amorphization implants, or the like, can be applied below, along with, or above the screen layer 120 to further limit dopant migration. In FIG. 1, the extent of carbon implants is generally indicated to extend through the screen layer 120 and may extend upward through either part of or all of the channel 110. Germanium pre-amorphization implants are generally indicated to extend from above the NMOS screen layer 120 downward past the APT suppression layer 122. For DDC devices that utilize a pre-amorphization layer and SPE anneal, the screening layer 120, the threshold voltage set layer, and the APT suppression layer 120 (the screen layer 120, threshold voltage set layer, and APT suppression layer 122 are also referred to as well implant layers) can all be affected by remaining germanium end of range (EOR) damage that can include dislocations, high interstitial injection, and other crystal defects to cause unwanted migration of boron or other dopant atoms through the damaged area.

Reducing unwanted damage effects while maintaining desired dopant profiles is possible with use of the following disclosed structures and processes. FIG. 3 generally illustrates a portion of a NMOS transistor 200 having a screen layer 220 and a substantially undoped channel layer 210 that are similar to corresponding layers of transistor 100 in FIG. 1 but formed without the use of Ge PAI. The transistor 200 instead utilizes in-situ carbon doped silicon substrate in which the well implant layers are formed in order to limit NMOS screen layer 220 diffusion. The transistor 200 includes an NMOS APT suppression layer 222, a NMOS screen layer 220 formed in the carbon doped silicon substrate and positioned above the NMOS APT suppression layer 222, and a substantially undoped channel layer 210. In one embodiment, carbon doped silicon is in-situ grown as an epitaxial layer on the substrate forming a carbon doped silicon substrate into which the NMOS screen layer 220 dopants are subsequently implanted so as to form the NMOS screen layer 220 within the carbon doped silicon substrate. The carbon dopants in the in-situ doped silicon substrate occupy substitutional sites, thereby reducing unwanted diffusion of NMOS screen layer 220 dopants and maintaining desired dopant profiles. As shown FIG. 3, some carbon dopants can diffuse into the substantially undoped channel layer 210 during subsequent process steps that form remaining elements of the transistor 200, e.g. during gate formation and/or source/drain 206 formation.

FIG. 4 generally illustrates a portion of the PMOS transistor 201 that can be formed on the same substrate as the NMOS transistor 200 depicted in FIG. 3. More specifically, this transistor 201 has added to its structure in-situ carbon doped silicon that is grown in the same process steps as for forming the carbon doped silicon substrate of FIG. 3. The transistor 201 includes a PMOS APT suppression layer 222, a PMOS screen layer 224 formed in the carbon doped silicon substrate and positioned above the PMOS APT suppression layer 222, and a substantially undoped channel layer 210. The transistor 201 utilizes the in-situ carbon doped silicon substrate to limit PMOS screen layer 220 diffusion. In one embodiment, the carbon doped silicon for the PMOS transistor 201 can be grown at the same time the carbon doped silicon for NMOS transistor 200 and PMOS screen layer 220 is formed, resulting in the carbon doped silicon substrate for the PMOS transistor 201. In one embodiment, the carbon doped silicon is in-situ grown as an epitaxial layer on the substrate 202 forming a carbon doped silicon substrate into which the PMOS screen layer 220 dopants are subsequently implanted so as to form the PMOS screen layer 220 within the carbon doped silicon substrate. The carbon dopants in the in-situ carbon doped silicon substrate occupy substitutional sites, thereby reducing unwanted diffusion of PMOS screen layer 220 dopants and maintaining desired dopant profiles. As shown in FIG. 4, some carbon dopants can diffuse into the substantially undoped channel layer 210 during subsequent process steps to form remaining elements of the transistor 201, e.g. gate formation or source/drain 206 formation.

The PMOS transistor 201 has carbon dopants in the PMOS screen layer 220 because the carbon doped silicon substrate is formed as a blanket epitaxial layer that is formed over both the NMOS and PMOS transistor regions 200 and 201 during the same process step. However, the carbon doping may be eliminated for the PMOS transistors 201 if the PMOS screen layer 220 is formed using dopants having a low diffusivity such that the diffusion of PMOS screen layer 220 dopant profile can be maintained without using carbon. Not using carbon in such embodiments can be advantageous because the carbon atoms can result in reduced mobility of the charge carriers and, therefore, affect the electrical characteristics of the PMOS transistor 201. Therefore, in alternative embodiments that use selective epitaxial layers to form the PMOS and NMOS screen layers 220, the PMOS transistors 201 can use a slow diffusing dopant species (such as As or Sb) to form the PMOS screen layer 220 and not have any carbon, while the NMOS transistors 200 can still use carbon to reduce the diffusion of NMOS screen layer 220 dopants.

FIG. 5 is an illustration of another variation of an NMOS transistor 300 having no incorporated germanium pre-amorphization implants, but with an in-situ epitaxial carbon doped silicon layer 330 positioned above the NMOS screen layer 320 to limit the diffusion of dopants from the screen layer 320. The transistor 300 also includes a NMOS APT suppression layer 322 and a NMOS screen layer 320 that are formed in the substrate 302 or in a doped well in the substrate 302. In one embodiment, the carbon doped silicon layer 330 is formed as an in-situ doped blanket epitaxial layer and is typically a thin layer that is 5-50 nm thick. The carbon dopants in the in-situ doped epitaxial layer 330 occupy substitutional sites, thereby reducing unwanted diffusion of NMOS screen layer 320 dopants and maintaining desired dopant profiles. Typically, the carbon doped silicon layer 330 reduces the diffusion of NMOS screen layer 320 dopants by protecting the NMOS screen layer 320 from interstitials generated above the NMOS screen layer 320, e.g., at the gate dielectric 340. As shown in FIG. 5, the substantially undoped channel layer 310 is formed above the carbon doped silicon layer 330. In one embodiment, the substantially undoped channel layer 310 is formed as a blanket epitaxial layer. In certain embodiments, the thickness of the carbon doped silicon layer 330 can range from as little as 5 nm up to the full thickness of the substantially undoped channel layer 310. In one embodiment, the thickness of the carbon doped silicon layer 330 is selected to be sufficient to trap interstitials generated from the gate dielectric 340.

FIG. 6 generally illustrates a portion of the PMOS transistor 301 that can be formed on the same substrate as the NMOS transistor 300 depicted in FIG. 5. The transistor 301 includes a PMOS APT suppression layer 322, a PMOS screen layer 320 positioned above the PMOS APT suppression layer 322, a carbon doped silicon layer 330 is formed above the NMOS screen layer 320, and a substantially undoped channel layer 310 formed above the carbon doped silicon layer 330. The PMOS APT suppression layer 322, and the PMOS screen layer 320 are formed by implanting dopants in the substrate 302 or in a doped well in the substrate 302. The carbon doped silicon layer 330 can be formed as a blanket epitaxial layer that is formed over both the NMOS transistor 300 and the PMOS transistor 301 during the same process step. The carbon doped silicon layer 330 is formed above the NMOS and PMOS screen layers 320. The carbon dopants in the in-situ doped epitaxial layer 330 occupy substitutional sites, thereby reducing unwanted diffusion of PMOS screen layer 320 dopants and maintaining desired dopant profiles. Typically, the carbon doped silicon layer 330 reduces the diffusion of PMOS screen layer 320 dopants by protecting the PMOS screen layer 320 from interstitials generated above the PMOS screen layer 320, e.g., at the gate dielectric 340. As shown in FIG. 6, the substantially undoped channel layer 310 is formed above the carbon doped silicon layer 330. In one embodiment, the substantially undoped channel layer 310 can also be a blanket epitaxial layer that is formed over both the PMOS transistor 301 and the NMOS transistor 300 during the same process steps. In alternative embodiments, where low diffusivity dopant species are used to form the PMOS screen layer 320, the carbon doped silicon layer 330 may not be desired. Such alternative embodiments can use selective epitaxy from the carbon doped silicon layer 330 above the NMOS screen layer 320 without forming the carbon doped silicon layer 330 above the PMOS screen layer 320, resulting in a PMOS transistor 301 that does not have any carbon dopants.

FIG. 7 is an illustration of an NMOS transistor 400 having no incorporated germanium pre-amorphization implants, but with an in-situ epitaxial carbon doped silicon layer 430 positioned above the screen layer 420 and a deep carbon implant layer 432 positioned below the screen layer 420 to limit the diffusion of dopants from the screen layer 420. The transistor 400 can be formed by implanting a NMOS APT suppression layer 422 in the substrate 402 or in a doped well in the substrate 402. Subsequently, carbon can be implanted to form the deep carbon implant layer 432, which is followed by an implant step that forms the NMOS screen layer 420. Since the deep carbon implant layer 432 protects the NMOS screen layer 420 from interstitials generated below the screen layer 420, it is typically positioned close to the NMOS screen layer 420. However, it can also be positioned below the NMOS screen layer 420 (such as between the NMOS screen layer 420 and the NMOS APT suppression layer 422), below the NMOS APT suppression layer 420, or above the source of interstitials below the NMOS screen layer 420. Thus, one layer of carbon 430 is an in-situ doped silicon layer epitaxially grown above the screen layer 420 and the other layer of carbon 432 is a deep carbon implant layer positioned below the screen layer 420. The positioning of deep carbon implant layer 432 in relation to in-situ epitaxial carbon doped silicon layer 430 (i.e. the distance between these layers and depth within the substrate 302) may be determined based on a desired threshold voltage for the NMOS transistor 400. In alternative embodiments, fluorine can be implanted instead of carbon to form the deep implant layer 432. The use of fluorine instead of carbon can be advantageous because fluorine can be fully activated with a normal spike anneal, while carbon may only be partially activated.

Referring to FIG. 7, the carbon doped silicon layer 430 is formed above the NMOS screen layer 420 and a substantially undoped channel layer 410 is formed above the carbon doped silicon layer 430. Formation of a complimentary PMOS transistor, though not shown, may similarly be performed as PMOS transistors 101, 201, and 301 discussed above with the additional features as discussed in FIG. 7. In one embodiment, the substantially undoped channel layer 410 and/or the carbon doped silicon layer 430 is formed as a blanket epitaxial layer that is formed over both a PMOS transistor and NMOS transistors 400 formed on the same substrate 402 during the same process steps. Typically, the carbon doped silicon layer 430 protects the NMOS screen layer 420 from interstitials generated above the NMOS screen layer 420, e.g., at the gate dielectric 440, and the deep carbon implant layer 432 protects the NMOS screen layer 420 from interstitials generated below the deep carbon implant layer 432. In one embodiment, where the PMOS screen layer of the PMOS transistor (not shown) is formed using a slow diffusing dopant species, the deep carbon implant layer can be formed only for the NMOS transistor 400, and the PMOS transistor may not have a deep carbon implant layer positioned below the PMOS screen layer. In such embodiments, the carbon doped silicon layer 430 may not be desired for the PMOS transistor. Therefore, the carbon doped silicon layer 430 can be formed as a selective epitaxial layer that is formed only above the NMOS screen layer 420 and not above the PMOS screen layer, resulting in a PMOS transistor that does not have any carbon dopants. In various embodiments, only one carbon doped layer (i.e., either the deep carbon implant layer 432 or the carbon doped silicon layer 430) can be used to protect the NMOS screen layer 420 or both carbon doped layers can be used (as illustrated in FIG. 7).

FIG. 8 is an illustration of an NMOS transistor 500 having no incorporated germanium pre-amorphization implants, but with a deep in-situ epitaxial carbon doped silicon formed in the substrate 502 to extend throughout the screen layer 520, an in-situ epitaxial carbon doped silicon layer 530 formed between the screen layer 520 and the substantially undoped channel 510, and a deep carbon implant layer 532 positioned below the screen layer 520 to limit the diffusion of dopants from the screen layer 520. The transistor 500 includes a NMOS APT suppression layer 522 that is formed by implanting dopants in a substrate 502 or a doped well in the substrate 502. After forming the NMOS APT suppression layer 522, carbon can be implanted to form the deep carbon implant layer 532. Thus, one use of carbon is in-situ carbon doped silicon epitaxially grown over the substrate 502 to create a carbon doped substrate region within which the device well implant layers can be formed. The second use of is a deep carbon implant layer 532 positioned below the screen layer 520. The third use of carbon is an in-situ carbon doped silicon layer 530 epitaxially grown above the screen layer 520. The positioning of deep carbon implant layer 532 in relation to in-situ epitaxial carbon doped silicon layer 530 (i.e. the distance between these layers and depth within the substrate 502) may be determined based on a desired threshold voltage for the NMOS transistor 500. In alternative embodiments, fluorine can be implanted instead of carbon to form the deep implant layer 532. In one embodiment, the deep in-situ carbon doped silicon is grown as an epitaxial layer on the substrate 502 forming a carbon doped silicon substrate into which the NMOS screen layer 520 dopants are subsequently implanted so as to form the NMOS screen layer 520 within the carbon doped silicon substrate. The carbon dopants in the carbon doped silicon substrate occupy substitutional sites, thereby reducing unwanted diffusion of NMOS screen layer 520 dopants and maintaining desired dopant profiles. The thin carbon doped silicon layer 530 is formed above the NMOS screen layer and a substantially undoped channel layer 510 is formed above the carbon doped silicon layer 530. In one embodiment, the substantially undoped channel layer 510 and/or the carbon doped silicon layer 530 can be formed as a blanket epitaxial layer that is formed over both a PMOS transistor (not shown) and NMOS transistor 500 formed on the same substrate 502 during the same process steps. In one embodiment, where the PMOS screen layer of the PMOS transistor is formed using a slow diffusing dopant species, the deep carbon implant layer can be formed only for the NMOS transistor 500, and the PMOS transistor may not have a deep carbon implant layer positioned below the PMOS screen layer. In such embodiments, the carbon doped silicon layer 530 and the carbon doped silicon substrate may not be desired for the PMOS transistor. Therefore, the carbon doped silicon layer 530 and the carbon doped silicon substrate can be formed as selective epitaxial layers that are formed only for the NMOS transistor 500 and not for the PMOS transistor, resulting in PMOS transistors that do not have any carbon dopants.

FIG. 9 illustrates several embodiments of a process 900 that can be used to produce structures of the present disclosure. As shown in step 905, carbon doped silicon can be in-situ grown as an epitaxial layer, forming a carbon doped silicon substrate area into which the DDC transistor can subsequently be fabricated. Embodiments of DDC transistors that are formed in a carbon doped substrate area have been described previously with reference to FIGS. 3, 4, and 8. In one embodiment, the in-situ carbon doped silicon can be grown on single wafers using chemical vapor deposition at temperatures in the range of 550° C.-800° C. and pressures in the range of 10-400 torr (T), at atmospheric pressure, or in a system pressurized to exceed atmospheric pressure, using a H₂ carrier gas in the range of 20-40 standard liters per minute (slm) with a silicon source such as SiH₄ or Si₂H₆ in the range of 50-100 standard cubic centimeter per minute (sccm) and a carbon source such as CH₃SiH₃ or C₂H₄ in the range of 10-50 sccm, where the mole fraction of the carbon source in H₂ can be in the range of 0.1% to 1%). In an alternative embodiment, the in-situ carbon doped silicon can be grown in a batch UHVCD furnace at 450-750° C. and 1-100 mT temperature and pressure, respectively, using an ambient such as He, H2, N2, or Ar. The silicon source can be SiH₄ or Si₂H₆ in the range of 1-50 sccm and the carbon source can be CH₃SiH₃ or C₂H₄ in the range of 1-10 sccm, where the mole fraction of the carbon source in H₂ can be in the range of 0.01% to 1%). In certain embodiments, the thickness of the in-situ carbon doped silicon can range between 20-100 nm. Typically the thickness of the in-situ carbon doped silicon is selected to be greater than the thickness of the PMOS screen layer to be formed, so that the PMOS screen layer is formed entirely within the in-situ carbon doped silicon. For example, if the PMOS screen layer thickness is 30 nm, the thickness of the carbon doped silicon can be selected to be 40 nm.

In step 910, a PMOS mask is photolithographically patterned on a wafer, which is then used in step 915 to form the PMOS well. In one embodiment, phosphorus (P) is implanted at 200-400 keV and at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm² to form the PMOS well. In steps 920 and 925, respectively, the PMOS APT suppression layer and the PMOS screen layer are formed. The PMOS well implant and/or the PMOS APT suppression layer implant can be done either directly into the in-situ carbon doped silicon or it can be directed to form a doped region below the in-situ carbon doped silicon. However, the PMOS screen implant is done directly into the in-situ carbon doped silicon layer so that the PMOS screen layer is formed within this substrate region. In one embodiment, arsenic (As) is implanted at 50-200 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOS APT suppression layer and antimony (Sb) is implanted at 10-50 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOS screen layer. The PMOS mask is removed at step 930 and an NMOS mask is formed at step 935. In step 940, the NMOS mask is used to form the NMOS well. In one embodiment, boron (B) is implanted at approximately 100-250 keV, at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm² to form the NMOS well. In step 945, the NMOS APT suppression layer is implanted in the NMOS well. In one embodiment additional B is implanted at 15-40 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the shallow NMOS APT suppression layer.

In step 950 carbon is optionally implanted to form a deep carbon implant layer that is positioned between the NMOS screen layer and the NMOS APT layer. Embodiments of DDC transistors having a deep carbon implant layer have been described previously with reference to FIGS. 7 and 8. In one embodiment, carbon can be implanted at 20-60 keV at doses in the range of 1×10¹⁴ to 1×10¹⁵ atoms/cm² to form the deep carbon implant layer. In step 955, the NMOS screen layer is formed, which is followed by a 900° C.-1250° C. RTP/laser well anneal in step 960 and removal of the NMOS mask in step 965. In one embodiment, B is implanted at 0.5 to 10 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the NMOS screen layer. Typically the implant conditions for the NMOS screen layer are selected such that the NMOS screen layer is formed within the carbon doped silicon substrate formed in step 905 (if present), and positioned above the deep carbon implant layer formed in step 950. Since the deep carbon implant layer protects the NMOS screen layer from interstitials generated below the screen layer, it is typically positioned either close to the NMOS screen layer or above the source of interstitials below the screen layer. In alternative embodiments, fluorine can be implanted instead of carbon to form the deep implant layer. The use of fluorine instead of carbon can be advantageous because fluorine can be fully activated with a normal spike anneal, while carbon may only be partially activated. In one embodiment, shown in step 970, a blanket epitaxial layer of substantially undoped silicon is grown, such that the substantially undoped silicon layer is formed over the screen layers of both the NMOS and PMOS transistors. In certain other embodiments, shown in steps 975 and 980, respectively, an intermediate blanket epitaxial carbon doped silicon layer can be grown followed by a blanket epitaxial layer of substantially undoped silicon. Typically thin (about 5-10 nanometers or so), the carbon doped silicon layer formed at step 975 can act to reduce diffusion of dopants from the screen layer into the substantially undoped epitaxial layer and it can also consume unwanted silicon interstitials generated above the screen layer and to further reduce boron diffusion in the device structure. In one embodiment, the blanket epitaxial layer grown in step 980 can have a thickness that is approximately in the range of 5-40 nanometers. Embodiments of DDC transistors having an in-situ epitaxial carbon doped silicon layer positioned above the screen layer have been described previously with reference to FIGS. 5-8.

Various embodiments of the process 900 can include some but not all of the process steps for forming one or more of the carbon doped silicon layers described above, i.e. steps 905, 950, and 975. In one such embodiment, step 905 is performed so that the DDC transistors are formed in a silicon substrate with carbon dopants, while steps 950 and 975 are performed to form the deep carbon implant layer below the screen layer and the thin in-situ carbon doped silicon layer above the screen layer, respectively. In alternative embodiments, only one of the steps 905, 950, and 975 are performed such that only one carbon doping is used to limit the diffusion of screen layer dopants. In other embodiments, all three of these steps are performed, such that three carbon dopings are used to limit the diffusion of screen layer dopants.

FIG. 10 illustrates several embodiments of a process 1000 where the STI structures are formed before forming the DDC transistor elements. The process 1000 can use selective epitaxy in place of the blanket epitaxy steps described above with reference to the process 900 of FIG. 9 and can, therefore, eliminate additional steps for removing the unwanted silicon growth that would otherwise be formed over exposed dielectric structures, e.g. polysilicon that would be formed over STI elements if blanket epitaxy processing was utilized after STI formation. In one embodiment of the process 1000, as shown in step 1005, carbon doped silicon is in-situ grown as a blanket epitaxial layer, forming a carbon doped silicon substrate into which the DDC transistors can subsequently be fabricated. In an alternative embodiment, the substrate level carbon doped silicon growth step can be omitted and the DDC transistors can be formed in the silicon substrate or in a well in the silicon substrate. In one embodiment, the process conditions for forming the carbon doped silicon substrate in step 1005 are similar to the process conditions described above with reference to step 905 of FIG. 9.

In step 1007, the STI structures are optionally formed for an embodiment using an STI first process flow, thereby defining the areas where the NMOS and PMOS DDC transistors are to be formed. In an alternative embodiment using an STI last process flow, step 1007 can be omitted and STI structures are not formed at this stage of the process. In step 1010, a PMOS mask is lithographically patterned on the wafer, which is then used in step 1015 to form the PMOS well. In one embodiment, phosphorus (P) is implanted at 200-400 keV, at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm² to form the PMOS well. In steps 1020 and 1025, respectively, the PMOS APT suppression layer and the PMOS screen layer are formed. In one embodiment, arsenic (As) is implanted at 50-200 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOS APT suppression layer and antimony (Sb) is implanted at 10-50 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOS screen layer. The PMOS mask is removed at step 1030 and an NMOS mask is formed at step 1035. In step 1040, the NMOS mask is used to form the NMOS well. In one embodiment, boron (B) is implanted at approximately 100-250 keV, at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm² to form the NMOS well. In step 1045, the NMOS APT suppression layer is implanted in the NMOS well. In one embodiment, additional B is implanted at 15-40 keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the shallow NMOS APT suppression layer.

In step 1050, an optional deep carbon implant can be performed to implant carbon above the APT suppression layer, followed by step 1055 that forms the NMOS screen layer above the carbon implant region. The deep carbon implant layer formed in step 1050 can limit the diffusion of NMOS screen layer dopants by trapping interstitials generated below the screen layer. The deep carbon implant layer may be used in addition to or in lieu of the carbon doped silicon substrate formed in step 1005. Typically, either the deep carbon implant layer or the carbon doped silicon substrate is used in a particular embodiment, with the deep carbon implant layer being used when the DDC transistors are formed in a silicon substrate instead of the carbon doped silicon substrate. Thus, the step 1050 for forming the deep carbon implant layer can be omitted in certain embodiments of the process 1000. Step 1050 can result in a deep carbon implant that is positioned between the APT layer and the screen layer for the NMOS transistor, such that the deep carbon implant can limit the diffusion of NMOS screen layer dopants (such as boron). In one embodiment, carbon is implanted at 20-60 keV at concentrations in the range of 1×10¹⁴ to 1×10¹⁵ to form the deep carbon implant layer. In one embodiment, B is implanted at 0.5 to 10 keV at concentrations in the range of 5×10¹² to 5×10¹³ to form the NMOS screen layer. Typically, the implant conditions for the NMOS screen layer are selected such that the NMOS screen layer is formed within the carbon doped silicon substrate formed in step 1005 and positioned above the deep carbon implant layer formed in step 1050. Since the deep carbon implant layer protects the NMOS screen layer from interstitials generated below the screen layer, it is typically positioned either close to the NMOS screen layer or above the source of interstitials below the screen layer (e.g., an area where the lattice structure may be damaged). In alternative embodiments, fluorine can be implanted instead of carbon to form the deep implant layer. The use of fluorine instead of carbon can be advantageous because fluorine can be fully activated with a normal spike anneal, while carbon may only be partially activated. In step 1060, a 900° C.-1250° C. RTP/laser well anneal is performed.

In step 1065, the NMOS mask is removed and, in step 1068, an optional hardmask may be formed. The hardmask formed in step 1068 can be used to define the regions of the NMOS and PMOS transistors such that the STI islands are masked off in process embodiments that use an STI first process flow so that subsequent steps that form selective epitaxial layers for the NMOS and PMOS transistors do not form polysilicon over the STI islands. Moreover, the hardmask of step 1068 can be used to define transistors having a predetermined threshold voltage such that the subsequent steps that form epitaxial layers for the transistors can form selective epitaxial layers of different thicknesses for transistors having different threshold voltages. For example, epitaxial layers having different thicknesses can be formed for LVt transistors having a low threshold voltage and HVt transistors having a high threshold voltage, and different hardmasks can be formed to define the LVt and HVt transistor areas. In an alternative embodiment, different hardmasks can be formed to define the NMOS and PMOS transistor areas, permitting the use of different epitaxial layers for the NMOS and PMOS transistors. For example, a NMOS hardmask can be used to form carbon doped silicon epitaxial layers for the NMOS transistors and a PMOS hardmask can be used to form a substantially undoped epitaxial layer for the PMOS transistor so the PMOS transistors have no carbon dopants.

In one embodiment of the process 1000, shown in step 1070, a selective epitaxial layer of substantially undoped silicon is grown over the regions where the NMOS and PMOS transistors are to be formed. In an alternative embodiment, shown in steps 1075 and 1080 respectively, an intermediate selective epitaxial carbon doped silicon layer can be grown followed by a selective epitaxial layer of substantially undoped silicon. Typically thin (about 5-10 nanometers or so), the carbon doped silicon epitaxial layer formed at step 1075 can act to reduce diffusion of dopants from the screen layer into the substantially undoped epitaxial layer and it can also consume unwanted silicon interstitials to further reduce boron diffusion in the device structure. In one embodiment, the selective epitaxial layers grown in steps 1070 and 1074 can have a thickness that is approximately in the range of 5-40 nanometers. In certain embodiments, a hardmask can be formed in step 1068 to support the subsequent selective epitaxial deposition steps. For example, a hardmask defining the PMOS transistor regions can be used to perform step 1070 for the PMOS transistors and a different hardmask defining the NMOS transistor regions can be used to perform steps 1075 and 1080 for the NMOS transistor regions.

In one embodiment of the process 1000, the carbon implant layer and the carbon doped silicon substrate is formed only for the NMOS transistors while PMOS transistors are kept free of carbon. Such an embodiment can be advantageously used if low diffusivity dopant species are used to form the PMOS screen layer such that the dopant profile of the PMOS screen layer can be maintained without using carbon. Eliminating carbon in the PMOS transistor can be beneficial because the presence of carbon dopants can reduce the charge carrier mobility and may have an effect on transistor electrical characteristics. In order to accommodate this, the optional step 1005 is omitted such that the corresponding carbon doped silicon substrate is not formed. A selective silicon etch for the NMOS transistor regions is performed (step 1072) prior to forming the thin in-situ carbon doped silicon selective epitaxial layer (step 1073) for the NMOS transistors. The purpose of the selective etch for the NMOS transistors is to recess the silicon region of the NMOS transistors such that, after deposition of the carbon doped silicon substrate in step 1005, the NMOS transistor regions can have substantially the same step height as the PMOS transistor regions. Subsequently, a substantially undoped silicon epitaxial layer is grown as selective epitaxial layer in step 1074 such that a selective epitaxial layer is formed over the screen layers of both the NMOS and PMOS transistors.

In step 1085, a low temperature STI process step is performed to form STI structures for a process embodiment using an STI last process flow. In step 1090, remaining elements of the NMOS and PMOS transistors are formed, such as gate structures, source/drain implants, etc.

FIG. 11 illustrates a process 1100, where STI is processed after the screen and channel layers of the DDC transistors have been formed. The process flow 1100 utilizes additional steps to allow the carbon species to be limited to the NMOS device. In step 1110, a PMOS mask is lithographically patterned on a wafer, which is then used in step 1115 to form a PMOS well. In one embodiment, phosphorous is implanted at 200-400 keV to form the PMOS well. The PMOS APT suppression layer and the PMOS screen layer are formed in steps 1120 and 1125, respectively. In one embodiment, arsenic (As) can be implanted at 50-200 keV to form the PMOS APT suppression layer and antimony (Sb) can be implanted at 10-50 keV to form the PMOS screen layer. In steps 1130 and 1135, respectively, the PMOS mask is removed and an NMOS hard mask is formed.

Referring to FIG. 11, in step 1140, a selective silicon etch is performed in regions where the NMOS transistors are to be formed. The purpose of the selective silicon etch is to recess the silicon region of the NMOS transistors such that, after subsequent deposition of selective epitaxial layers for the NMOS transistors, the NMOS transistors regions can have substantially similar height as the PMOS transistor regions. In one embodiment, the selective silicon etch step 1140 is performed before the NMOS well implant and the NMOS screen implant in steps 1145 and 1150, respectively. In an alternative embodiment, the selective silicon etch step 1140 is performed after step 1145 and 1150. In one embodiment, Boron (B) is implanted at 100-250 keV to form the NMOS well and additional B is implanted at 15-40 keV to form a shallow NMOS APT suppression layer. If the depth of the selective silicon etchback is small compared to the depth of the NMOS well and NMOS APT suppression layers, then the NMOS well and NMOS APT suppression layer implant conditions are similar for the process embodiment that performs the NMOS selective well etch before step 1145, as compared to the embodiment that performs the NMOS selective well etch after step 1150. For example, similar implant conditions for the two embodiments are performed if the depth of the selective well etch is about 30 nm. Alternatively, the process embodiment that performs the NMOS selective well etch before step 1145 can use a lower implant energy for the NMOS well and NMOS APT suppression implants, as compared to the embodiment that performs the NMOS selective well etch after step 1150. In step 1155, NMOS selective epitaxial steps are performed to form the layers for the NMOS transistors. In accordance with various embodiments, these epitaxial steps can form an NMOS transistor stack that includes (a) a first selective epitaxial layer of carbon doped silicon, followed by a second selective epitaxial layer of silicon doped with carbon and NMOS screen layer dopants (such as boron), followed by a third selective epitaxial layer of thin carbon doped silicon that is formed above the second layer; or (b) a selective epitaxial layer of silicon doped with carbon and NMOS screen layer dopants to form a doped substrate layer; or (c) a selective epitaxial layer of carbon doped silicon to form a carbon doped substrate in which NMOS screen layer dopants are subsequently implanted.

In step 1160, a NMOS transistor threshold implant can be optionally performed, if the NMOS transistors have a threshold set region. In step 1170, the NMOS mask is removed, and in step 1175 various thermal processing steps can be performed, including at step 1175 a 500° C.-800° C. SPE or a 900° C.-1250° C. RTP well anneal. In step 1180, a blanket epitaxial layer of substantially undoped silicon is formed such that the epitaxial layer is formed over the screen layers of both the NMOS and PMOS transistors. In one embodiment, the blanket epitaxial layer can have a thickness that is approximately in the range of 5-40 nanometers. After formation of the DDC transistor elements (such as the well implant layers and the substantially undoped channel layer described above), a low temperature STI formation is performed at step 1185 followed by gate formation at step 1190. Remaining transistor process modules are performed to complete the formation of the DDC transistor.

Transistors created according to the foregoing embodiments, structures, and processes can have a reduced threshold voltage mismatch arising from diffusion mediated dopant variations as compared to conventional MOS analog or digital transistors. This is particularly important for transistor circuits that rely on closely matched transistors for optimal operation, including differential matching circuits, analog amplifying circuits, and many digital circuits in widespread use such as SRAM cells. Variation can be even further reduced by adoption of structures such as a screen layer, an undoped channel, or a Vt set layer as described herein to further effectively increase headroom which the devices have to operate. This allows high-bandwidth electronic devices with improved sensitivity and performance, but still having reduced power consumption.

The present disclosure discusses building the screen and channel of advanced transistors such as a deeply depleted channel (DDC) type transistor. However, the methods and techniques described above can also be used by one skilled in the art to improve the securement of dopant profiles in other transistor types or transistor features such as shallow lightly doped drains (LDD) and S/D regions in advanced transistors.

Although the present disclosure has been described in detail with reference to a particular embodiment, it should be understood that various other changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the appended claims. Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications.

Claims

1. A method for forming a plurality of FETs in a substrate, comprising: forming at least one PMOS FET; andforming at least one NMOS FET, the forming at least one NMOS FET includes: implanting a dopant to form an NMOS antipunchthrough layer;implanting a dopant to form an NMOS screen layer;forming a carbon-containing region above and below the NMOS screen layer, wherein the carbon-containing region is operable to substantially limit diffusion of the NMOS screen layer dopants;annealing using a low thermal budget anneal; anddepositing a substantially undoped epitaxial silicon layer on the carbon-containing region; andforming trench isolation structures to electrically isolate the plurality of FETs from one another.

2. The method of claim 1, wherein the carbon-containing region is formed using ion implantation.

3. The method of claim 1, wherein the annealing includes using solid phase epitaxy at a temperature of between 500 and 800 degrees Celsius.

4. The method of claim 1, wherein the annealing includes using a rapid thermal anneal at a temperature of between 900 and 1250 degrees Celsius.

5. The method of claim 1, wherein the depositing of the substantially undoped epitaxial silicon layer includes using selective epitaxial growth.

6. The method of claim 1, further comprising forming a threshold voltage set layer positioned between the NMOS screen layer and the substantially undoped epitaxial silicon layer.