Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same

Description

BACKGROUND

A push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The chip area reduction provides an economic benefit for migrating to newer technologies. The 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%. The reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers.

In the evolution of lithography, as the minimum feature size approached the wavelength of the light source used to expose the feature shapes, unintended interactions occurred between neighboring features. Today minimum feature sizes are approaching 45 nm (nanometers), while the wavelength of the light source used in the photolithography process remains at 193 nm. The difference between the minimum feature size and the wavelength of light used in the photolithography process is defined as the lithographic gap. As the lithographic gap grows, the resolution capability of the lithographic process decreases.

An interference pattern occurs as each shape on the mask interacts with the light. The interference patterns from neighboring shapes can create constructive or destructive interference. In the case of constructive interference, unwanted shapes may be inadvertently created. In the case of destructive interference, desired shapes may be inadvertently removed. In either case, a particular shape is printed in a different manner than intended, possibly causing a device failure. Correction methodologies, such as optical proximity correction (OPC), attempt to predict the impact from neighboring shapes and modify the mask such that the printed shape is fabricated as desired. The quality of the light interaction prediction is declining as process geometries shrink and as the light interactions become more complex.

In view of the foregoing, a solution is needed for managing lithographic gap issues as technology continues to progress toward smaller semiconductor device features sizes.

SUMMARY

In one embodiment, an integrated circuit is disclosed to include a first gate electrode feature of a first gate electrode track. The first gate electrode feature of the first gate electrode track forms a first n-channel transistor as it crosses an n-diffusion region. The integrated circuit also includes a second gate electrode feature of the first gate electrode track. The second gate electrode feature of the first gate electrode track forms a first p-channel transistor as it crosses a p-diffusion region. The first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing. The integrated circuit also includes a first gate electrode feature of a second gate electrode track. The first gate electrode feature of the second gate electrode track forms a second n-channel transistor as it crosses the n-diffusion region. The integrated circuit also includes a second gate electrode feature of the second gate electrode track. The second gate electrode feature of the second gate electrode track forms a second p-channel transistor as it crosses the p-diffusion region. The first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing such that a line of sight perpendicular to the first and second gate electrode tracks does not exist through the first and second end-to-end spacings.

In another embodiment, a cell of a semiconductor device is disclosed. The cell includes a substrate portion formed to include a plurality of diffusion regions. The plurality of diffusion regions respectively correspond to active areas of the substrate portion within which one or more processes are applied to modify one or more electrical characteristics of the active areas of the substrate portion. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion.

Also in this embodiment, the cell includes a gate electrode level of the cell formed above the substrate portion. The gate electrode level includes a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size measured in the first parallel direction. The size of each end-to-end spacing between originating layout features corresponding to adjacent ones of the number of conductive features within the gate electrode level of the cell is substantially equal and is minimized to an extent allowed by a semiconductor device manufacturing capability. The number of conductive features within the gate electrode level of the cell includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level of the cell.

A width size of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction. The width size of the conductive features within a photolithographic interaction radius within the gate electrode level is less than a wavelength of light used in a photolithography process to fabricate the conductive features within the gate electrode level. The wavelength of light used in the photolithography process is less than or equal to 193 nanometers. The photolithographic interaction radius is five wavelengths of light used in the photolithography process.

Some of the number of conductive features within the gate electrode level of the cell are defined to include one or more gate electrode portions which extend over one or more of the active areas of the substrate portion corresponding to the plurality of diffusion regions. Each gate electrode portion and a corresponding active area of the substrate portion over which it extends together define a respective transistor device.

Also in this embodiment, the cell includes a number of interconnect levels formed above the gate electrode level of the cell. The substrate portion, the gate electrode level of the cell, and the number of interconnect levels are spatially aligned such that structures fabricated within each of the substrate portion, the gate electrode level of the cell, and the number of interconnect levels spatially relate to connect as required to form functional electronic devices within the semiconductor device.

In one embodiment, a semiconductor chip includes a region including a plurality of transistors, where each of the plurality of transistors in the region forms part of circuitry associated with execution of one or more logic functions. The region includes at least ten conductive structures formed within the semiconductor chip, where some of the at least ten conductive structures form at least one transistor gate electrode. Each of the at least ten conductive structures respectively has a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end. The total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end. The total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end. The total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end. The total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end. The corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges. The corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges. The top surfaces of the at least ten conductive structures are co-planar with each other. Each of the at least ten conductive structures has a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end. Each of the at least ten conductive structures has a length as measured along its lengthwise centerline from its first end to its second end. The first edge of each of the at least ten conductive structures is substantially straight. The second edge of each of the at least ten conductive structures is substantially straight. Each of the at least ten conductive structures has both its first edge and its second edge oriented substantially parallel to its lengthwise centerline. Each of the at least ten conductive structures has a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline. Each of the first direction and the second direction is oriented substantially parallel to the co-planar top surfaces of the at least ten conductive structures. The at least ten conductive structures are positioned in a side-by-side manner such that each of the at least ten conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least ten conductive structures. The width of each of the at least ten conductive structures is less than 45 nanometers. The region has a size of about 965 nanometers as measured in the second direction. Each of the at least ten conductive structures is positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least ten conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers. The at least ten conductive structures includes a first conductive structure. The first conductive structure includes a portion that forms a gate electrode of first transistor of a first transistor type. The first conductive structure also includes a portion that forms a gate electrode of a first transistor of a second transistor type. The at least ten conductive structures includes a second conductive structure. The second conductive structure includes a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type. The at least ten conductive structures includes a third conductive structure. The third conductive structure includes a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type. The at least ten conductive structures includes a fourth conductive structure. The fourth conductive structure includes a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type. The at least ten conductive structures includes a fifth conductive structure. The fifth conductive structure includes a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type. The first transistor of the first transistor type includes a first diffusion terminal. The second transistor of the first transistor type includes a first diffusion terminal. The first diffusion terminal of the first transistor of the first transistor type is electrically connected to the first diffusion terminal of the second transistor of the first transistor type through a first electrical connection. The first transistor of the second transistor type includes a first diffusion terminal. The second transistor of the second transistor type includes a first diffusion terminal. The first diffusion terminal of the first transistor of the second transistor type is electrically connected to the first diffusion terminal of the second transistor of the second transistor type through a second electrical connection. The second transistor of the first transistor type includes a second diffusion terminal. The third transistor of the first transistor type includes a first diffusion terminal. The second diffusion terminal of the second transistor of the first transistor type is electrically connected to the first diffusion terminal of the third transistor of the first transistor type through a third electrical connection. The second transistor of the second transistor type includes a second diffusion terminal. The third transistor of the second transistor type includes a first diffusion terminal. The second diffusion terminal of the second transistor of the second transistor type is electrically connected to the first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection. The third transistor of the first transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the first transistor type through a fifth electrical connection. The third transistor of the second transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the second transistor type through a sixth electrical connection. The third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection. The gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection. The gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type through a ninth electrical connection. Each transistor of the first transistor type having its gate electrode formed by any of the at least ten conductive structures is included in a first collection of transistors. Each transistor of the second transistor type having its gate electrode formed by any of the at least ten conductive structures is included in a second collection of transistors. The first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region. The inner sub-region does not include a source or a drain of any transistor.

Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 2 is an illustration showing a generalized stack of layers used to define a dynamic array architecture, in accordance with one embodiment of the present invention;

FIG. 3B is an illustration showing separate base grids projected across separate regions of the die, in accordance with an exemplary embodiment of the present invention;

FIG. 3C is an illustration showing an exemplary linear-shaped feature defined to be compatible with the dynamic array, in accordance with one embodiment of the present invention;

FIG. 3D is an illustration showing another exemplary linear-shaped feature defined to be compatible with the dynamic array, in accordance with one embodiment of the present invention;

FIG. 4 is an illustration showing a diffusion layer layout of an exemplary dynamic array, in accordance with one embodiment of the present invention;

FIG. 5 is an illustration showing a gate electrode layer and a diffusion contact layer above and adjacent to the diffusion layer of FIG. 4, in accordance with one embodiment of the present invention;

FIG. 6 is an illustration showing a gate electrode contact layer defined above and adjacent to the gate electrode layer of FIG. 5, in accordance with one embodiment of the present invention;

FIGS. 6A-6E show annotated versions of FIG. 6;

FIG. 7A is an illustration showing a traditional approach for making contact to the gate electrode;

FIG. 7B is an illustration showing a gate electrode contact defined in accordance with one embodiment of the present invention;

FIG. 8A is an illustration showing a metal 1 layer defined above and adjacent to the gate electrode contact layer of FIG. 6, in accordance with one embodiment of the present invention;

FIG. 8B is an illustration showing the metal 1 layer of FIG. 8A with larger track widths for the metal 1 ground and power tracks, relative to the other metal 1 tracks;

FIG. 9 is an illustration showing a via 1 layer defined above and adjacent to the metal 1 layer of FIG. 8A, in accordance with one embodiment of the present invention;

FIG. 10 is an illustration showing a metal 2 layer defined above and adjacent to the via 1 layer of FIG. 9, in accordance with one embodiment of the present invention;

FIG. 11 is an illustration showing conductor tracks traversing the dynamic array in a first diagonal direction relative to the first and second reference directions (x) and (y), in accordance with one embodiment of the present invention;

FIG. 12 is an illustration showing conductor tracks traversing the dynamic array in a second diagonal direction relative to the first and second reference directions (x) and (y), in accordance with one embodiment of the present invention;

FIG. 13C is an illustration showing an example of a sub-resolution contact layout utilizing various shaped sub-resolution contacts, in accordance with one embodiment of the present invention;

FIG. 13D is an illustration showing an exemplary implementation of alternate phase shift masking (APSM) with sub-resolution contacts, in accordance with one embodiment of the present invention;

FIG. 14 is an illustration showing a semiconductor chip structure, in accordance with one embodiment of the present invention;

FIG. 14A shows an annotated version of FIG. 14;

FIG. 15 shows an example layout architecture defined in accordance with one embodiment of the present invention; and

FIG. 15A shows an annotated version of FIG. 15.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

Generally speaking, a dynamic array architecture is provided to address semiconductor manufacturing process variability associated with a continually increasing lithographic gap. In the area of semiconductor manufacturing, lithographic gap is defined as the difference between the minimum size of a feature to be defined and the wavelength of light used to render the feature in the lithographic process, wherein the feature size is less than the wavelength of the light. Current lithographic processes utilize a light wavelength of 193 nm. However, current feature sizes are as small as 65 nm and are expected to soon approach sizes as small as 45 nm. With a size of 65 nm, the shapes are three times smaller than the wavelength of the light used to define the shapes. Also, considering that the interaction radius of light is about five light wavelengths, it should be appreciated that shapes exposed with a 193 nm light source will influence the exposure of shapes approximately 5*193 nm (965 nm) away. When considering the 65 nm sized features with respect to 90 nm sized features, it should be appreciated that approximately two times as many 65 nm sizes features may be within the 965 nm interaction radius of the 193 nm light source as compared to the 90 nm sized features.

Due to the increased number of features within the interaction radius of the light source, the extent and complexity of light interference contributing to exposure of a given feature is significant. Additionally, the particular shapes associated with the features within the interaction radius of the light source weighs heavily on the type of light interactions that occur. Traditionally, designers were allowed to define essentially any two-dimensional topology of feature shapes so long as a set of design rules were satisfied. For example, in a given layer of the chip, i.e., in a given mask, the designer may have defined two-dimensionally varying features having bends that wrap around each other. When such two-dimensionally varying features are located in neighboring proximity to each other, the light used to expose the features will interact in a complex and generally unpredictable manner. The light interaction becomes increasingly more complex and unpredictable as the feature sizes and relative spacing become smaller.

Traditionally, if a designer follows the established set of design rules, the resulting product will be manufacturable with a specified probability associated with the set of design rules. Otherwise, for a design that violates the set of design rules, the probability of successful manufacture of the resulting product is unknown. To address the complex light interaction between neighboring two-dimensionally varying features, in the interest of successful product manufacturing, the set of design rules is expanded significantly to adequately address the possible combinations of two-dimensionally varying features. This expanded set of design rules quickly becomes so complicated and unwieldy that application of the expanded set of design rules becomes prohibitively time consuming, expensive, and prone to error. For example, the expanded set of design rules requires complex verification. Also, the expanded set of design rules may not be universally applied. Furthermore, manufacturing yield is not guaranteed even if all design rules are satisfied.

It should be appreciated that accurate prediction of all possible light interactions when rendering arbitrarily-shaped two-dimensional features is generally not feasible. Moreover, as an alternative to or in combination with expansion of the set of design rules, the set of design rules may also be modified to include increased margin to account for unpredictable light interaction between the neighboring two-dimensionally varying features. Because the design rules are established in an attempt to cover the random two-dimensional feature topology, the design rules may incorporate a significant amount of margin. While addition of margin in the set of design rules assists with the layout portions that include the neighboring two-dimensionally varying features, such global addition of margin causes other portions of the layout that do not include the neighboring two-dimensionally varying features to be overdesigned, thus leading to decreased optimization of chip area utilization and electrical performance.

In view of the foregoing, it should be appreciated that semiconductor product yield is reduced as a result of parametric failures that stem from variability introduced by design-dependent unconstrained feature topologies, i.e., arbitrary two-dimensionally varying features disposed in proximity to each other. By way of example, these parametric failures may result from failure to accurately print contacts and vias and from variability in fabrication processes. The variability in fabrication processes may include CMP dishing, layout feature shape distortion due to photolithography, gate distortion, oxide thickness variability, implant variability, and other fabrication related phenomena. The dynamic array architecture of the present invention is defined to address the above-mentioned semiconductor manufacturing process variability.

FIG. 1 is an illustration showing a number of neighboring layout features and a representation of light intensity used to render each of the layout features, in accordance with one embodiment of the present invention. Specifically, three neighboring linear-shaped layout features (101A-101C) are depicted as being disposed in a substantially parallel relationship within a given mask layer. The distribution of light intensity from a layout feature shape is represented by a sinc function. The sinc functions (103A-103C) represent the distribution of light intensity from each of the layout features (101A-101C, respectively). The neighboring linear-shaped layout features (101A-101C) are spaced apart at locations corresponding to peaks of the sinc functions (103A-103C). Thus, constructive interference between the light energy associated with the neighboring layout features (101A-101C), i.e., at the peaks of the sine functions (103A-103C), serves to reinforce the exposure of the neighboring shapes (101A-101C) for the layout feature spacing illustrated. In accordance with the foregoing, the light interaction represented in FIG. 1 represents a synchronous case.

As illustrated in FIG. 1, when linear-shaped layout features are defined in a regular repeating pattern at an appropriate spacing, constructive interference of the light energy associated with the various layout features serves to enhance the exposure of each layout feature. The enhanced exposure of the layout features provided by the constructive light interference can dramatically reduce or even eliminate a need to utilize optical proximity correction (OPC) and/or reticle enhancement technology (RET) to obtain sufficient rendering of the layout features.

A forbidden pitch, i.e., forbidden layout feature spacing, occurs when the neighboring layout features (101A-101C) are spaced such that peaks of the sinc function associated with one layout feature align with valleys of the sinc function associated with another layout feature, thus causing destructive interference of the light energy. The destructive interference of the light energy causes the light energy focused at a given location to be reduced. Therefore, to realize the beneficial constructive light interference associated with neighboring layout features, it is necessary to predict the layout feature spacing at which the constructive overlap of the sinc function peaks will occur. Predictable constructive overlap of the sinc function peaks and corresponding layout feature shape enhancement can be realized if the layout feature shapes are rectangular, near the same size, and are oriented in the same direction, as illustrated by the layout features (101A-101C) in FIG. 1. In this manner, resonant light energy from neighboring layout feature shapes is used to enhance the exposure of a particular layout feature shape.

FIG. 2 is an illustration showing a generalized stack of layers used to define a dynamic array architecture, in accordance with one embodiment of the present invention. It should be appreciated that the generalized stack of layers used to define the dynamic array architecture, as described with respect to FIG. 2, is not intended to represent an exhaustive description of the CMOS manufacturing process. However, the dynamic array is to be built in accordance with standard CMOS manufacturing processes. Generally speaking, the dynamic array architecture includes both the definition of the underlying structure of the dynamic array and the techniques for assembling the dynamic array for optimization of area utilization and manufacturability. Thus, the dynamic array is designed to optimize semiconductor manufacturing capabilities.

With regard to the definition of the underlying structure of the dynamic array, the dynamic array is built-up in a layered manner upon a base substrate 201, e.g., upon a silicon substrate, or silicon-on-insulator (SOI) substrate. Diffusion regions 203 are defined in the base substrate 201. The diffusion regions 203 represent selected regions of the base substrate 201 within which impurities are introduced for the purpose of modifying the electrical properties of the base substrate 201. Above the diffusion regions 203, diffusion contacts 205 are defined to enable connection between the diffusion regions 203 and conductor lines. For example, the diffusion contacts 205 are defined to enable connection between source and drain diffusion regions 203 and their respective conductor nets. Also, gate electrode features 207 are defined above the diffusion regions 203 to form transistor gates. Gate electrode contacts 209 are defined to enable connection between the gate electrode features 207 and conductor lines. For example, the gate electrode contacts 209 are defined to enable connection between transistor gates and their respective conductor nets.

Interconnect layers are defined above the diffusion contact 205 layer and the gate electrode contact layer 209. The interconnect layers include a first metal (metal 1) layer 211, a first via (via 1) layer 213, a second metal (metal 2) layer 215, a second via (via 2) layer 217, a third metal (metal 3) layer 219, a third via (via 3) layer 221, and a fourth metal (metal 4) layer 223. The metal and via layers enable definition of the desired circuit connectivity. For example, the metal and via layers enable electrical connection of the various diffusion contacts 205 and gate electrode contacts 209 such that the logic function of the circuitry is realized. It should be appreciated that the dynamic array architecture is not limited to a specific number of interconnect layers, i.e., metal and via layers. In one embodiment, the dynamic array may include additional interconnect layers 225, beyond the fourth metal (metal 4) layer 223. Alternatively, in another embodiment, the dynamic array may include less than four metal layers.

The dynamic array is defined such that layers (other than the diffusion region layer 203) are restricted with regard to layout feature shapes that can be defined therein. Specifically, in each layer other than the diffusion region layer 203, only linear-shaped layout features are allowed. A linear-shaped layout feature in a given layer is characterized as having a consistent vertical cross-section shape and extending in a single direction over the substrate. Thus, the linear-shaped layout features define structures that are one-dimensionally varying. The diffusion regions 203 are not required to be one-dimensionally varying, although they are allowed to be if necessary. Specifically, the diffusion regions 203 within the substrate can be defined to have any two-dimensionally varying shape with respect to a plane coincident with a top surface of the substrate. In one embodiment, the number of diffusion bend topologies is limited such that the interaction between the bend in diffusion and the conductive material, e.g., polysilicon, that forms the gate electrode of the transistor is predictable and can be accurately modeled. The linear-shaped layout features in a given layer are positioned to be parallel with respect to each other. Thus, the linear-shaped layout features in a given layer extend in a common direction over the substrate and parallel with the substrate.

The underlying layout methodology of the dynamic array uses constructive light interference of light waves in the lithographic process to reinforce exposure of neighboring shapes in a given layer. Therefore, the spacing of the parallel, linear-shaped layout features in a given layer is designed around the constructive light interference of the standing light waves such that lithographic correction (e.g., OPC/RET) is minimized or eliminated. Thus, in contrast to conventional OPC/RET-based lithographic processes, the dynamic array defined herein exploits the light interaction between neighboring features, rather than attempting to compensate for the light interaction between neighboring features.

Because the standing light wave for a given linear-shaped layout feature can be accurately modeled, it is possible to predict how the standing light waves associated with the neighboring linear-shaped layout features disposed in parallel in a given layer will interact. Therefore, it is possible to predict how the standing light wave used to expose one linear-shaped feature will contribute to the exposure of its neighboring linear-shaped features. Prediction of the light interaction between neighboring linear-shaped features enables the identification of an optimum feature-to-feature spacing such that light used to render a given shape will reinforce its neighboring shapes. The feature-to-feature spacing in a given layer is defined as the feature pitch, wherein the pitch is the center-to-center separation distance between adjacent linear-shaped features in a given layer.

To provide the desired exposure reinforcement between neighboring features, the linear-shaped layout features in a given layer are spaced such that constructive and destructive interference of the light from neighboring features will be optimized to produce the best rendering of all features in the neighborhood. The feature-to-feature spacing in a given layer is proportional to the wavelength of the light used to expose the features. The light used to expose each feature within about a five light wavelength distance from a given feature will serve to enhance the exposure of the given feature to some extent. The exploitation of constructive interference of the standing light waves used to expose neighboring features enables the manufacturing equipment capability to be maximized and not be limited by concerns regarding light interactions during the lithography process.

As discussed above, the dynamic array incorporates a restricted topology in which the features within each layer (other than diffusion) are required to be linear-shaped features that are oriented in a parallel manner to traverse over the substrate in a common direction. With the restricted topology of the dynamic array, the light interaction in the photolithography process can be optimized such that the printed image on the mask is essentially identical to the drawn shape in the layout, i.e., essentially a 100% accurate transfer of the layout onto the resist is achieved.

FIG. 3A is an illustration showing an exemplary base grid to be projected onto the dynamic array to facilitate definition of the restricted topology, in accordance with one embodiment of the present invention. The base grid can be used to facilitate parallel placement of the linear-shaped features in each layer of the dynamic array at the appropriate optimized pitch. Although not physically defined as part of the dynamic array, the base grid can be considered as a projection on each layer of the dynamic array. Also, it should be understood that the base grid is projected in a substantially consistent manner with respect to position on each layer of the dynamic array, thus facilitating accurate feature stacking and alignment.

In the exemplary embodiment of FIG. 3A, the base grid is defined as a rectangular grid, i.e., Cartesian grid, in accordance with a first reference direction (x) and a second reference direction (y). The gridpoint-to-gridpoint spacing in the first and second reference directions can be defined as necessary to enable definition of the linear-shaped features at the optimized feature-to-feature spacing. Also, the gridpoint spacing in the first reference direction (x) can be different than the gridpoint spacing in the second reference direction (y). In one embodiment, a single base grid is projected across the entire die to enable location of the various linear-shaped features in each layer across the entire die. However, in other embodiments, separate base grids can be projected across separate regions of the die to support different feature-to-feature spacing requirements within the separate regions of the die. FIG. 3B is an illustration showing separate base grids projected across separate regions of the die, in accordance with an exemplary embodiment of the present invention.

The base grid is defined with consideration for the light interaction function, i.e., the sinc function, and the manufacturing capability, wherein the manufacturing capability is defined by the manufacturing equipment and processes to be utilized in fabricating the dynamic array. With regard to the light interaction function, the base grid is defined such that the spacing between gridpoints enables alignment of peaks in the sinc functions describing the light energy projected upon neighboring gridpoints. Therefore, linear-shaped features optimized for lithographic reinforcement can be specified by drawing a line from a first gridpoint to a second gridpoint, wherein the line represents a rectangular structure of a given width. It should be appreciated that the various linear-shaped features in each layer can be specified according to their endpoint locations on the base grid and their width.

FIG. 3C is an illustration showing an exemplary linear-shaped feature 301 defined to be compatible with the dynamic array, in accordance with one embodiment of the present invention. The linear-shaped feature 301 has a substantially rectangular cross-section defined by a width 303 and a height 307. The linear-shaped feature 301 extends in a linear direction to a length 305. In one embodiment, a cross-section of the linear-shaped feature, as defined by its width 303 and height 307, is substantially uniform along its length 305. It should be understood, however, that lithographic effects may cause a rounding of the ends of the linear-shaped feature 301. The first and second reference directions (x) and (y), respectively, of FIG. 3A are shown to illustrate an exemplary orientation of the linear-shaped feature on the dynamic array. It should be appreciated that the linear-shaped feature may be oriented to have its length 305 extend in either the first reference direction (x), the second reference direction (y), or in diagonal direction defined relative to the first and second reference directions (x) and (y). Regardless of the linear-shaped features' particular orientation with respect to the first and second reference directions (x) and (y), it should be understood that the linear-shaped feature is defined in a plane that is substantially parallel to a top surface of the substrate upon which the dynamic array is built. Also, it should be understood that the linear-shaped feature is free of bends, i.e., change in direction, in the plane defined by the first and second reference directions.

FIG. 3D is an illustration showing another exemplary linear-shaped feature 317 defined to be compatible with the dynamic array, in accordance with one embodiment of the present invention. The linear-shaped feature 317 has a trapezoidal cross-section defined by a lower width 313, an upper width 315, and a height 309. The linear-shaped feature 317 extends in a linear direction to a length 311. In one embodiment, the cross-section of the linear-shaped feature 317 is substantially uniform along its length 311. It should be understood, however, that lithographic effects may cause a rounding of the ends of the linear-shaped feature 317. The first and second reference directions (x) and (y), respectively, of FIG. 3A are shown to illustrate an exemplary orientation of the linear-shaped feature on the dynamic array. It should be appreciated that the linear-shaped feature 317 may be oriented to have its length 311 extend in either the first reference direction (x), the second reference direction (y), or in diagonal direction defined relative to the first and second reference directions (x) and (y). Regardless of the particular orientation of the linear-shaped feature 317 with regard to the first and second reference directions (x) and (y), it should be understood that the linear-shaped feature 317 is defined in a plane that is substantially parallel to a top surface of the substrate upon which the dynamic array is built. Also, it should be understood that the linear-shaped feature 317 is free of bends, i.e., change in direction, in the plane defined by the first and second reference directions.

Although FIGS. 3C and 3D explicitly discuss linear shaped features having rectangular and trapezoidal cross-sections, respectively, it should be understood that the linear shaped features having other types of cross-sections can be defined within the dynamic array. Therefore, essentially any suitable cross-sectional shape of the linear-shaped feature can be utilized so long as the linear-shaped feature is defined to have a length that extends in one direction, and is oriented to have its length extend in either the first reference direction (x), the second reference direction (y), or in diagonal direction defined relative to the first and second reference directions (x) and (y).

The layout architecture of the dynamic array follows the base grid pattern. Thus, it is possible to use grid points to represent where changes in direction occur in diffusion, wherein gate electrode and metal linear-shaped features are placed, where contacts are placed, where opens are in the linear-shaped gate electrode and metal features, etc. The pitch of the gridpoints, i.e., the gridpoint-to-gridpoint spacing, should be set for a given feature line width, e.g., width 303 in FIG. 3C, such that exposure of neighboring linear-shaped features of the given feature line width will reinforce each other, wherein the linear-shaped features are centered on gridpoints. With reference to the dynamic array stack of FIG. 2 and the exemplary base grid of FIG. 3A, in one embodiment, the gridpoint spacing in the first reference direction (x) is set by the required gate electrode gate pitch. In this same embodiment, the gridpoint pitch in the second reference direction (y) is set by the metal 1 and metal 3 pitch. For example, in a 90 nm process technology, i.e., minimum feature size equal to 90 nm, the gridpoint pitch in the second reference direction (y) is about 0.24 micron. In one embodiment, metal 1 and metal 2 layers will have a common spacing and pitch. A different spacing and pitch may be used above the metal 2 layer.

The various layers of the dynamic array are defined such that the linear-shaped features in adjacent layers extend in a crosswise manner with respect to each other. For example, the linear-shaped features of adjacent layers may extend orthogonally, i.e., perpendicularly with respect to each other. Also, the linear-shaped features of one layer may extend across the linear-shaped features of an adjacent layer at an angle, e.g., at about 45 degrees. For example, in one embodiment the linear-shaped feature of one layer extend in the first reference direction (x) and the linear-shaped features of the adjacent layer extend diagonally with respect to the first (x) and second (y) reference directions. It should be appreciated that to route a design in the dynamic array having the linear-shaped features positioned in the crosswise manner in adjacent layers, opens can be defined in the linear-shaped features, and contacts and vias can be defined as necessary.

The dynamic array minimizes the use of bends in layout shapes to eliminate unpredictable lithographic interactions. Specifically, prior to OPC or other RET processing, the dynamic array allows bends in the diffusion layer to enable control of device sizes, but does not allow bends in layers above the diffusion layer. The layout features in each layer above the diffusion layer are linear in shape, e.g., FIG. 3C, and disposed in a parallel relationship with respect to each other. The linear shapes and parallel positioning of layout features are implemented in each stack layer of the dynamic array where predictability of constructive light interference is necessary to ensure manufacturability. In one embodiment, the linear shapes and parallel positioning of layout features are implemented in the dynamic array in each layer above diffusion through metal 2. Above metal 2, the layout features may be of sufficient size and shape that constructive light interference is not required to ensure manufacturability. However, the presence of constructive light interference in patterning layout features above metal 2 may be beneficial.

An exemplary buildup of dynamic array layers from diffusion through metal 2 are described with respect to FIGS. 4 through 14. It should be appreciated that the dynamic array described with respect to FIGS. 4 through 14 is provided by way of example only, and is not intended to convey limitations of the dynamic array architecture. The dynamic array can be used in accordance with the principles presented herein to define essentially any integrated circuit design.

FIG. 4 is an illustration showing a diffusion layer layout of an exemplary dynamic array, in accordance with one embodiment of the present invention. The diffusion layer of FIG. 4 shows a p-diffusion region 401 and an n-diffusion region 403. While the diffusion regions are defined according to the underlying base grid, the diffusion regions are not subject to the linear-shaped feature restrictions associated with the layers above the diffusion layer. The diffusion regions 401 and 403 include diffusion squares 405 defined where diffusion contacts will be located. The diffusion regions 401 and 403 do not include extraneous jogs or corners, thus improving the use of lithographic resolution and enabling more accurate device extraction. Additionally, n+ mask regions (412 and 416) and p+ mask regions (410 and 414) are defined as rectangles on the (x), (y) grid with no extraneous jogs or notches. This style permits use of larger diffusion regions, eliminates need for OPC/RET, and enables use of lower resolution and lower cost lithographic systems, e.g., i-line illumination at 365 nm. It should be appreciated that the n+ mask region 416 and the p+ mask region 410, as depicted in FIG. 4, are for an embodiment that does not employ well-biasing. In an alternative embodiment where well-biasing is to be used, the n+ mask region 416 shown in FIG. 4 will actually be defined as a p+ mask region. Also, in this alternative embodiment, the p+ mask region 410 shown in FIG. 4 will actually be defined as a n+ mask region.

FIG. 5 is an illustration showing a gate electrode layer and a diffusion contact layer above and adjacent to the diffusion layer of FIG. 4, in accordance with one embodiment of the present invention. As those skilled in the CMOS arts will appreciate, the gate electrode features 501 define the transistor gates. The gate electrode features 501 are defined as linear shaped features extending in a parallel relationship across the dynamic array in the second reference direction (y). In one embodiment, the gate electrode features 501 are defined to have a common width. However, in another embodiment, one or more of the gate electrode features can be defined to have a different width. For example, FIG. 5 shows a gate electrode features 501A that has a larger width relative to the other gate electrode features 501. The pitch (center-to-center spacing) of the gate electrode features 501 is minimized while ensuring optimization of lithographic reinforcement, i.e., resonant imaging, provided by neighboring gate electrode features 501. For discussion purposes, gate electrode features 501 extending across the dynamic array in a given line are referred to as a gate electrode track.

The gate electrode features 501 form n-channel and p-channel transistors as they cross the diffusion regions 403 and 401, respectively. Optimal gate electrode feature 501 printing is achieved by drawing gate electrode features 501 at every grid location, even though no diffusion region may be present at some grid locations. Also, long continuous gate electrode features 501 tend to improve line end shortening effects at the ends of gate electrode features within the interior of the dynamic array. Additionally, gate electrode printing is significantly improved when all bends are removed from the gate electrode features 501.

Each of the gate electrode tracks may be interrupted, i.e., broken, any number of times in linearly traversing across the dynamic array in order to provide required electrical connectivity for a particular logic function to be implemented. When a given gate electrode track is required to be interrupted, the separation between ends of the gate electrode track segments at the point of interruption is minimized to the extent possible taking into consideration the manufacturing capability and electrical effects. In one embodiment, optimal manufacturability is achieved when a common end-to-end spacing is used between features within a particular layer.

Minimizing the separation between ends of the gate electrode track segments at the points of interruption serves to maximize the lithographic reinforcement, and uniformity thereof, provided from neighboring gate electrode tracks. Also, in one embodiment, if adjacent gate electrode tracks need to be interrupted, the interruptions of the adjacent gate electrode tracks are made such that the respective points of interruption are offset from each other so as to avoid, to the extent possible, an occurrence of neighboring points of interruption. More specifically, points of interruption within adjacent gate electrode tracks are respectively positioned such that a line of sight does not exist through the points of interruption, wherein the line of sight is considered to extend perpendicularly to the direction in which the gate electrode tracks extend over the substrate. Additionally, in one embodiment, the gate electrodes may extend through the boundaries at the top and bottom of the cells, i.e., the PMOS or NMOS cells. This embodiment would enable bridging of neighboring cells.

With further regard to FIG. 5, diffusion contacts 503 are defined at each diffusion square 405 to enhance the printing of diffusion contacts via resonant imaging. The diffusion squares 405 are present around every diffusion contact 503 to enhance the printing of the power and ground connection polygons at the diffusion contacts 503.

The gate electrode features 501 and diffusion contacts 503 share a common grid spacing. More specifically, the gate electrode feature 501 placement is offset by one-half the grid spacing relative to the diffusion contacts 503. For example, if the gate electrode features 501 and diffusion contact 503 grid spacing is 0.36 μm, then the diffusion contacts are placed such that the x-coordinate of their center falls on an integer multiple of 0.36 μm, while the x-coordinate of the center of each gate electrode feature 501 minus 0.18 μm should be an integer multiple of 0.36 μm. In the present example, the x-coordinates are represented by the following:

- Diffusion contact center x-coordinate=I*0.36 μm, where I is the grid number;
- Gate electrode feature center x-coordinate=0.18 μm+I*0.36 μm, where I is the grid number.

The grid based system of the dynamic array ensures that all contacts (diffusion and gate electrode) will land on a horizontal grid that is equal to a multiple of one-half of the diffusion contact grid and a vertical grid that is set by the metal 1 pitch. In the example above, the gate electrode feature and diffusion contact grid is 0.36 μm. The diffusion contacts and gate electrode contacts will land on a horizontal grid that is a multiple of 0.18 μm. Also, the vertical grid for 90 nm process technologies is about 0.24 μm.

FIG. 6 is an illustration showing a gate electrode contact layer defined above and adjacent to the gate electrode layer of FIG. 5, in accordance with one embodiment of the present invention. In the gate electrode contact layer, gate electrode contacts 601 are drawn to enable connection of the gate electrode features 501 to the overlying metal conduction lines. In general, design rules will dictate the optimum placement of the gate electrode contacts 601. In one embodiment, the gate electrode contacts are drawn on top of the transistor endcap regions. This embodiment minimizes white space in the dynamic array when design rules specify long transistor endcaps. In some process technologies white space may be minimized by placing a number of gate electrode contacts for a cell in the center of the cell. Also, it should be appreciated that in the present invention, the gate electrode contact 601 is oversized in the direction perpendicular to the gate electrode feature 501 to ensure overlap between the gate electrode contact 601 and the gate electrode feature 501.

FIG. 6A shows an annotated version of FIG. 6. The features depicted in FIG. 6A are exactly the same as the features depicted in FIG. 6. FIG. 6A shows a first conductive gate level structure 501a having a lengthwise centerline 6a01. FIG. 6A shows a second conductive gate level structure 501b and a third conductive gate level structure 501c having a lengthwise centerline 6a03. FIG. 6A shows a fourth conductive gate level structure 501d and a fifth conductive gate level structure 501e having the lengthwise centerline 6a05. FIG. 6A shows a sixth conductive gate level structure 501f having a lengthwise centerline 6a07. FIG. 6A shows a seventh conductive gate level structure 501g having a lengthwise centerline 6a09. FIG. 6A shows an eighth conductive gate level structure 501h having a lengthwise centerline 6a11.

FIG. 6A shows the first conductive gate level structure 501a separated from each of the second conductive gate level structure 501b and third conductive gate level structure 501c by a centerline-to-centerline spacing 6a13 as measured in a direction perpendicular to the parallel direction of the gate level structures. FIG. 6A shows the second conductive gate level structure 501b separated from the fourth conductive gate level structure 501d by a centerline-to-centerline spacing 6a15 as measured in the direction perpendicular to the parallel direction of the gate level structures. FIG. 6A shows the third conductive gate level structure 501c separated from the fifth conductive gate level structure 501e by a centerline-to-centerline spacing 6a15 as measured in the direction perpendicular to the parallel direction of the gate level structures. FIG. 6A shows the sixth conductive gate level structure 501f separated from each of the fourth conductive gate level structure 501d and fifth conductive gate level structure 501e by a centerline-to-centerline spacing 6a17 as measured in the direction perpendicular to the parallel direction of the gate level structures. FIG. 6A shows the sixth conductive gate level structure 501f separated from the seventh conductive gate level structure 501g by a centerline-to-centerline spacing 6a19 as measured in the direction perpendicular to the parallel direction of the gate level structures. FIG. 6A shows the seventh conductive gate level structure 501g separated from the eighth conductive gate level structure 501h by a centerline-to-centerline spacing 6a21 as measured in the direction perpendicular to the parallel direction of the gate level structures.

FIG. 6A shows the first conductive gate level structure 501a forming a gate electrode of a transistor 6a47 of a first transistor type and a gate electrode of a transistor 6a37 of a second transistor type. FIG. 6A shows the second conductive gate level structure 501b forming a gate electrode of a transistor 6a49 of the first transistor type. FIG. 6A shows the third conductive gate level structure 501c forming a gate electrode of a transistor 6a39 of the second transistor type. FIG. 6A shows the fourth conductive gate level structure 501d forming a gate electrode of a transistor 6a51 of the first transistor type. FIG. 6A shows the fifth conductive gate level structure 501e forming a gate electrode of a transistor 6a41 of the second transistor type. FIG. 6A shows the sixth conductive gate level structure 501f forming a gate electrode of a transistor 6a53 of the first transistor type and a gate electrode of a transistor 6a43 of the second transistor type. FIG. 6A shows the seventh conductive gate level structure 501g not forming a gate electrode of a transistor. FIG. 6A shows the eighth conductive gate level structure 501h forming a gate electrode of a transistor 6a55 of the first transistor type and a gate electrode of a transistor 6a45 of the second transistor type.

FIG. 6A shows the contact 601a connected to the first conductive gate level structure 501a. FIG. 6A shows the contact 601b connected to the second conductive gate level structure 501b. FIG. 6A shows the contact 601c connected to the third conductive gate level structure 501c. FIG. 6A shows the contact 601d connected to the fourth conductive gate level structure 501d. FIG. 6A shows the contact 601e connected to the fifth conductive gate level structure 501e. FIG. 6A shows the contact 601f connected to the sixth conductive gate level structure 501f.

FIG. 6A shows the contact 601b positioned to contact the second conductive gate level structure 501b at a contact-to-gate distance 6a25 from a gate electrode of the transistor 6a49. FIG. 6A shows the contact 601c positioned to contact the third conductive gate level structure 501c at a contact-to-gate distance 6a27 from a gate electrode of the transistor 6a39. FIG. 6A shows the contact 601d positioned to contact the fourth conductive gate level structure 501d at a contact-to-gate distance 6a23 from a gate electrode of the transistor 6a51. FIG. 6A shows the contact 601e positioned to contact the fifth conductive gate level structure 501e at a contact-to-gate distance 6a29 from a gate electrode of the transistor 6a41.

FIG. 6B shows an annotated version of FIG. 6. The features depicted in FIG. 6B are exactly the same as the features depicted in FIG. 6. FIG. 6B shows the contact 601b located at a contact position 6a31 in the parallel direction of the conductive gate level structures, i.e., in the y direction. FIG. 6B shows the contact 601c and the contact 601d located at a contact position 6a33 in the parallel direction of the conductive gate level structures. FIG. 6B shows the contact 601e located at a contact position 6a35 in the parallel direction of the conductive gate level structures. FIG. 6B shows the contacts 601b and 601e positioned outside the diffusion regions 401 and 403 of different diffusion region types. FIG. 6B shows the contacts 601c and 601d positioned between the diffusion regions 401 and 403 of different diffusion region types, i.e., positioned over the inner non-diffusion region between the diffusion regions 401 and 403 of different diffusion region types.

FIG. 6C shows an annotated version of FIG. 6. The features depicted in FIG. 6C are exactly the same as the features depicted in FIG. 6. FIG. 6C shows the second conductive gate level structure 501b extending a distance 6a57 beyond the contact 601b in the parallel direction (y-direction) away from the gate electrode of the transistor 6a49. FIG. 6C shows the third conductive gate level structure 501c extending a distance 6a59 beyond the contact 601c in the parallel direction (y-direction) away from the gate electrode of the transistor 6a39. FIG. 6C shows the fourth conductive gate level structure 501d extending a distance 6a61 beyond the contact 601d in the parallel direction (y-direction) away from the gate electrode of the transistor 6a51. FIG. 6C shows the fifth conductive gate level structure 501e extending a distance 6a63 beyond the contact 601e in the parallel direction (y-direction) away from the gate electrode of the transistor 6a41.

FIG. 6D shows an annotated version of FIG. 6. The features depicted in FIG. 6D are exactly the same as the features depicted in FIG. 6. FIG. 6D shows the first conductive gate level structure 501a defined to have a length 6a89 as measured in the parallel direction (y-direction). FIG. 6D shows the second conductive gate level structure 501b defined to have a length 6a93 as measured in the parallel direction (y-direction). FIG. 6D shows the third conductive gate level structure 501c defined to have a length 6a91 as measured in the parallel direction (y-direction). FIG. 6D shows the fourth conductive gate level structure 501d defined to have a length 6a97 as measured in the parallel direction (y-direction). FIG. 6D shows the fifth conductive gate level structure 501e defined to have a length 6a95 as measured in the parallel direction (y-direction). FIG. 6D shows the sixth conductive gate level structure 501f defined to have a length 6a99 as measured in the parallel direction (y-direction). FIG. 6D shows the seventh conductive gate level structure 501g defined to have a length 6a101 as measured in the parallel direction (y-direction). FIG. 6D shows the eighth conductive gate level structure 501h defined to have a length 6a103 as measured in the parallel direction (y-direction).

FIG. 6D shows the second conductive gate level structure 501b positioned in a spaced apart end-to-end manner with the third conductive gate level structure 501c. FIG. 6D shows the second conductive gate level structure 501b separated from the third conductive gate level structure 501c by a first end-to-end spacing 6a85 as measured in the parallel direction (y-direction). FIG. 6D shows the fourth conductive gate level structure 501d positioned in a spaced apart end-to-end manner with the fifth conductive gate level structure 501e. FIG. 6D shows the fourth conductive gate level structure 501d separated from the fifth conductive gate level structure 501e by a second end-to-end spacing 6a87 as measured in the parallel direction (y-direction). FIG. 6D shows the first end-to-end spacing 6a85 positioned over the inner non-diffusion region between the two diffusion regions 401 and 403 of different diffusion types. FIG. 6D shows the second end-to-end spacing 6a87 positioned over the inner non-diffusion region between the two diffusion regions 401 and 403 of different diffusion types. FIG. 6D shows the first end-to-end spacing 6a85 offset in the parallel direction (y-direction) from the second end-to-end spacing 6a87.

FIG. 6D shows the first, second, fourth, sixth, seventh, and eighth conductive gate level structures 501a, 501b, 501d, 501f, 501g, 501h, respectively, each having an end aligned with a first common position 6a81 in the parallel direction (y-direction). FIG. 6D shows the first, third, fifth, sixth, seventh, and eighth conductive gate level structures 501a, 501c, 501e, 501f, 501g, 501h, respectively, each having an end aligned with a second common position 6a83 in the parallel direction (y-direction).

FIG. 6E shows an annotated version of FIG. 6. The features depicted in FIG. 6E are exactly the same as the features depicted in FIG. 6. FIG. 6E shows the second conductive gate level feature 501b having an outer extension distance 6a105 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a49 and away from the transistor 6a39. FIG. 6E shows the second conductive gate level feature 501b having an inner extension distance 6a107 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a49 and toward the transistor 6a39. FIG. 6E shows the third conductive gate level feature 501c having an outer extension distance 6a111 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a39 and away from the transistor 6a49. FIG. 6E shows the third conductive gate level feature 501c having an inner extension distance 6a109 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a39 and toward the transistor 6a49.

FIG. 6E shows the fourth conductive gate level feature 501d having an outer extension distance 6a113 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a51 and away from the transistor 6a41. FIG. 6E shows the fourth conductive gate level feature 501d having an inner extension distance 6a115 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a51 and toward the transistor 6a41. FIG. 6E shows the fifth conductive gate level feature 501e having an outer extension distance 6a119 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a41 and away from the transistor 6a51. FIG. 6E shows the fifth conductive gate level feature 501e having an inner extension distance 6a117 as measured in the parallel direction (y-direction) away from the gate electrode of the transistor 6a41 and toward the transistor 6a51. FIG. 7A is an illustration showing a traditional approach for making contact to a gate electrode, e.g., polysilicon feature. In the traditional configuration of FIG. 7A, an enlarged rectangular gate electrode region 707 is defined where a gate electrode contact 709 is to be located. The enlarged rectangular gate electrode region 707 introduces a bend of distance 705 in the gate electrode. The bend associated with the enlarged rectangular gate electrode region 707 sets up undesirable light interactions and distorts the gate electrode line 711. Distortion of the gate electrode line 711 is especially problematic when the gate electrode width is about the same as a transistor length.

FIG. 7B is an illustration showing a gate electrode contact 601, e.g., polysilicon contact, defined in accordance with one embodiment of the present invention. The gate electrode contact 601 is drawn to overlap the edges of the gate electrode feature 501, and extend in a direction substantially perpendicular to the gate electrode feature 501. In one embodiment, the gate electrode contact 601 is drawn such that the vertical dimension 703 is same as the vertical dimension used for the diffusion contacts 503. For example, if the diffusion contact 503 opening is specified to be 0.12 μm square then the vertical dimension of the gate electrode contact 601 is drawn at 0.12 μm. However, in other embodiments, the gate electrode contact 601 can be drawn such that the vertical dimension 703 is different from the vertical dimension used for the diffusion contacts 503.

In one embodiment, the gate electrode contact 601 extension 701 beyond the gate electrode feature 501 is set such that maximum overlap is achieved between the gate electrode contact 601 and the gate electrode feature 501. The extension 701 is defined to accommodate line end shortening of the gate electrode contact 601, and misalignment between the gate electrode contact layer and gate electrode feature layer. The length of the gate electrode contact 601 is defined to ensure maximum surface area contact between the gate electrode contact 601 and the gate electrode feature 501, wherein the maximum surface area contact is defined by the width of the gate electrode feature 501.

FIG. 8A is an illustration showing a metal 1 layer defined above the gate electrode contact layer of FIG. 6, in accordance with one embodiment of the present invention. The metal 1 layer includes a number of metal 1 tracks 801-821 defined to include linear shaped features extending in a parallel relationship across the dynamic array. The metal 1 tracks 801-821 extend in a direction substantially perpendicular to the gate electrode features 501 in the underlying gate electrode layer of FIG. 5. Thus, in the present example, the metal 1 tracks 801-821 extend linearly across the dynamic array in the first reference direction (x). The pitch (center-to-center spacing) of the metal 1 tracks 801-821 is minimized while ensuring optimization of lithographic reinforcement, i.e., resonant imaging, provided by neighboring metal 1 tracks 801-821. For example, in one embodiment, the metal 1 tracks 801-821 are centered on a vertical grid of about 0.24 μm for a 90 nm process technology.

Each of the metal 1 tracks 801-821 may be interrupted, i.e., broken, any number of times in linearly traversing across the dynamic array in order to provide required electrical connectivity for a particular logic function to be implemented. When a given metal 1 track 801-821 is required to be interrupted, the separation between ends of the metal 1 track segments at the point of interruption is minimized to the extent possible taking into consideration manufacturing capability and electrical effects. Minimizing the separation between ends of the metal 1 track segments at the points of interruption serves to maximize the lithographic reinforcement, and uniformity thereof, provided from neighboring metal 1 tracks. Also, in one embodiment, if adjacent metal 1 tracks need to be interrupted, the interruptions of the adjacent metal 1 tracks are made such that the respective points of interruption are offset from each other so as to avoid, to the extent possible, an occurrence of neighboring points of interruption. More specifically, points of interruption within adjacent metal 1 tracks are respectively positioned such that a line of sight does not exist through the points of interruption, wherein the line of sight is considered to extend perpendicularly to the direction in which the metal 1 tracks extend over the substrate.

In the example of FIG. 8A, the metal 1 track 801 is connected to the ground supply, and the metal 1 track 821 is connected to the power supply voltage. In the embodiment of FIG. 8A, the widths of the metal 1 tracks 801 and 821 are the same as the other metal 1 tracks 803-819. However, in another embodiment, the widths of metal 1 tracks 801 and 821 are larger than the widths of the other metal 1 tracks 803-819. FIG. 8B is an illustration showing the metal 1 layer of FIG. 8A with larger track widths for the metal 1 ground and power tracks (801A and 821A), relative to the other metal 1 tracks 803-819.

The metal 1 track pattern is optimally configured to optimize the use of “white space” (space not occupied by transistors). The example of FIG. 8A includes the two shared metal 1 power tracks 801 and 821, and nine metal 1 signal tracks 803-819. Metal 1 tracks 803, 809, 811, and 819 are defined as gate electrode contact tracks in order to minimize white space. Metal 1 tracks 805 and 807 are defined to connect to n-channel transistor source and drains. Metal 1 tracks 813, 815, and 817 are defined to connect to p-channel source and drains. Also, any of the nine metal 1 signal tracks 803-819 can be used as a feed through if no connection is required. For example, metal 1 tracks 813 and 815 are configured as feed through connections.

FIG. 9 is an illustration showing a via 1 layer defined above and adjacent to the metal 1 layer of FIG. 8A, in accordance with one embodiment of the present invention. Vias 901 are defined in the via 1 layer to enable connection of the metal 1 tracks 801-821 to higher level conduction lines.

FIG. 10 is an illustration showing a metal 2 layer defined above and adjacent to the via 1 layer of FIG. 9, in accordance with one embodiment of the present invention. The metal 2 layer includes a number of metal 2 tracks 1001 defined as linear shaped features extending in a parallel relationship across the dynamic array. The metal 2 tracks 1001 extend in a direction substantially perpendicular to the metal 1 tracks 801-821 in the underlying metal 1 layer of FIG. 8A, and in a direction substantially parallel to the gate electrode tracks 501 in the underlying gate electrode layer of FIG. 5. Thus, in the present example, the metal 2 tracks 1001 extend linearly across the dynamic array in the second reference direction (y).

The pitch (center-to-center spacing) of the metal 2 tracks 1001 is minimized while ensuring optimization of lithographic reinforcement, i.e., resonant imaging, provided by neighboring metal 2 tracks. It should be appreciated that regularity can be maintained on higher level interconnect layers in the same manner as implemented in the gate electrode and metal 1 layers. In one embodiment, the gate electrode feature 501 pitch and the metal 2 track pitch is the same. In another embodiment, the contacted gate electrode pitch (e.g., polysilicon-to-polysilicon space with a diffusion contact in between) is greater than the metal 2 track pitch. In this embodiment, the metal 2 track pitch is optimally set to be ⅔ or ¾ of the contacted gate electrode pitch. Thus, in this embodiment, the gate electrode track and metal 2 track align at every two gate electrode track pitches and every three metal 2 track pitches. For example, in a 90 nm process technology, the optimum contacted gate electrode track pitch is 0.36 μm, and the optimum metal 2 track pitch is 0.24 μm. In another embodiment, the gate electrode track and the metal 2 track align at every three gate electrode pitches and every four metal 2 pitches. For example, in a 90 nm process technology, the optimum contacted gate electrode track pitch is 0.36 μm, and the optimum metal 2 track pitch is 0.27 μm.

Each of the metal 2 tracks 1001 may be interrupted, i.e., broken, any number of times in linearly traversing across the dynamic array in order to provide required electrical connectivity for a particular logic function to be implemented. When a given metal 2 track 1001 is required to be interrupted, the separation between ends of the metal 2 track segments at the point of interruption is minimized to the extent possible taking into consideration manufacturing and electrical effects. Minimizing the separation between ends of the metal 2 track segments at the points of interruption serves to maximize the lithographic reinforcement, and uniformity thereof, provided from neighboring metal 2 tracks. Also, in one embodiment, if adjacent metal 2 tracks need to be interrupted, the interruptions of the adjacent metal 2 tracks are made such that the respective points of interruption are offset from each other so as to avoid, to the extent possible, an occurrence of neighboring points of interruption. More specifically, points of interruption within adjacent metal 2 tracks are respectively positioned such that a line of sight does not exist through the points of interruption, wherein the line of sight is considered to extend perpendicularly to the direction in which the metal 2 tracks extend over the substrate.

As discussed above, the conduction lines in a given metal layer above the gate electrode layer may traverse the dynamic array in a direction coincident with either the first reference direction (x) or the second reference direction (y). It should be further appreciated that the conduction lines in a given metal layer above the gate electrode layer may traverse the dynamic array in a diagonal direction relative to the first and second reference directions (x) and (y). FIG. 11 is an illustration showing conductor tracks 1101 traversing the dynamic array in a first diagonal direction relative to the first and second reference directions (x) and (y), in accordance with one embodiment of the present invention. FIG. 12 is an illustration showing conductor tracks 1201 traversing the dynamic array in a second diagonal direction relative to the first and second reference directions (x) and (y), in accordance with one embodiment of the present invention.

As with the metal 1 and metal 2 tracks discussed above, the diagonal traversing conductor tracks 1101 and 1201 of FIGS. 11 and 12 may be interrupted, i.e., broken, any number of times in linearly traversing across the dynamic array in order to provide required electrical connectivity for a particular logic function to be implemented. When a given diagonal traversing conductor track is required to be interrupted, the separation between ends of the diagonal conductor track at the point of interruption is minimized to the extent possible taking into consideration manufacturing and electrical effects. Minimizing the separation between ends of the diagonal conductor track at the points of interruption serves to maximize the lithographic reinforcement, and uniformity thereof, provided from neighboring diagonal conductor tracks.

An optimal layout density within the dynamic array is achieved by implementing the following design rules:

at least two metal 1 tracks be provided across the n-channel device area;

at least two metal 1 tracks be provided across the p-channel device area;

at least two gate electrode tracks be provided for the n-channel device; and

at least two gate electrode tracks be provided for the p-channel device.

Contacts and vias are becoming the most difficult mask from a lithographic point of view. This is because the contacts and vias are getting smaller, more closely spaced, and are randomly distributed. The spacing and density of the cuts (contact or vias) makes it extremely difficult to reliably print the shapes. For example, cut shapes may be printed improperly due to destructive interference patterns from neighboring shapes or lack of energy on lone shapes. If a cut is properly printed, the manufacturing yield of the associated contact or via is extremely high. Sub-resolution contacts can be provided to reinforce the exposure of the actual contacts, so long as the sub-resolution contacts do not resolve. Also, the sub-resolution contacts can be of any shape so long as they are smaller than the resolution capability of the lithographic process.

FIG. 13A is an illustration showing an example of a sub-resolution contact layout used to lithographically reinforce diffusion contacts and gate electrode contacts, in accordance with one embodiment of the present invention. Sub-resolution contacts 1301 are drawn such that they are below the resolution of the lithographic system and will not be printed. The function of the sub-resolution contacts 1301 is to increase the light energy at the desired contact locations, e.g., 503, 601, through resonant imaging. In one embodiment, sub-resolution contacts 1301 are placed on a grid such that both gate electrode contacts 601 and diffusion contacts 503 are lithographically reinforced. For example, sub-resolution contacts 1301 are placed on a grid that is equal to one-half the diffusion contact 503 grid spacing to positively impact both gate electrode contacts 601 and diffusion contacts 503. In one embodiment, a vertical spacing of the sub-resolution contacts 1301 follows the vertical spacing of the gate electrode contacts 601 and diffusion contacts 503.

Grid location 1303 in FIG. 13A denotes a location between adjacent gate electrode contacts 601. Depending upon the lithographic parameters in the manufacturing process, it is possible that a sub-resolution contact 1301 at this grid location would create an undesirable bridge between the two adjacent gate electrode contacts 601. If bridging is likely to occur, a sub-resolution contact 1301 at location 1303 can be omitted. Although FIG. 13A shows an embodiment where sub-resolution contacts are placed adjacent to actual features to be resolved and not elsewhere, it should be understood that another embodiment may place a sub-resolution contact at each available grid location so as to fill the grid.

FIG. 13B is an illustration showing the sub-resolution contact layout of FIG. 13A with sub-resolution contacts defined to fill the grid to the extent possible, in accordance with one embodiment of the present invention. It should be appreciated that while the embodiment of FIG. 13B fills the grid to the extent possible with sub-resolution contacts, placement of sub-resolution contacts is avoided at locations that would potentially cause undesirable bridging between adjacent fully resolved features.

FIG. 13C is an illustration showing an example of a sub-resolution contact layout utilizing various shaped sub-resolution contacts, in accordance with one embodiment of the present invention. Alternative sub-resolution contact shapes can be utilized so long as the sub-resolution contacts are below the resolution capability of the manufacturing process. FIG. 13C shows the use of “X-shaped” sub-resolution contacts 1305 to focus light energy at the corners of the adjacent contacts. In one embodiment, the ends of the X-shaped sub-resolution contact 1305 are extended to further enhance the deposition of light energy at the corners of the adjacent contacts.

FIG. 13D is an illustration showing an exemplary implementation of alternate phase shift masking (APSM) with sub-resolution contacts, in accordance with one embodiment of the present invention. As in FIG. 13A, sub-resolution contacts are utilized to lithographically reinforce diffusion contacts 503 and gate electrode contacts 601. APSM is used to improve resolution when neighboring shapes create destructive interference patterns. The APSM technique modifies the mask so that the phase of light traveling through the mask on neighboring shapes is 180 degrees out of phase. This phase shift serves to remove destructive interference and allowing for greater contact density. By way of example, contacts in FIG. 13D marked with a plus “+” sign represent contacts exposed with light waves of a first phase while contacts marked with a minus sign “−” represent contacts exposed with light waves that are shifted in phase by 180 degrees relative to the first phase used for the “+” sign contacts. It should be appreciated that the APSM technique is utilized to ensure that adjacent contacts are separated from each other.

As feature sizes decrease, semiconductor dies are capable of including more gates. As more gates are included, however, the density of the interconnect layers begins to dictate the die size. This increasing demand on the interconnect layers drives higher levels of interconnect layers. However, the stacking of interconnect layers is limited in part by the topology of the underlying layers. For example, as interconnect layers are built up, islands, ridges, and troughs can occur. These islands, ridges, and troughs can cause breaks in the interconnect lines that cross them.

To mitigate these islands and troughs, the semiconductor manufacturing process utilizes a chemical mechanical polishing (CMP) procedure to mechanically and chemically polish the surface of the semiconductor wafer such that each subsequent interconnect layer is deposited on a substantially flat surface. Like the photolithography process the quality of the CMP process is layout pattern dependent. Specifically, an uneven distribution of a layout features across a die or a wafer can cause too much material to be removed in some places and not enough material to be removed in other places, thus causing variations in the interconnect thickness and unacceptable variations in the capacitance and resistance of the interconnect layer. The capacitance and resistance variation within the interconnect layer may alter the timing of a critical net causing design failure.

The CMP process requires that dummy fill be added in the areas without interconnect shapes so that a substantially uniform wafer topology is provided to avoid dishing and improve center-to-edge uniformity. Traditionally, dummy fill is placed post-design. Thus, in the traditional approach the designer is not aware of the dummy fill characteristics. Consequently, the dummy fill placed post-design may adversely influence the design performance in a manner that has not been evaluated by the designer. Also, because the conventional topology prior to the dummy fill is unconstrained, i.e., non-uniform, the post-design dummy fill will not be uniform and predictable. Therefore, in the conventional process, the capacitive coupling between the dummy fill regions and the neighboring active nets cannot be predicted by the designer.

As previously discussed, the dynamic array disclosed herein provides optimal regularity by maximally filling all interconnect tracks from gate electrode layer upward. If multiple nets are required in a single interconnect track, the interconnect track is split with a minimally spaced gap. For example, track 809 representing the metal 1 conduction line in FIG. 8A represents three separate nets in the same track, where each net corresponds to a particular track segment. More specifically, there are two poly contact nets and a floating net to fill the track with minimal spacing between the track segments. The substantially complete filling of tracks maintains the regular pattern that creates resonant images across the dynamic array. Also, the regular architecture of the dynamic array with maximally filled interconnect tracks ensures that the dummy fill is placed in a uniform manner across the die. Therefore, the regular architecture of the dynamic array assists the CMP process to produce substantially uniform results across the die/wafer. Also, the regular gate pattern of the dynamic array assists with gate etching uniformity (microloading). Additionally, the regular architecture of the dynamic array combined with the maximally filled interconnect tracks allows the designer to analyze the capacitive coupling effects associated with the maximally filled tracks during the design phase and prior to fabrication.

Because the dynamic array sets the size and spacing of the linearly shaped features, i.e., tracks and contacts, in each mask layer, the design of the dynamic array can be optimized for the maximum capability of the manufacturing equipment and processes. That is to say, because the dynamic array is restricted to the regular architecture for each layer above diffusion, the manufacturer is capable of optimizing the manufacturing process for the specific characteristics of the regular architecture. It should be appreciated that with the dynamic array, the manufacturer does not have to be concerned with accommodating the manufacture of a widely varying set of arbitrarily-shaped layout features as is present in conventional unconstrained layouts.

An example of how the capability of manufacturing equipment can be optimized is provided as follows. Consider that a 90 nm process has a metal 2 pitch of 280 nm. This metal 2 pitch of 280 nm is not set by the maximum capability of equipment. Rather, this metal 2 pitch of 280 nm is set by the lithography of the vias. With the via lithography issues removed, the maximum capability of the equipment allows for a metal 2 pitch of about 220 nm. Thus, the design rules for metal 2 pitch include about 25% margin to account for the light interaction unpredictability in the via lithography.

The regular architecture implemented within the dynamic array allows the light interaction unpredictability in the via lithography to be removed, thus allowing for a reduction in the metal 2 pitch margin. Such a reduction in the metal 2 pitch margin allows for a more dense design, i.e., allows for optimization of chip area utilization. Additionally, with the restricted, i.e., regular, topology afforded by the dynamic array, the margin in the design rules can be reduced. Moreover, not only can the excess margin beyond the capability of the process be reduced, the restricted topology afforded by the dynamic array also allows the number of required design rules to be substantially reduced. For example, a typical design rule set for an unconstrained topology could have more than 600 design rules. A design rule set for use with the dynamic array may have about 45 design rules. Therefore, the effort required to analyze and verify the design against the design rules is decreased by more than a factor of ten with the restricted topology of the dynamic array.

When dealing with line end-to-line end gaps (i.e., track segment-to-track segment gaps) in a given track of a mask layer in the dynamic array, a limited number of light interactions exist. This limited number of light interactions can be identified, predicted, and accurately compensated for ahead of time, dramatically reducing or completely eliminating the requirement for OPC/RET. The compensation for light interactions at line end-to-line end gaps represents a lithographic modification of the as-drawn feature, as opposed to a correction based on modeling of interactions, e.g., OPC/RET, associated with the as-drawn feature.

Also, with the dynamic array, changes to the as-drawn layout are only made where needed. In contrast, OPC is performed over an entire layout in a conventional design flow. In one embodiment, a correction model can be implemented as part of the layout generation for the dynamic array. For example, due to the limited number of possible line end gap interactions, a router can be programmed to insert a line break having characteristics defined as a function of its surroundings, i.e., as a function of its particular line end gap light interactions. It should be further appreciated that the regular architecture of the dynamic array allows the line ends to be adjusted by changing vertices rather than by adding vertices. Thus, in contrast with unconstrained topologies that rely on the OPC process, the dynamic array significantly reduces the cost and risk of mask production. Also, because the line end gap interactions in the dynamic array can be accurately predicted in the design phase, compensation for the predicted line end gap interactions during the design phase does not increase risk of design failure.

In conventional unconstrained topologies, designers are required to have knowledge of the physics associated with the manufacturing process due to the presence of design dependent failures. With the grid-based system of the dynamic array as disclosed herein, the logical design can be separated from the physical design. More specifically, with the regular architecture of the dynamic array, the limited number of light interactions to be evaluated within the dynamic array, and the design independent nature of the dynamic array, designs can be represented using a grid point based netlist, as opposed to a physical netlist.

With the dynamic array, the design is not required to be represented in terms of physical information. Rather, the design can be represented as a symbolic layout. Thus, the designer can represent the design from a pure logic perspective without having to represent physical characteristics, e.g., sizes, of the design. It should be understood that the grid-based netlist, when translated to physical, matches the optimum design rules exactly for the dynamic array platform. When the grid-based dynamic array moves to a new technology, e.g., smaller technology, a grid-based netlist can be moved directly to the new technology because there is no physical data in the design representation. In one embodiment, the grid-based dynamic array system includes a rules database, a grid-based (symbolic) netlist, and the dynamic array architecture.

It should be appreciated that the grid-based dynamic array eliminates topology related failures associated with conventional unconstrained architectures. Also, because the manufacturability of the grid-based dynamic array is design independent, the yield of the design implemented on the dynamic array is independent of the design. Therefore, because the validity and yield of the dynamic array is preverified, the grid-based netlist can be implemented on the dynamic array with preverified yield performance.

FIG. 14 is an illustration showing a semiconductor chip structure 1400, in accordance with one embodiment of the present invention. The semiconductor chip structure 1400 represents an exemplary portion of a semiconductor chip, including a diffusion region 1401 having a number of conductive lines 1403A-1403G defined thereover. The diffusion region 1401 is defined in a substrate 1405, to define an active region for at least one transistor device. The diffusion region 1401 can be defined to cover an area of arbitrary shape relative to the substrate 1405 surface.

The conductive lines 1403A-1403G are arranged to extend over the substrate 1405 in a common direction 1407. It should also be appreciated that each of the number of conductive lines 1403A-1403G are restricted to extending over the diffusion region 1401 in the common direction 1407. In one embodiment, the conductive lines 1403A-1403G defined immediately over the substrate 1405 are polysilicon lines. In one embodiment, each of the conductive lines 1403A-1403G is defined to have essentially the same width 1409 in a direction perpendicular to the common direction 1407 of extension. In another embodiment, some of the conductive lines 1403A-1403G are defined to have different widths relative to the other conductive lines. However, regardless of the width of the conductive lines 1403A-1403G, each of the conductive lines 1403A-1403G is spaced apart from adjacent conductive lines according to essentially the same center-to-center pitch 1411.

As shown in FIG. 14, some of the conductive lines (1403B-1403E) extend over the diffusion region 1401, and other conductive lines (1403A, 1403F, 1403G) extend over non-diffusion portions the substrate 1405. It should be appreciated that the conductive lines 1403A-1403G maintain their width 1409 and pitch 1411 regardless of whether they are defined over diffusion region 1401 or not. Also, it should be appreciated that the conductive lines 1403A-1403G maintain essentially the same length 1413 regardless of whether they are defined over diffusion region 1401 or not, thereby maximizing lithographic reinforcement between the conductive lines 1403A-1403G across the substrate. In this manner, some of the conductive lines, e.g., 1403D, defined over the diffusion region 1401 include a necessary active portion 1415, and one or more uniformity extending portions 1417.

It should be appreciated that the semiconductor chip structure 1400 represents a portion of the dynamic array described above with respect to FIGS. 2-13D. Therefore, it should be understood that the uniformity extending portions 1417 of the conductive lines (1403B-1403E) are present to provide lithographic reinforcement of neighboring conductive lines 1403A-1403G. Also, although they may not be required for circuit operation, each of conductive lines 1403A, 1403F, and 1403G are present to provide lithographic reinforcement of neighboring conductive lines 1403A-1403G.

The concept of the necessary active portion 1415 and the uniformity extending portions 1417 also applies to higher level interconnect layers. As previously described with regard to the dynamic array architecture, adjacent interconnect layers traverse over the substrate in transverse directions, e.g., perpendicular or diagonal directions, to enable routing/connectivity required by the logic device implemented within the dynamic array. As with the conductive lines 1403A-1403G, each of the conductive lines within an interconnect layer may include a required portion (necessary active portion) to enable required routing/connectivity, and a non-required portion (uniformity extending portion) to provide lithographic reinforcement to neighboring conductive lines. Also, as with the conductive lines 1403A-1403G, the conductive lines within an interconnect layer extend in a common direction over the substrate, have essentially the same width, and are spaced apart from each other according to an essentially constant pitch.

In one embodiment, conductive lines within an interconnect layer follow essentially the same ratio between line width and line spacing. For example, at 90 nm the metal 4 pitch is 280 nm with a line width and line spacing equal to 140 nm. Larger conductive lines can be printed on a larger line pitch if the line width is equal to the line spacing.

FIG. 14A shows an annotated version of FIG. 14. The features depicted in FIG. 14A are exactly the same as the features depicted in FIG. 14. FIG. 14A shows each of the conductive lines 1403B and 1403C to have a uniformity extending portion 14a01 as measured in the common direction 1407. FIG. 14A shows each of the conductive lines 1403D and 1403E to have a uniformity extending portion 14a03 as measured in the common direction 1407. FIG. 14A shows each of the conductive lines 1403B, 1403C, 1403D, and 1403E to have a uniformity extending portion 14a05 as measured in the common direction 1407. FIG. 15 shows an example layout architecture defined in accordance with one embodiment of the present invention. The layout architecture follows a grid pattern and is based upon a horizontal grid and a vertical grid. The horizontal grid is set by the poly gate pitch. The vertical pitch is set by the metal 1/metal 3 pitch. All of the rectangular shapes should be centered on a grid point. The layout architecture minimizes the use of bends to eliminate unpredictable lithographic interactions. Bends are allowed on the diffusion layer to control transistor device sizes. Other layers should be rectangular in shape and fixed in one dimension.

FIG. 15A shows an annotated version of FIG. 15. The features depicted in FIG. 15A are exactly the same as the features depicted in FIG. 15. FIG. 15A shows a first electrical connection 15a01 (as denoted by the heavy solid black line). FIG. 15A shows a second electrical connection 15a03 (as denoted by the heavy dashed black line).

The invention described herein can be embodied as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data which can be thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. Additionally, a graphical user interface (GUI) implemented as computer readable code on a computer readable medium can be developed to provide a user interface for performing any embodiment of the present invention.

While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.

Claims

1. A semiconductor chip, comprising: a region including a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the region including at least eight conductive structures formed within the semiconductor chip, some of the at least eight conductive structures forming at least one transistor gate electrode,each of the at least eight conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least eight conductive structures co-planar with each other,each of the at least eight conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least eight conductive structures is substantially straight,wherein the second edge of each of the at least eight conductive structures is substantially straight,each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,wherein the at least eight conductive structures are positioned in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least eight conductive structures,wherein the width of each of the at least eight conductive structures is less than 45 nanometers, the region having a size of about 965 nanometers as measured in the second direction, each of the at least eight conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,wherein the at least eight conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of first transistor of a first transistor type, the first conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type,wherein the at least eight conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,wherein the at least eight conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,wherein the at least eight conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,wherein the at least eight conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type electrically connected to the first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,wherein the first transistor of the second transistor type includes a first diffusion terminal, and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type electrically connected to the first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,wherein the second transistor of the first transistor type includes a second diffusion terminal, and the third transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the first transistor type electrically connected to the first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,wherein the second transistor of the second transistor type includes a second diffusion terminal, and the third transistor of the second transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the second transistor type electrically connected to the first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,wherein the third transistor of the first transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the first transistor type through a fifth electrical connection,wherein the third transistor of the second transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the second transistor type through a sixth electrical connection,wherein the third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection, wherein the seventh electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline,wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor.
2. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level, the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, andwherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level.
3. The semiconductor chip as recited in claim 2, wherein the region includes a second interconnect conductive structure positioned next to and spaced apart from the first interconnect conductive structure in a same interconnect level as the first interconnect conductive structure, the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure.
4. The semiconductor chip as recited in claim 3, wherein the first and second interconnect conductive structures are positioned such that a distance as measured in the second direction between their lengthwise centerlines is substantially equal to a second pitch, wherein the second pitch is a fractional multiple of the first pitch.
5. The semiconductor chip as recited in claim 4, wherein the second pitch is less than or equal to the first pitch.
6. The semiconductor chip as recited in claim 5, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures.
7. The semiconductor chip as recited in claim 6, wherein the first and second interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level.
8. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level, the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, andwherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level.
9. The semiconductor chip as recited in claim 8, wherein the region includes a second interconnect conductive structure positioned in a same interconnect level as the first interconnect conductive structure, the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,wherein the first and second interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to a second pitch.
10. The semiconductor chip as recited in claim 9, wherein the region includes a third interconnect conductive structure positioned in the same interconnect level as the first and second interconnect conductive structures, the third interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the third interconnect conductive structure defined by a first end of the third interconnect conductive structure, a second end of the third interconnect conductive structure, a first edge of the third interconnect conductive structure, and a second edge of the third interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the third interconnect conductive structure is equal to a sum of a total distance along the first edge of the third interconnect conductive structure and a total distance along the second edge of the third interconnect conductive structure and a total distance along the first end of the third interconnect conductive structure and a total distance along the second end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the first end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within a space between the first and second edges of the third interconnect conductive structure,wherein the second end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within the space between the first and second edges of the third interconnect conductive structure,the third interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the second edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the third interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the third interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the third interconnect conductive structure,wherein the region includes a fourth interconnect conductive structure positioned in the same interconnect level as the first, second, and third interconnect conductive structures,the fourth interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the fourth interconnect conductive structure defined by a first end of the fourth interconnect conductive structure, a second end of the fourth interconnect conductive structure, a first edge of the fourth interconnect conductive structure, and a second edge of the fourth interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the fourth interconnect conductive structure is equal to a sum of a total distance along the first edge of the fourth interconnect conductive structure and a total distance along the second edge of the fourth interconnect conductive structure and a total distance along the first end of the fourth interconnect conductive structure and a total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the first end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within a space between the first and second edges of the fourth interconnect conductive structure,wherein the second end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within the space between the first and second edges of the fourth interconnect conductive structure,the fourth interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the second edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the fourth interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the fourth interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the fourth interconnect conductive structure,wherein the third and fourth interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to the second pitch.
11. The semiconductor chip as recited in claim 10, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures.
12. The semiconductor chip as recited in claim 11, wherein the first, second, third, and fourth interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level.
13. The semiconductor chip as recited in claim 1, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures, or the ninth electrical connection includes one or more overlying interconnect conductive structures, or both the eighth and the ninth electrical connections include one or more overlying electrical connections, wherein each overlying interconnect conductive structure is formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth or ninth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth or ninth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline.
14. The semiconductor chip as recited in claim 1, wherein the lengthwise centerline of the second conductive structure is substantially aligned with the lengthwise centerline of the third conductive structure, and wherein the lengthwise centerline of the fourth conductive structure is substantially aligned with the lengthwise centerline of the fifth conductive structure.
15. The semiconductor chip as recited in claim 14, wherein a gate electrode of the fourth transistor of the first transistor type and a gate electrode of the fourth transistor of the second transistor type are formed by respective portions of a single one of the at least eight conductive structures.
16. The semiconductor chip as recited in claim 15, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor, the non-gate forming conductive structure positioned between at least two neighboring conductive structures of the at least eight conductive structures, with at least one of the at least two neighboring conductive structures forming at least one gate electrode of at least one transistor,the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two neighboring conductive structures by the first pitch as measured in the second direction,the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two neighboring conductive structures,the non-gate forming conductive structure having an overall length as measured in the first direction that is substantially equal to an overall length as measured in the first direction of at least one of the at least two neighboring conductive structures.
17. The semiconductor chip as recited in claim 16, wherein the region includes a first connection forming conductive structure positioned to physically join to the top surface of the second conductive structure, wherein the first connection forming conductive structure is positioned a first connection distance away from a nearest gate electrode forming portion of the second conductive structure, the first connection distance measured in the first direction between closest located portions of the first connection forming conductive structure and the nearest gate electrode forming portion of the second conductive structure, wherein the region includes a second connection forming conductive structure positioned to physically join to the top surface of the third conductive structure, wherein the second connection forming conductive structure is positioned a second connection distance away from a nearest gate electrode forming portion of the third conductive structure, the second connection distance measured in the first direction between closest located portions of the second connection forming conductive structure and the nearest gate electrode forming portion of the third conductive structure,wherein the region includes a third connection forming conductive structure positioned to physically join to the top surface of the fourth conductive structure, wherein the third connection forming conductive structure is positioned a third connection distance away from a nearest gate electrode forming portion of the fourth conductive structure, the third connection distance measured in the first direction between closest located portions of the third connection forming conductive structure and the nearest gate electrode forming portion of the fourth conductive structure,wherein the region includes a fourth connection foil ng conductive structure positioned to physically join to the top surface of the fifth conductive structure, wherein the fourth connection forming conductive structure is positioned a fourth connection distance away from a nearest gate electrode forming portion of the fifth conductive structure, the fourth connection distance measured in the first direction between closest located portions of the fourth connection forming conductive structure and the nearest gate electrode forming portion of the fifth conductive structure,wherein at least two of the first, second, third, and fourth connection distances are different.
18. The semiconductor chip as recited in claim 17, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline.
19. The semiconductor chip as recited in claim 14, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline.
20. The semiconductor chip as recited in claim 14, wherein three of the first, second, third, fourth, and fifth conductive structures have different lengths.
21. The semiconductor chip as recited in claim 20, wherein the region includes a first connection forming conductive structure positioned to physically join to the top surface of the second conductive structure, wherein the region includes a second connection forming conductive structure positioned to physically join to the top surface of the third conductive structure,wherein the region includes a third connection forming conductive structure positioned to physically join to the top surface of the fourth conductive structure,wherein the region includes a fourth connection forming conductive structure positioned to physically join to the top surface of the fifth conductive structure,wherein at least one of the first, second, third, and fourth connection forming conductive structures is positioned at a respective location that is not directly above any gate electrode of any transistor of the first collection of transistors and that is not directly above any gate electrode of any transistor of the second collection of transistors and that is not directly above the inner sub-region of the region.
22. The semiconductor chip as recited in claim 21, wherein the first connection forming conductive structure is positioned a first connection distance away from a nearest gate electrode forming portion of the second conductive structure, the first connection distance measured in the first direction between closest located portions of the first connection forming conductive structure and the nearest gate electrode forming portion of the second conductive structure, wherein the second connection forming conductive structure is positioned a second connection distance away from a nearest gate electrode forming portion of the third conductive structure, the second connection distance measured in the first direction between closest located portions of the second connection forming conductive structure and the nearest gate electrode forming portion of the third conductive structure,wherein the third connection forming conductive structure is positioned a third connection distance away from a nearest gate electrode forming portion of the fourth conductive structure, the third connection distance measured in the first direction between closest located portions of the third connection forming conductive structure and the nearest gate electrode forming portion of the fourth conductive structure,wherein the fourth connection forming conductive structure is positioned a fourth connection distance away from a nearest gate electrode forming portion of the fifth conductive structure, the fourth connection distance measured in the first direction between closest located portions of the fourth connection forming conductive structure and the nearest gate electrode forming portion of the fifth conductive structure,wherein at least two of the first, second, third, and fourth connection distances are different.
23. The semiconductor chip as recited in claim 22, wherein the first connection forming conductive structure is positioned a first extension distance away from an extension end of the second conductive structure, wherein the extension end of the second conductive structure is either the first end or the second end of the second conductive structure, the first extension distance measured in the first direction pointing away from the gate electrode of the second transistor of the first transistor type from a location on the first connection forming conductive structure closest to the extension end of the second conductive structure, wherein the second connection forming conductive structure is positioned a second extension distance away from an extension end of the third conductive structure, wherein the extension end of the third conductive structure is either the first end or the second end of the third conductive structure, the second extension distance measured in the first direction pointing away from the gate electrode of the second transistor of the second transistor type from a location on the second connection forming conductive structure closest to the extension end of the third conductive structure,wherein the third connection forming conductive structure is positioned a third extension distance away from an extension end of the fourth conductive structure, wherein the extension end of the fourth conductive structure is either the first end or the second end of the fourth conductive structure, the third extension distance measured in the first direction pointing away from the gate electrode of the third transistor of the first transistor type from a location on the third connection forming conductive structure closest to the extension end of the fourth conductive structure,wherein the fourth connection forming conductive structure is positioned a fourth extension distance away from an extension end of the fifth conductive structure, wherein the extension end of the fifth conductive structure is either the first end or the second end of the fifth conductive structure, the fourth extension distance measured in the first direction pointing away from the gate electrode of the third transistor of the second transistor type from a location on the fourth connection forming conductive structure closest to the extension end of the fifth conductive structure, andwherein at least two of the first, second, third, and fourth extension distances are different.
24. The semiconductor chip as recited in claim 21, wherein at least two of the first, second, third, and fourth connection forming conductive structures is positioned at a respective location that is not directly above any gate electrode of any transistor of the first collection of transistors and that is not directly above any gate electrode of any transistor of the second collection of transistors and that is not directly above the inner sub-region of the region.
25. The semiconductor chip as recited in claim 24, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor, the non-gate forming conductive structure positioned between at least two neighboring conductive structures of the at least eight conductive structures, with at least one of the at least two neighboring conductive structures forming at least one gate electrode of at least one transistor,the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two neighboring conductive structures by the first pitch as measured in the second direction,the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two neighboring conductive structures.
26. The semiconductor chip as recited in claim 25, wherein the region includes a first gate contact positioned to physically contact the top surface of the first conductive structure, the first gate contact substantially centered in the second direction upon the first conductive structure, the first gate contact formed to extend in a vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the first conductive structure through a dielectric material to contact at least one interconnect conductive structure, wherein the region includes a second gate contact positioned to physically contact the top surface of the second conductive structure, the second gate contact substantially centered in the second direction upon the second conductive structure, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the second conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a third gate contact positioned to physically contact the top surface of the third conductive structure, the third gate contact substantially centered in the second direction upon the third conductive structure, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the third conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a fourth gate contact positioned to physically contact the top surface of the fourth conductive structure, the fourth gate contact substantially centered in the second direction upon the fourth conductive structure, the fourth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the fourth conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a fifth gate contact positioned to physically contact the top surface of the fifth conductive structure, the fifth gate contact substantially centered in the second direction upon the fifth conductive structure, the fifth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the fifth conductive structure through the dielectric material to contact at least one interconnect conductive structure.
27. The semiconductor chip as recited in claim 25, wherein the first connection forming conductive structure is positioned a first extension distance away from an extension end of the second conductive structure, wherein the extension end of the second conductive structure is either the first end or the second end of the second conductive structure, the first extension distance measured in the first direction pointing away from the gate electrode of the second transistor of the first transistor type from a location on the first connection forming conductive structure closest to the extension end of the second conductive structure, wherein the second connection forming conductive structure is positioned a second extension distance away from an extension end of the third conductive structure, wherein the extension end of the third conductive structure is either the first end or the second end of the third conductive structure, the second extension distance measured in the first direction pointing away from the gate electrode of the second transistor of the second transistor type from a location on the second connection forming conductive structure closest to the extension end of the third conductive structure,wherein the third connection forming conductive structure is positioned a third extension distance away from an extension end of the fourth conductive structure, wherein the extension end of the fourth conductive structure is either the first end or the second end of the fourth conductive structure, the third extension distance measured in the first direction pointing away from the gate electrode of the third transistor of the first transistor type from a location on the third connection forming conductive structure closest to the extension end of the fourth conductive structure,wherein the fourth connection forming conductive structure is positioned a fourth extension distance away from an extension end of the fifth conductive structure, wherein the extension end of the fifth conductive structure is either the first end or the second end of the fifth conductive structure, the fourth extension distance measured in the first direction pointing away from the gate electrode of the third transistor of the second transistor type from a location on the fourth connection forming conductive structure closest to the extension end of the fifth conductive structure, andwherein at least two of the first, second, third, and fourth extension distances are different.
28. A method for manufacturing an integrated circuit within a semiconductor chip, comprising: forming a plurality of transistors within a region of the semiconductor chip, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the plurality of transistors having respective gate electrodes formed by some of at least eight conductive structures present within the region,wherein forming the plurality of transistors includes forming each of the at least eight conductive structures to respectively have a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least eight conductive structures co-planar with each other,wherein forming the plurality of transistors includes forming each of the at least eight conductive structures to have a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least eight conductive structures is substantially straight,wherein the second edge of each of the at least eight conductive structures is substantially straight,each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline, wherein the width of each of the at least eight conductive structures is less than 45 nanometers,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,wherein forming the plurality of transistors includes positioning the at least eight conductive structures in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least eight conductive structures,and wherein each of the at least eight conductive structures is positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,the at least eight conductive structures including a first conductive structure, the first conductive structure including a portion that forms a gate electrode of first transistor of a first transistor type, the first conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type,the at least eight conductive structures including a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,the at least eight conductive structures including a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,the at least eight conductive structures including a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,the at least eight conductive structures including a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,the first transistor of the first transistor type including a first diffusion terminal electrically connected to a first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,the first transistor of the second transistor type including a first diffusion terminal electrically connected to a first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,the second transistor of the first transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,the second transistor of the second transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,the third transistor of the first transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the first transistor type through a fifth electrical connection,the third transistor of the second transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the second transistor type through a sixth electrical connection,wherein the third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection, wherein the seventh electrical connection is formed to include one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline,wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,wherein the region has a size of about 965 nanometers as measured in the second direction.
29. The method as recited in claim 28, further comprising: forming a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level,the first interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure; andforming a second interconnect conductive structure at a position next to and spaced apart from the first interconnect conductive structure in a same interconnect level as the first interconnect conductive structure,the second interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,wherein the first and second interconnect conductive structures are positioned such that a distance as measured in the second direction between their lengthwise centerlines is substantially equal to a second pitch, wherein the second pitch is a fractional multiple of the first pitch, and wherein the second pitch is less than or equal to the first pitch,wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, andwherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level.
30. The method as recited in claim 29, wherein the eighth electrical connection is formed to include one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline.

CLAIM OF PRIORITY

This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/774,919, filed on Feb. 22, 2013, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/572,225, filed on Oct. 1, 2009, issued as U.S. Pat. No. 8,436,400, on May 7, 2013, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/212,562, filed Sep. 17, 2008, issued as U.S. Pat. No. 7,842,975, on Nov. 30, 2010, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 11/683,402, filed Mar. 7, 2007, issued as U.S. Pat. No. 7,446,352, on Nov. 4, 2008, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/781,288, filed Mar. 9, 2006. Each of the above-identified applications is incorporated herein by reference in its entirety. This application is related to each application identified in the table below. The disclosure of each application identified in the table below is incorporated herein by reference in its entirety. applicationSer. No.Filing Date12/561,207Sep. 16, 200912/561,216Sep. 16, 200912/561,220Sep. 16, 200912/561,224Sep. 16, 200912/561,229Sep. 16, 200912/561,234Sep. 16, 200912/561,238Sep. 16, 200912/561,243Sep. 16, 200912/561,246Sep. 16, 200912/561,247Sep. 16, 200912/563,031Sep. 18, 200912/563,042Sep. 18, 200912/563,051Sep. 18, 200912/563,056Sep. 18, 200912/563,061Sep. 18, 200912/563,063Sep. 18, 200912/563,066Sep. 18, 200912/563,074Sep. 18, 200912/563,076Sep. 18, 200912/563,077Sep. 18, 200912/567,528Sep. 25, 200912/567,542Sep. 25, 200912/567,555Sep. 25, 200912/567,565Sep. 25, 200912/567,574Sep. 25, 200912/567,586Sep. 25, 200912/567,597Sep. 25, 200912/567,602Sep. 25, 200912/567,609Sep. 25, 200912/567,616Sep. 25, 200912/567,623Sep. 25, 200912/567,630Sep. 25, 200912/567,634Sep. 25, 200912/567,641Sep. 25, 200912/567,648Sep. 25, 200912/567,654Sep. 25, 200912/571,343Sep. 30, 200912/571,351Sep. 30, 200912/571,357Sep. 30, 200912/571,998Oct. 1, 200912/572,011Oct. 1, 200912/572,022Oct. 1, 200912/572,046Oct. 1, 200912/572,055Oct. 1, 200912/572,061Oct. 1, 200912/572,068Oct. 1, 200912/572,077Oct. 1, 200912/572,091Oct. 1, 200912/572,194Oct. 1, 200912/572,201Oct. 1, 200912/572,212Oct. 1, 200912/572,218Oct. 1, 200912/572,221Oct. 1, 200912/572,225Oct. 1, 200912/572,228Oct. 1, 200912/572,229Oct. 1, 200912/572,232Oct. 1, 200912/572,237Oct. 1, 200912/572,239Oct. 1, 200912/572,243Oct. 1, 200913/774,919Feb. 22, 201313/774,940Feb. 22, 201313/774,954Feb. 22, 201313/774,970Feb. 22, 201313/827,615Mar. 14, 201313/827,755Mar. 14, 201313/834,302Mar. 15, 201313/837,123Mar. 15, 201314/304,778Jun. 13, 201414/711,731May 13, 201514/731,316Jun. 4, 201512/013,342Jan. 11, 200813/073,994Mar. 28, 201112/013,356Jan. 11, 200813/047,474Mar. 14, 201114/276,528May 13, 201412/013,366Jan. 11, 200813/007,582Jan. 14, 201113/007,584Jan. 14, 201112/363,705Jan. 30, 200913/897,307May 17, 201314/216,891Mar. 17, 201412/402,465Mar. 11, 200912/753,711Apr. 2, 201012/753,727Apr. 2, 201012/753,733Apr. 2, 201012/753,740Apr. 2, 201012/753,753Apr. 2, 201012/753,758Apr. 2, 201013/741,298Jan. 14, 201312/753,766Apr. 2, 201013/589,028Aug. 17, 201212/753,776Apr. 2, 201012/753,789Apr. 2, 201012/753,793Apr. 2, 201012/753,795Apr. 2, 201012/753,798Apr. 2, 201013/741,305Jan. 14, 201312/753,805Apr. 2, 201012/753,810Apr. 2, 201012/753,817Apr. 2, 201012/754,050Apr. 5, 201012/754,061Apr. 5, 201012/754,078Apr. 5, 201012/754,091Apr. 5, 201012/754,103Apr. 5, 201012/754,114Apr. 5, 201012/754,129Apr. 5, 201012/754,147Apr. 5, 201012/754,168Apr. 5, 201012/754,215Apr. 5, 201012/754,233Apr. 5, 201012/754,351Apr. 5, 201013/591,141Aug. 21, 201212/754,384Apr. 5, 201012/754,563Apr. 5, 201012/754,566Apr. 5, 201013/831,530Mar. 14, 201313/831,605Mar. 15, 201313/831,636Mar. 15, 201313/831,664Mar. 15, 201313/831,717Mar. 15, 201313/831,742Mar. 15, 201313/831,811Mar. 15, 201313/831,832Mar. 15, 201314/242,308Apr. 1, 201414/273,483May 8, 201414/303,587Jun. 12, 201414/476,511Sep. 3, 201414/642,633Mar. 9, 201514/945,361Nov. 18, 201512/399,948Mar. 7, 200912/411,249Mar. 25, 200913/085,447Apr. 12, 201113/918,890Jun. 14, 201314/298,206Jun. 6, 201412/484,130Jun. 12, 200912/479,674Jun. 5, 200912/481,445Jun. 9, 200913/898,155May 20, 201312/497,052Jul. 2, 200913/540,529Jul. 2, 201214/040,590Sep. 27, 201314/605,946Jan. 26, 201512/466,335May 14, 200912/466,341May 14, 200912/512,932Jul. 30, 200914/834,295Aug. 24, 201512/435,672May 5, 200914/181,556Feb. 14, 201412/775,429May 6, 201012/904,134Oct. 13, 201014/187,171Feb. 21, 201413/373,470Nov. 14, 201114/875,570Oct. 5, 201513/312,673Dec. 6, 201114/481,845Sep. 9, 201413/473,439May 16, 201214/187,088Feb. 21, 201413/740,191Jan. 12, 201313/841,951Mar. 15, 2013

US Referenced Citations (827)

Number	Name	Date	Kind
4069493	Bobenrieth	Jan 1978	A
4197555	Uehara et al.	Apr 1980	A
4417161	Uya	Nov 1983	A
4424460	Best	Jan 1984	A
4602270	Finegold	Jul 1986	A
4613940	Shenton et al.	Sep 1986	A
4657628	Holloway et al.	Apr 1987	A
4682202	Tanizawa	Jul 1987	A
4745084	Rowson et al.	May 1988	A
4780753	Ohkura et al.	Oct 1988	A
4801986	Chang et al.	Jan 1989	A
4804636	Groover, III	Feb 1989	A
4812688	Chu et al.	Mar 1989	A
4884115	Michel et al.	Nov 1989	A
4928160	Crafts	May 1990	A
4975756	Haken et al.	Dec 1990	A
5047979	Leung	Sep 1991	A
5068603	Mahoney	Nov 1991	A
5079614	Khatakhotan	Jan 1992	A
5097422	Corbin et al.	Mar 1992	A
5117277	Yuyama et al.	May 1992	A
5121186	Wong et al.	Jun 1992	A
5208765	Turnbull	May 1993	A
5224057	Igarashi	Jun 1993	A
5242770	Chen et al.	Sep 1993	A
5268319	Harari	Dec 1993	A
5298774	Ueda et al.	Mar 1994	A
5313426	Sakuma et al.	May 1994	A
5338963	Klaasen	Aug 1994	A
5351197	Upton et al.	Sep 1994	A
5359226	DeJong	Oct 1994	A
5365454	Nakagawa et al.	Nov 1994	A
5367187	Yuen	Nov 1994	A
5378649	Huang	Jan 1995	A
5396128	Dunning et al.	Mar 1995	A
5420447	Waggoner	May 1995	A
5461577	Shaw et al.	Oct 1995	A
5471403	Fujimaga	Nov 1995	A
5497334	Russell et al.	Mar 1996	A
5497337	Ponnapalli et al.	Mar 1996	A
5526307	Lin et al.	Jun 1996	A
5536955	Ali	Jul 1996	A
5545904	Orbach	Aug 1996	A
5581098	Chang	Dec 1996	A
5581202	Yano et al.	Dec 1996	A
5612893	Hao et al.	Mar 1997	A
5636002	Garofalo	Jun 1997	A
5656861	Godinho et al.	Aug 1997	A
5682323	Pasch et al.	Oct 1997	A
5684311	Shaw	Nov 1997	A
5684733	Wu et al.	Nov 1997	A
5698873	Colwell et al.	Dec 1997	A
5705301	Garza et al.	Jan 1998	A
5723883	Gheewalla	Mar 1998	A
5723908	Fuchida et al.	Mar 1998	A
5740068	Liebmann et al.	Apr 1998	A
5745374	Matsumoto	Apr 1998	A
5764533	deDood	Jun 1998	A
5774367	Reyes et al.	Jun 1998	A
5780909	Hayashi	Jul 1998	A
5789776	Lancaster et al.	Aug 1998	A
5790417	Chao et al.	Aug 1998	A
5796128	Tran et al.	Aug 1998	A
5796624	Sridhar et al.	Aug 1998	A
5798298	Yang et al.	Aug 1998	A
5814844	Nagata et al.	Sep 1998	A
5825203	Kusunoki et al.	Oct 1998	A
5834851	Ikeda et al.	Nov 1998	A
5838594	Kojima	Nov 1998	A
5841663	Sharma et al.	Nov 1998	A
5847421	Yamaguchi	Dec 1998	A
5850362	Sakuma et al.	Dec 1998	A
5852562	Shinomiya et al.	Dec 1998	A
5858580	Wang et al.	Jan 1999	A
5898194	Gheewala	Apr 1999	A
5900340	Reich et al.	May 1999	A
5905287	Hirata	May 1999	A
5908827	Sirna	Jun 1999	A
5915199	Hsu	Jun 1999	A
5917207	Colwell et al.	Jun 1999	A
5920486	Beahm et al.	Jul 1999	A
5923059	Gheewala	Jul 1999	A
5923060	Gheewala	Jul 1999	A
5929469	Mimoto et al.	Jul 1999	A
5930163	Hara et al.	Jul 1999	A
5935763	Caterer et al.	Aug 1999	A
5949101	Aritome	Sep 1999	A
5973507	Yamazaki	Oct 1999	A
5977305	Wigler et al.	Nov 1999	A
5977574	Schmitt et al.	Nov 1999	A
5998879	Iwaki et al.	Dec 1999	A
6009251	Ho et al.	Dec 1999	A
6026223	Scepanovic et al.	Feb 2000	A
6037613	Mariyama	Mar 2000	A
6037617	Kumagai	Mar 2000	A
6044007	Capodieci	Mar 2000	A
6054872	Fudanuki et al.	Apr 2000	A
6063132	DeCamp et al.	May 2000	A
6077310	Yamamoto et al.	Jun 2000	A
6080206	Tadokoro et al.	Jun 2000	A
6084255	Ueda	Jul 2000	A
6084437	Sako	Jul 2000	A
6091845	Pierrat et al.	Jul 2000	A
6099584	Arnold et al.	Aug 2000	A
6100025	Wigler et al.	Aug 2000	A
6114071	Chen et al.	Sep 2000	A
6144227	Sato	Nov 2000	A
6159839	Jeng et al.	Dec 2000	A
6166415	Sakemi et al.	Dec 2000	A
6166560	Ogura et al.	Dec 2000	A
6174742	Sudhindranath et al.	Jan 2001	B1
6182272	Andreev et al.	Jan 2001	B1
6194104	Hsu	Feb 2001	B1
6194252	Yamaguchi	Feb 2001	B1
6194912	Or-Bach	Feb 2001	B1
6209123	Maziasz et al.	Mar 2001	B1
6230299	McSherry et al.	May 2001	B1
6232173	Hsu et al.	May 2001	B1
6240542	Kapur	May 2001	B1
6249902	Igusa et al.	Jun 2001	B1
6255600	Schaper	Jul 2001	B1
6255845	Wong et al.	Jul 2001	B1
6262487	Igarashi et al.	Jul 2001	B1
6269472	Garza et al.	Jul 2001	B1
6275973	Wein	Aug 2001	B1
6282696	Garza et al.	Aug 2001	B1
6291276	Gonzalez	Sep 2001	B1
6297668	Schober	Oct 2001	B1
6297674	Kono et al.	Oct 2001	B1
6303252	Lin	Oct 2001	B1
6331733	Or-Bach et al.	Dec 2001	B1
6331791	Huang	Dec 2001	B1
6335250	Egi	Jan 2002	B1
6338972	Sudhindranath et al.	Jan 2002	B1
6347062	Nii et al.	Feb 2002	B2
6356112	Tran et al.	Mar 2002	B1
6359804	Kuriyama et al.	Mar 2002	B2
6370679	Chang et al.	Apr 2002	B1
6378110	Ho	Apr 2002	B1
6380592	Tooher et al.	Apr 2002	B2
6388296	Hsu	May 2002	B1
6393601	Tanaka et al.	May 2002	B1
6399972	Masuda et al.	Jun 2002	B1
6400183	Yamashita et al.	Jun 2002	B2
6408427	Cong et al.	Jun 2002	B1
6415421	Anderson et al.	Jul 2002	B2
6416907	Winder et al.	Jul 2002	B1
6417549	Oh	Jul 2002	B1
6421820	Mansfield et al.	Jul 2002	B1
6425112	Bula et al.	Jul 2002	B1
6425117	Pasch et al.	Jul 2002	B1
6426269	Haffner et al.	Jul 2002	B1
6436805	Trivedi	Aug 2002	B1
6445049	Iranmanesh	Sep 2002	B1
6445065	Gheewala et al.	Sep 2002	B1
6467072	Yang et al.	Oct 2002	B1
6469328	Yanai et al.	Oct 2002	B2
6470489	Chang et al.	Oct 2002	B1
6476493	Or-Bach et al.	Nov 2002	B2
6477695	Gandhi	Nov 2002	B1
6480032	Aksamit	Nov 2002	B1
6480989	Chan et al.	Nov 2002	B2
6492066	Capodieci et al.	Dec 2002	B1
6496965	van Ginneken et al.	Dec 2002	B1
6504186	Kanamoto et al.	Jan 2003	B2
6505327	Lin	Jan 2003	B2
6505328	van Ginneken et al.	Jan 2003	B1
6507941	Leung et al.	Jan 2003	B1
6509952	Govil et al.	Jan 2003	B1
6514849	Hui et al.	Feb 2003	B1
6516459	Sahouria	Feb 2003	B1
6523156	Cirit	Feb 2003	B2
6525350	Kinoshita et al.	Feb 2003	B1
6536028	Katsioulas et al.	Mar 2003	B1
6543039	Watanabe	Apr 2003	B1
6553544	Tanaka et al.	Apr 2003	B2
6553559	Liebmann et al.	Apr 2003	B2
6553562	Capodieci et al.	Apr 2003	B2
6566720	Aldrich	May 2003	B2
6570234	Gardner	May 2003	B1
6571140	Wewalaarachchi	May 2003	B1
6571379	Takayama	May 2003	B2
6574786	Pohlenz et al.	Jun 2003	B1
6578190	Ferguson et al.	Jun 2003	B2
6583041	Capodieci	Jun 2003	B1
6588005	Kobayashi et al.	Jul 2003	B1
6590289	Shively	Jul 2003	B2
6591207	Naya et al.	Jul 2003	B2
6609235	Ramaswamy et al.	Aug 2003	B2
6610607	Armbrust et al.	Aug 2003	B1
6617621	Gheewala et al.	Sep 2003	B1
6620561	Winder et al.	Sep 2003	B2
6621132	Onishi et al.	Sep 2003	B2
6632741	Clevenger et al.	Oct 2003	B1
6633182	Pileggi et al.	Oct 2003	B2
6635935	Makino	Oct 2003	B2
6642744	Or-Bach et al.	Nov 2003	B2
6643831	Chang et al.	Nov 2003	B2
6650014	Kariyazaki	Nov 2003	B2
6661041	Keeth	Dec 2003	B2
6662350	Fried et al.	Dec 2003	B2
6664587	Guterman et al.	Dec 2003	B2
6673638	Bendik et al.	Jan 2004	B1
6677649	Minami et al.	Jan 2004	B2
6687895	Zhang	Feb 2004	B2
6690206	Rikino et al.	Feb 2004	B2
6691297	Misaka et al.	Feb 2004	B1
6700405	Hirairi	Mar 2004	B1
6703170	Pindo	Mar 2004	B1
6709880	Yamamoto et al.	Mar 2004	B2
6714903	Chu et al.	Mar 2004	B1
6732334	Nakatsuka	May 2004	B2
6732338	Crouse et al.	May 2004	B2
6732344	Sakamoto et al.	May 2004	B2
6734506	Oyamatsu	May 2004	B2
6737199	Hsieh	May 2004	B1
6737318	Murata et al.	May 2004	B2
6737347	Houston et al.	May 2004	B1
6745372	Cote et al.	Jun 2004	B2
6745380	Bodendorf et al.	Jun 2004	B2
6749972	Yu	Jun 2004	B2
6750555	Satomi et al.	Jun 2004	B2
6760269	Nakase et al.	Jul 2004	B2
6765245	Bansal	Jul 2004	B2
6777138	Pierrat et al.	Aug 2004	B2
6777146	Samuels	Aug 2004	B1
6787823	Shibutani	Sep 2004	B2
6789244	Dasasathyan et al.	Sep 2004	B1
6789246	Mohan et al.	Sep 2004	B1
6792591	Shi et al.	Sep 2004	B2
6792593	Takashima et al.	Sep 2004	B2
6794677	Tamaki et al.	Sep 2004	B2
6794914	Sani et al.	Sep 2004	B2
6795332	Yamaoka et al.	Sep 2004	B2
6795358	Tanaka et al.	Sep 2004	B2
6795952	Stine et al.	Sep 2004	B1
6795953	Bakarian et al.	Sep 2004	B2
6800883	Furuya et al.	Oct 2004	B2
6806180	Cho	Oct 2004	B2
6807663	Cote et al.	Oct 2004	B2
6809399	Ikeda et al.	Oct 2004	B2
6812574	Tomita et al.	Nov 2004	B2
6818389	Fritze et al.	Nov 2004	B2
6818929	Tsutsumi et al.	Nov 2004	B2
6819136	Or-Bach	Nov 2004	B2
6820248	Gan	Nov 2004	B1
6826738	Cadouri	Nov 2004	B2
6834375	Stine et al.	Dec 2004	B1
6841880	Matsumoto et al.	Jan 2005	B2
6850854	Naya et al.	Feb 2005	B2
6854096	Eaton et al.	Feb 2005	B2
6854100	Chuang et al.	Feb 2005	B1
6867073	Enquist	Mar 2005	B1
6871338	Yamauchi	Mar 2005	B2
6872990	Kang	Mar 2005	B1
6877144	Rittman et al.	Apr 2005	B1
6881523	Smith	Apr 2005	B2
6884712	Yelehanka et al.	Apr 2005	B2
6885045	Hidaka	Apr 2005	B2
6889370	Kerzman et al.	May 2005	B1
6897517	Houdt et al.	May 2005	B2
6897536	Nomura et al.	May 2005	B2
6898770	Boluki et al.	May 2005	B2
6904582	Rittman et al.	Jun 2005	B1
6918104	Pierrat et al.	Jul 2005	B2
6920079	Shibayama	Jul 2005	B2
6921982	Joshi et al.	Jul 2005	B2
6922354	Ishikura et al.	Jul 2005	B2
6924560	Wang et al.	Aug 2005	B2
6928635	Pramanik et al.	Aug 2005	B2
6931617	Sanie et al.	Aug 2005	B2
6953956	Or-Bach et al.	Oct 2005	B2
6954918	Houston	Oct 2005	B2
6957402	Templeton et al.	Oct 2005	B2
6968527	Pierrat	Nov 2005	B2
6974978	Possley	Dec 2005	B1
6977856	Tanaka et al.	Dec 2005	B2
6978436	Cote et al.	Dec 2005	B2
6978437	Rittman et al.	Dec 2005	B1
6980211	Lin et al.	Dec 2005	B2
6992394	Park	Jan 2006	B2
6992925	Peng	Jan 2006	B2
6993741	Liebmann et al.	Jan 2006	B2
6994939	Ghandehari et al.	Feb 2006	B1
6998722	Madurawe	Feb 2006	B2
7003068	Kushner et al.	Feb 2006	B2
7009862	Higeta et al.	Mar 2006	B2
7016214	Kawamata	Mar 2006	B2
7022559	Barnak et al.	Apr 2006	B2
7028285	Cote et al.	Apr 2006	B2
7041568	Goldbach et al.	May 2006	B2
7052972	Sandhu et al.	May 2006	B2
7053424	Ono	May 2006	B2
7063920	Baba-Ali	Jun 2006	B2
7064068	Chou et al.	Jun 2006	B2
7065731	Jacques et al.	Jun 2006	B2
7079413	Tsukamoto et al.	Jul 2006	B2
7079989	Wimer	Jul 2006	B2
7093208	Williams et al.	Aug 2006	B2
7093228	Andreev et al.	Aug 2006	B2
7103870	Misaka et al.	Sep 2006	B2
7105871	Or-Bach et al.	Sep 2006	B2
7107551	de Dood et al.	Sep 2006	B1
7115343	Gordon et al.	Oct 2006	B2
7115920	Bernstein et al.	Oct 2006	B2
7120882	Kotani et al.	Oct 2006	B2
7124386	Smith et al.	Oct 2006	B2
7126837	Banachowicz et al.	Oct 2006	B1
7132203	Pierrat	Nov 2006	B2
7137092	Maeda	Nov 2006	B2
7141853	Campbell et al.	Nov 2006	B2
7143380	Anderson et al.	Nov 2006	B1
7149999	Kahng et al.	Dec 2006	B2
7152215	Smith et al.	Dec 2006	B2
7155685	Mori et al.	Dec 2006	B2
7155689	Pierrat et al.	Dec 2006	B2
7159197	Falbo et al.	Jan 2007	B2
7174520	White et al.	Feb 2007	B2
7175940	Laidig et al.	Feb 2007	B2
7176508	Joshi et al.	Feb 2007	B2
7177215	Tanaka et al.	Feb 2007	B2
7183611	Bhattacharyya	Feb 2007	B2
7185294	Zhang	Feb 2007	B2
7188322	Cohn et al.	Mar 2007	B2
7194712	Wu	Mar 2007	B2
7200835	Zhang et al.	Apr 2007	B2
7202517	Dixit et al.	Apr 2007	B2
7205191	Kobayashi	Apr 2007	B2
7208794	Hofmann et al.	Apr 2007	B2
7214579	Widdershoven et al.	May 2007	B2
7219326	Reed et al.	May 2007	B2
7221031	Ryoo et al.	May 2007	B2
7225423	Bhattacharya et al.	May 2007	B2
7227183	Donze et al.	Jun 2007	B2
7228510	Ono	Jun 2007	B2
7231628	Pack et al.	Jun 2007	B2
7235424	Chen et al.	Jun 2007	B2
7243316	White et al.	Jul 2007	B2
7252909	Shin et al.	Aug 2007	B2
7257017	Liaw	Aug 2007	B2
7264990	Rueckes et al.	Sep 2007	B2
7266787	Hughes et al.	Sep 2007	B2
7269803	Khakzadi et al.	Sep 2007	B2
7278118	Pileggi et al.	Oct 2007	B2
7279727	Ikoma et al.	Oct 2007	B2
7287320	Wang et al.	Oct 2007	B2
7294534	Iwaki	Nov 2007	B2
7302651	Allen et al.	Nov 2007	B2
7308669	Buehler et al.	Dec 2007	B2
7312003	Cote et al.	Dec 2007	B2
7315994	Aller et al.	Jan 2008	B2
7327591	Sadra et al.	Feb 2008	B2
7329938	Kinoshita	Feb 2008	B2
7335966	Ihme et al.	Feb 2008	B2
7337421	Kamat	Feb 2008	B2
7338896	Vanhaelemeersch et al.	Mar 2008	B2
7345909	Chang et al.	Mar 2008	B2
7346885	Semmler	Mar 2008	B2
7350183	Cui et al.	Mar 2008	B2
7353492	Gupta et al.	Apr 2008	B2
7358131	Bhattacharyya	Apr 2008	B2
7360179	Smith et al.	Apr 2008	B2
7360198	Rana et al.	Apr 2008	B2
7366997	Rahmat et al.	Apr 2008	B1
7367008	White et al.	Apr 2008	B2
7376931	Kokubun	May 2008	B2
7383521	Smith et al.	Jun 2008	B2
7397260	Chanda et al.	Jul 2008	B2
7400627	Wu et al.	Jul 2008	B2
7402848	Chang et al.	Jul 2008	B2
7404154	Venkatraman et al.	Jul 2008	B1
7404173	Wu et al.	Jul 2008	B2
7411252	Anderson et al.	Aug 2008	B2
7421678	Barnes et al.	Sep 2008	B2
7423298	Mariyama et al.	Sep 2008	B2
7424694	Ikeda	Sep 2008	B2
7424695	Tamura et al.	Sep 2008	B2
7424696	Vogel et al.	Sep 2008	B2
7426710	Zhang et al.	Sep 2008	B2
7432562	Bhattacharyya	Oct 2008	B2
7434185	Dooling et al.	Oct 2008	B2
7441211	Gupta et al.	Oct 2008	B1
7442630	Kelberlau et al.	Oct 2008	B2
7444609	Charlebois et al.	Oct 2008	B2
7446352	Becker et al.	Nov 2008	B2
7449371	Kemerling et al.	Nov 2008	B2
7458045	Cote et al.	Nov 2008	B2
7459792	Chen	Dec 2008	B2
7465973	Chang et al.	Dec 2008	B2
7466607	Hollis et al.	Dec 2008	B2
7469396	Hayashi et al.	Dec 2008	B2
7480880	Visweswariah et al.	Jan 2009	B2
7480891	Sezginer	Jan 2009	B2
7484197	Allen et al.	Jan 2009	B2
7485934	Liaw	Feb 2009	B2
7487475	Kriplani et al.	Feb 2009	B1
7492013	Correale, Jr.	Feb 2009	B2
7500211	Komaki	Mar 2009	B2
7502275	Nii et al.	Mar 2009	B2
7503026	Ichiryu et al.	Mar 2009	B2
7504184	Hung et al.	Mar 2009	B2
7506300	Sezginer et al.	Mar 2009	B2
7508238	Yamagami	Mar 2009	B2
7509621	Melvin, III	Mar 2009	B2
7509622	Sinha et al.	Mar 2009	B2
7512017	Chang	Mar 2009	B2
7512921	Shibuya	Mar 2009	B2
7514355	Katase	Apr 2009	B2
7514959	Or-Bach et al.	Apr 2009	B2
7523429	Kroyan et al.	Apr 2009	B2
7527900	Zhou et al.	May 2009	B2
7538368	Yano	May 2009	B2
7543262	Wang et al.	Jun 2009	B2
7563701	Chang et al.	Jul 2009	B2
7564134	Lee et al.	Jul 2009	B2
7568174	Sezginer et al.	Jul 2009	B2
7569309	Blatchford et al.	Aug 2009	B2
7569310	Wallace et al.	Aug 2009	B2
7569894	Suzuki	Aug 2009	B2
7575973	Mokhlesi et al.	Aug 2009	B2
7598541	Okamoto et al.	Oct 2009	B2
7598558	Hashimoto et al.	Oct 2009	B2
7614030	Hsu	Nov 2009	B2
7625790	Yang	Dec 2009	B2
7632610	Wallace et al.	Dec 2009	B2
7640522	Gupta et al.	Dec 2009	B2
7646651	Lee et al.	Jan 2010	B2
7653884	Furnish et al.	Jan 2010	B2
7665051	Ludwig et al.	Feb 2010	B2
7700466	Booth et al.	Apr 2010	B2
7712056	White et al.	May 2010	B2
7739627	Chew et al.	Jun 2010	B2
7749662	Matthew et al.	Jul 2010	B2
7755110	Gliese et al.	Jul 2010	B2
7770144	Dellinger	Aug 2010	B2
7791109	Wann et al.	Sep 2010	B2
7802219	Tomar et al.	Sep 2010	B2
7825437	Pillarisetty et al.	Nov 2010	B2
7842975	Becker et al.	Nov 2010	B2
7873929	Kahng et al.	Jan 2011	B2
7882456	Zach	Feb 2011	B2
7888705	Becker et al.	Feb 2011	B2
7898040	Nawaz	Mar 2011	B2
7906801	Becker et al.	Mar 2011	B2
7908578	Becker et al.	Mar 2011	B2
7910958	Becker et al.	Mar 2011	B2
7910959	Becker et al.	Mar 2011	B2
7917877	Singh et al.	Mar 2011	B2
7917879	Becker et al.	Mar 2011	B2
7923266	Thijs et al.	Apr 2011	B2
7923337	Chang et al.	Apr 2011	B2
7923757	Becker et al.	Apr 2011	B2
7926001	Pierrat	Apr 2011	B2
7932544	Becker et al.	Apr 2011	B2
7932545	Becker et al.	Apr 2011	B2
7934184	Zhang	Apr 2011	B2
7939443	Fox et al.	May 2011	B2
7943966	Becker et al.	May 2011	B2
7943967	Becker et al.	May 2011	B2
7948012	Becker et al.	May 2011	B2
7948013	Becker et al.	May 2011	B2
7952119	Becker et al.	May 2011	B2
7956421	Becker	Jun 2011	B2
7958465	Lu et al.	Jun 2011	B2
7962867	White et al.	Jun 2011	B2
7962879	Tang et al.	Jun 2011	B2
7964267	Lyons et al.	Jun 2011	B1
7971160	Osawa et al.	Jun 2011	B2
7989847	Becker et al.	Aug 2011	B2
7989848	Becker et al.	Aug 2011	B2
7992122	Burstein et al.	Aug 2011	B1
7994583	Inaba	Aug 2011	B2
8004042	Yang et al.	Aug 2011	B2
8022441	Becker et al.	Sep 2011	B2
8030689	Becker et al.	Oct 2011	B2
8035133	Becker et al.	Oct 2011	B2
8044437	Venkatraman et al.	Oct 2011	B1
8058671	Becker et al.	Nov 2011	B2
8058690	Chang	Nov 2011	B2
8072003	Becker et al.	Dec 2011	B2
8072053	Li	Dec 2011	B2
8088679	Becker et al.	Jan 2012	B2
8088680	Becker et al.	Jan 2012	B2
8088681	Becker et al.	Jan 2012	B2
8088682	Becker et al.	Jan 2012	B2
8089098	Becker et al.	Jan 2012	B2
8089099	Becker et al.	Jan 2012	B2
8089100	Becker et al.	Jan 2012	B2
8089101	Becker et al.	Jan 2012	B2
8089102	Becker et al.	Jan 2012	B2
8089103	Becker et al.	Jan 2012	B2
8089104	Becker et al.	Jan 2012	B2
8101975	Becker et al.	Jan 2012	B2
8110854	Becker et al.	Feb 2012	B2
8129750	Becker et al.	Mar 2012	B2
8129751	Becker et al.	Mar 2012	B2
8129752	Becker et al.	Mar 2012	B2
8129754	Becker et al.	Mar 2012	B2
8129755	Becker et al.	Mar 2012	B2
8129756	Becker et al.	Mar 2012	B2
8129757	Becker et al.	Mar 2012	B2
8129819	Becker et al.	Mar 2012	B2
8130529	Tanaka	Mar 2012	B2
8134183	Becker et al.	Mar 2012	B2
8134184	Becker et al.	Mar 2012	B2
8134185	Becker et al.	Mar 2012	B2
8134186	Becker et al.	Mar 2012	B2
8138525	Becker et al.	Mar 2012	B2
8161427	Morgenshtein et al.	Apr 2012	B2
8178905	Toubou	May 2012	B2
8178909	Venkatraman et al.	May 2012	B2
8198656	Becker et al.	Jun 2012	B2
8207053	Becker et al.	Jun 2012	B2
8214778	Quandt et al.	Jul 2012	B2
8217428	Becker et al.	Jul 2012	B2
8225239	Reed et al.	Jul 2012	B2
8225261	Hong et al.	Jul 2012	B2
8245180	Smayling et al.	Aug 2012	B2
8247846	Becker	Aug 2012	B2
8253172	Becker et al.	Aug 2012	B2
8253173	Becker et al.	Aug 2012	B2
8258547	Becker et al.	Sep 2012	B2
8258548	Becker et al.	Sep 2012	B2
8258549	Becker et al.	Sep 2012	B2
8258550	Becker et al.	Sep 2012	B2
8258551	Becker et al.	Sep 2012	B2
8258552	Becker et al.	Sep 2012	B2
8258581	Becker et al.	Sep 2012	B2
8264007	Becker et al.	Sep 2012	B2
8264008	Becker et al.	Sep 2012	B2
8264009	Becker et al.	Sep 2012	B2
8283701	Becker et al.	Oct 2012	B2
8294212	Wang et al.	Oct 2012	B2
8316327	Herold	Nov 2012	B2
8356268	Becker et al.	Jan 2013	B2
8378407	Audzeyeu et al.	Feb 2013	B2
8395224	Becker et al.	Mar 2013	B2
8402397	Robles et al.	Mar 2013	B2
8405163	Becker et al.	Mar 2013	B2
8422274	Tomita et al.	Apr 2013	B2
8436400	Becker et al.	May 2013	B2
8453094	Kornachuk et al.	May 2013	B2
8575706	Becker et al.	Nov 2013	B2
8667443	Smayling et al.	Mar 2014	B2
8701071	Kornachuk et al.	Apr 2014	B2
8735995	Becker et al.	May 2014	B2
8756551	Becker et al.	Jun 2014	B2
8836045	Becker et al.	Sep 2014	B2
8839162	Amundson et al.	Sep 2014	B2
8839175	Smayling et al.	Sep 2014	B2
8847329	Becker et al.	Sep 2014	B2
8863063	Becker et al.	Oct 2014	B2
9202779	Kornachuk et al.	Dec 2015	B2
20010049813	Chan et al.	Dec 2001	A1
20020003270	Makino	Jan 2002	A1
20020015899	Chen et al.	Feb 2002	A1
20020030510	Kono et al.	Mar 2002	A1
20020063582	Rikino	May 2002	A1
20020068423	Park et al.	Jun 2002	A1
20020079927	Katoh et al.	Jun 2002	A1
20020149392	Cho	Oct 2002	A1
20020166107	Capodieci et al.	Nov 2002	A1
20020194575	Allen et al.	Dec 2002	A1
20030042930	Pileggi et al.	Mar 2003	A1
20030046653	Liu	Mar 2003	A1
20030061592	Agrawal et al.	Mar 2003	A1
20030088839	Watanabe	May 2003	A1
20030088842	Cirit	May 2003	A1
20030103176	Abe et al.	Jun 2003	A1
20030106037	Moniwa et al.	Jun 2003	A1
20030117168	Uneme et al.	Jun 2003	A1
20030124847	Houston et al.	Jul 2003	A1
20030125917	Rich et al.	Jul 2003	A1
20030126569	Rich et al.	Jul 2003	A1
20030145288	Wang et al.	Jul 2003	A1
20030145299	Fried et al.	Jul 2003	A1
20030177465	MacLean et al.	Sep 2003	A1
20030185076	Worley	Oct 2003	A1
20030203287	Miyagawa	Oct 2003	A1
20030229868	White et al.	Dec 2003	A1
20030229875	Smith et al.	Dec 2003	A1
20040029372	Jang et al.	Feb 2004	A1
20040049754	Liao et al.	Mar 2004	A1
20040063038	Shin et al.	Apr 2004	A1
20040115539	Broeke et al.	Jun 2004	A1
20040139412	Ito et al.	Jul 2004	A1
20040145028	Matsumoto et al.	Jul 2004	A1
20040153979	Chang	Aug 2004	A1
20040161878	Or-Bach et al.	Aug 2004	A1
20040164360	Nishida et al.	Aug 2004	A1
20040169201	Hidaka	Sep 2004	A1
20040194050	Hwang et al.	Sep 2004	A1
20040196705	Ishikura et al.	Oct 2004	A1
20040229135	Wang et al.	Nov 2004	A1
20040232444	Shimizu	Nov 2004	A1
20040243966	Dellinger	Dec 2004	A1
20040262640	Suga	Dec 2004	A1
20050009312	Butt et al.	Jan 2005	A1
20050009344	Hwang et al.	Jan 2005	A1
20050012157	Cho et al.	Jan 2005	A1
20050044522	Maeda	Feb 2005	A1
20050055828	Wang et al.	Mar 2005	A1
20050076320	Maeda	Apr 2005	A1
20050087806	Hokazono	Apr 2005	A1
20050093147	Tu	May 2005	A1
20050101112	Rueckes et al.	May 2005	A1
20050110130	Kitabayashi et al.	May 2005	A1
20050135134	Yen	Jun 2005	A1
20050136340	Baselmans et al.	Jun 2005	A1
20050138598	Kokubun	Jun 2005	A1
20050156200	Kinoshita	Jul 2005	A1
20050185325	Hur	Aug 2005	A1
20050189604	Gupta et al.	Sep 2005	A1
20050189614	Ihme et al.	Sep 2005	A1
20050196685	Wang et al.	Sep 2005	A1
20050205894	Sumikawa et al.	Sep 2005	A1
20050212018	Schoellkopf et al.	Sep 2005	A1
20050224982	Kemerling et al.	Oct 2005	A1
20050229130	Wu et al.	Oct 2005	A1
20050251771	Robles	Nov 2005	A1
20050264320	Chan et al.	Dec 2005	A1
20050264324	Nakazato	Dec 2005	A1
20050266621	Kim	Dec 2005	A1
20050268256	Tsai et al.	Dec 2005	A1
20050278673	Kawachi	Dec 2005	A1
20050280031	Yano	Dec 2005	A1
20060038234	Liaw	Feb 2006	A1
20060063334	Donze et al.	Mar 2006	A1
20060070018	Semmler	Mar 2006	A1
20060084261	Iwaki	Apr 2006	A1
20060091550	Shimazaki et al.	May 2006	A1
20060095872	McElvain	May 2006	A1
20060101370	Cui et al.	May 2006	A1
20060112355	Pileggi et al.	May 2006	A1
20060113533	Tamaki et al.	Jun 2006	A1
20060113567	Ohmori et al.	Jun 2006	A1
20060120143	Liaw	Jun 2006	A1
20060121715	Chang et al.	Jun 2006	A1
20060123376	Vogel et al.	Jun 2006	A1
20060125024	Ishigaki	Jun 2006	A1
20060131609	Kinoshita et al.	Jun 2006	A1
20060136848	Ichiryu et al.	Jun 2006	A1
20060146638	Chang et al.	Jul 2006	A1
20060151810	Ohshige	Jul 2006	A1
20060158270	Gibet et al.	Jul 2006	A1
20060177744	Bodendorf et al.	Aug 2006	A1
20060181310	Rhee	Aug 2006	A1
20060195809	Cohn et al.	Aug 2006	A1
20060195810	Morton	Aug 2006	A1
20060197557	Chung	Sep 2006	A1
20060206854	Barnes et al.	Sep 2006	A1
20060223302	Chang et al.	Oct 2006	A1
20060248495	Sezginer	Nov 2006	A1
20060261417	Suzuki	Nov 2006	A1
20060277521	Chen	Dec 2006	A1
20070001304	Liaw	Jan 2007	A1
20070002617	Houston	Jan 2007	A1
20070004147	Toubou	Jan 2007	A1
20070007574	Ohsawa	Jan 2007	A1
20070038973	Li et al.	Feb 2007	A1
20070074145	Tanaka	Mar 2007	A1
20070094634	Seizginer et al.	Apr 2007	A1
20070101305	Smith et al.	May 2007	A1
20070105023	Zhou et al.	May 2007	A1
20070106971	Lien et al.	May 2007	A1
20070113216	Zhang	May 2007	A1
20070172770	Witters et al.	Jul 2007	A1
20070186196	Tanaka	Aug 2007	A1
20070196958	Bhattacharya et al.	Aug 2007	A1
20070209029	Ivonin et al.	Sep 2007	A1
20070210391	Becker et al.	Sep 2007	A1
20070234252	Visweswariah et al.	Oct 2007	A1
20070234262	Uedi et al.	Oct 2007	A1
20070241810	Onda	Oct 2007	A1
20070256039	White	Nov 2007	A1
20070257277	Takeda et al.	Nov 2007	A1
20070264758	Correale	Nov 2007	A1
20070274140	Joshi et al.	Nov 2007	A1
20070277129	Allen et al.	Nov 2007	A1
20070288882	Kniffin et al.	Dec 2007	A1
20070290361	Chen	Dec 2007	A1
20070294652	Bowen	Dec 2007	A1
20070297249	Chang et al.	Dec 2007	A1
20080001176	Gopalakrishnan et al.	Jan 2008	A1
20080005712	Charlebois et al.	Jan 2008	A1
20080021689	Yamashita et al.	Jan 2008	A1
20080022247	Kojima et al.	Jan 2008	A1
20080046846	Chew et al.	Feb 2008	A1
20080081472	Tanaka	Apr 2008	A1
20080082952	O'Brien	Apr 2008	A1
20080086712	Fujimoto	Apr 2008	A1
20080097641	Miyashita et al.	Apr 2008	A1
20080098334	Pileggi et al.	Apr 2008	A1
20080098341	Kobayashi et al.	Apr 2008	A1
20080099795	Bernstein et al.	May 2008	A1
20080127000	Majumder et al.	May 2008	A1
20080127029	Graur et al.	May 2008	A1
20080134128	Blatchford et al.	Jun 2008	A1
20080144361	Wong	Jun 2008	A1
20080148216	Chan et al.	Jun 2008	A1
20080163141	Scheffer et al.	Jul 2008	A1
20080168406	Rahmat et al.	Jul 2008	A1
20080211028	Suzuki	Sep 2008	A1
20080216207	Tsai	Sep 2008	A1
20080244494	McCullen	Oct 2008	A1
20080251779	Kakoschke et al.	Oct 2008	A1
20080265290	Nielsen et al.	Oct 2008	A1
20080276105	Hoberman et al.	Nov 2008	A1
20080283910	Dreeskornfeld et al.	Nov 2008	A1
20080285331	Torok et al.	Nov 2008	A1
20080308848	Inaba	Dec 2008	A1
20080308880	Inaba	Dec 2008	A1
20080315258	Masuda et al.	Dec 2008	A1
20090014811	Becker et al.	Jan 2009	A1
20090024974	Yamada	Jan 2009	A1
20090031261	Smith et al.	Jan 2009	A1
20090032898	Becker et al.	Feb 2009	A1
20090032967	Becker et al.	Feb 2009	A1
20090037864	Becker et al.	Feb 2009	A1
20090057780	Wong et al.	Mar 2009	A1
20090075485	Ban et al.	Mar 2009	A1
20090077524	Nagamura	Mar 2009	A1
20090085067	Hayashi et al.	Apr 2009	A1
20090087991	Yatsuda et al.	Apr 2009	A1
20090101940	Barrows et al.	Apr 2009	A1
20090106714	Culp et al.	Apr 2009	A1
20090155990	Yanagidaira et al.	Jun 2009	A1
20090181314	Shyu et al.	Jul 2009	A1
20090187871	Cork	Jul 2009	A1
20090206443	Juengling	Aug 2009	A1
20090224408	Fox	Sep 2009	A1
20090228853	Hong et al.	Sep 2009	A1
20090228857	Kornachuk et al.	Sep 2009	A1
20090235215	Lavin et al.	Sep 2009	A1
20090273100	Aton et al.	Nov 2009	A1
20090280582	Thijs et al.	Nov 2009	A1
20090302372	Chang et al.	Dec 2009	A1
20090319977	Saxena et al.	Dec 2009	A1
20100001321	Becker et al.	Jan 2010	A1
20100006897	Becker et al.	Jan 2010	A1
20100006898	Becker et al.	Jan 2010	A1
20100006899	Becker et al.	Jan 2010	A1
20100006900	Becker et al.	Jan 2010	A1
20100006901	Becker et al.	Jan 2010	A1
20100006902	Becker et al.	Jan 2010	A1
20100006903	Becker et al.	Jan 2010	A1
20100006947	Becker et al.	Jan 2010	A1
20100006948	Becker et al.	Jan 2010	A1
20100006950	Becker et al.	Jan 2010	A1
20100006951	Becker et al.	Jan 2010	A1
20100006986	Becker et al.	Jan 2010	A1
20100011327	Becker et al.	Jan 2010	A1
20100011328	Becker et al.	Jan 2010	A1
20100011329	Becker et al.	Jan 2010	A1
20100011330	Becker et al.	Jan 2010	A1
20100011331	Becker et al.	Jan 2010	A1
20100011332	Becker et al.	Jan 2010	A1
20100011333	Becker et al.	Jan 2010	A1
20100012981	Becker et al.	Jan 2010	A1
20100012982	Becker et al.	Jan 2010	A1
20100012983	Becker et al.	Jan 2010	A1
20100012984	Becker et al.	Jan 2010	A1
20100012985	Becker et al.	Jan 2010	A1
20100012986	Becker et al.	Jan 2010	A1
20100017766	Becker et al.	Jan 2010	A1
20100017767	Becker et al.	Jan 2010	A1
20100017768	Becker et al.	Jan 2010	A1
20100017769	Becker et al.	Jan 2010	A1
20100017770	Becker et al.	Jan 2010	A1
20100017771	Becker et al.	Jan 2010	A1
20100017772	Becker et al.	Jan 2010	A1
20100019280	Becker et al.	Jan 2010	A1
20100019281	Becker et al.	Jan 2010	A1
20100019282	Becker et al.	Jan 2010	A1
20100019283	Becker et al.	Jan 2010	A1
20100019284	Becker et al.	Jan 2010	A1
20100019285	Becker et al.	Jan 2010	A1
20100019286	Becker et al.	Jan 2010	A1
20100019287	Becker et al.	Jan 2010	A1
20100019288	Becker et al.	Jan 2010	A1
20100019308	Chan et al.	Jan 2010	A1
20100023906	Becker et al.	Jan 2010	A1
20100023907	Becker et al.	Jan 2010	A1
20100023908	Becker et al.	Jan 2010	A1
20100023911	Becker et al.	Jan 2010	A1
20100025731	Becker et al.	Feb 2010	A1
20100025732	Becker et al.	Feb 2010	A1
20100025733	Becker et al.	Feb 2010	A1
20100025734	Becker et al.	Feb 2010	A1
20100025735	Becker et al.	Feb 2010	A1
20100025736	Becker et al.	Feb 2010	A1
20100032722	Becker et al.	Feb 2010	A1
20100032723	Becker et al.	Feb 2010	A1
20100032724	Becker et al.	Feb 2010	A1
20100032726	Becker et al.	Feb 2010	A1
20100037194	Becker et al.	Feb 2010	A1
20100037195	Becker et al.	Feb 2010	A1
20100096671	Becker et al.	Apr 2010	A1
20100115484	Frederick	May 2010	A1
20100203689	Bernstein et al.	Aug 2010	A1
20100224943	Kawasaki	Sep 2010	A1
20100229140	Strolenberg et al.	Sep 2010	A1
20100232212	Anderson et al.	Sep 2010	A1
20100252865	Van Der Zanden	Oct 2010	A1
20100264468	Xu	Oct 2010	A1
20100270681	Bird et al.	Oct 2010	A1
20100287518	Becker	Nov 2010	A1
20100301482	Schultz et al.	Dec 2010	A1
20110016909	Mirza et al.	Jan 2011	A1
20110108890	Becker et al.	May 2011	A1
20110108891	Becker et al.	May 2011	A1
20110154281	Zach	Jun 2011	A1
20110207298	Anderson et al.	Aug 2011	A1
20110260253	Inaba	Oct 2011	A1
20110298025	Haensch et al.	Dec 2011	A1
20110317477	Liaw	Dec 2011	A1
20120012932	Perng et al.	Jan 2012	A1
20120273841	Quandt et al.	Nov 2012	A1
20130097574	Balabanov et al.	Apr 2013	A1
20130200465	Becker et al.	Aug 2013	A1
20130200469	Becker et al.	Aug 2013	A1
20130207198	Becker et al.	Aug 2013	A1
20130207199	Becker et al.	Aug 2013	A1
20130254732	Kornachuk et al.	Sep 2013	A1
20140197543	Kornachuk et al.	Jul 2014	A1
20150249041	Becker	Sep 2015	A1
20150270218	Becker	Sep 2015	A1

Foreign Referenced Citations (74)

Number	Date	Country
0102644	Jul 1989	EP
0788166	Aug 1997	EP
1394858	Mar 2004	EP
1670062	Jun 2006	EP
1833091	Aug 2007	EP
1730777	Sep 2007	EP
2251901	Nov 2010	EP
2860920	Apr 2005	FR
58-182242	Oct 1983	JP
58-215827	Dec 1983	JP
61-182244	Aug 1986	JP
S63-310136	Dec 1988	JP
H01284115	Nov 1989	JP
03-165061	Jul 1991	JP
H05152937	Jun 1993	JP
H05211437	Aug 1993	JP
H05218362	Aug 1993	JP
H07-153927	Jun 1995	JP
2684980	Jul 1995	JP
1995-302706	Nov 1995	JP
1997-09289251	Nov 1997	JP
10-116911	May 1998	JP
1999-045948	Feb 1999	JP
2001-068558	Mar 2001	JP
2001-168707	Jun 2001	JP
2002-026125	Jan 2002	JP
2002-026296	Jan 2002	JP
2002-184870	Jun 2002	JP
2001-056463	Sep 2002	JP
2002-258463	Sep 2002	JP
2002-289703	Oct 2002	JP
2001-272228	Mar 2003	JP
2003-100872	Apr 2003	JP
2003-264231	Sep 2003	JP
2004-013920	Jan 2004	JP
2004-200300	Jul 2004	JP
2004-241529	Aug 2004	JP
2004-342757	Dec 2004	JP
2005-020008	Jan 2005	JP
2003-359375	May 2005	JP
2005-135971	May 2005	JP
2005-149265	Jun 2005	JP
2005-183793	Jul 2005	JP
2005-203447	Jul 2005	JP
2005-268610	Sep 2005	JP
2005-114752	Oct 2006	JP
2006-303022	Nov 2006	JP
2007-012855	Jan 2007	JP
2007-013060	Jan 2007	JP
2007-043049	Feb 2007	JP
2011-515841	May 2011	JP
10-0417093	Jun 1997	KR
10-1998-087485	Dec 1998	KR
1998-0084215	Dec 1998	KR
10-1999-0057943	Jul 1999	KR
2000-0005660	Jan 2000	KR
10-2000-0028830	May 2000	KR
10-2002-0034313	May 2002	KR
10-2002-0070777	Sep 2002	KR
2003-0022006	Mar 2003	KR
10-2005-0030347	Mar 2005	KR
2005-0037965	Apr 2005	KR
2006-0108233	Oct 2006	KR
386288	Apr 2000	TW
200709309	Mar 2007	TW
200709565	Mar 2007	TW
200811704	Mar 2008	TW
200947567	Nov 2009	TW
WO 2005104356	Nov 2005	WO
WO 2006014849	Feb 2006	WO
WO 2006052738	May 2006	WO
WO 2006090445	Aug 2006	WO
WO 2007014053	Feb 2007	WO
WO 2007103587	Sep 2007	WO

Non-Patent Literature Citations (204)

Entry
U.S. Appl. No. 60/625,342, filed May 25, 2006, Pileggi et al.
Acar, et al., “A Linear-Centric Simulation Framework for Parametric Fluctuations”, 2002, IEEE, Carnegie Mellon University USA, pp. 1-8, Jan. 28, 2002.
Amazawa, et al., “Fully Planarized Four-Level Interconnection with Stacked VLAS Using CMP of Selective CVD-A1 and Insulator and its Application to Quarter Micron Gate Array LSIs”, 1995, IEEE, Japan, pp. 473-476, Dec. 10, 1995.
Axelrad et al. “Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Design”, 2000, International Symposium on Quality Electronic Design (ISQED), Mar. 20, 2000.
Balasinski et al. “Impact of Subwavelength CD Tolerance on Device Performance”, 2002, SPIE vol. 4692, Jul. 11, 2002.
Burkhardt, et al., “Dark Field Double Dipole Lithography (DDL) for Back-End-Of-Line Processes”, 2007, SPIE Proceeding Series, vol. 6520; Mar. 26, 2007.
Capetti, et al., “Sub kl = 0.25 Lithography with Double Patterning Technique for 45nm Technology Node Flash Memory Devices at λ = 193nm”, 2007, SPIE Proceeding Series, vol. 6520; Mar. 27, 2007.
Capodieci, L., et al., “Toward a Methodology for Manufacturability-Driven Design Rule Exploration,” DAC 2004, Jun. 7, 2004, San Diego, CA.
Chandra, et al., “An Interconnect Channel Design Methodology for High Performance Integrated Circuits”, 2004, IEEE, Carnegie Mellon University, pp. 1-6, Feb. 16, 2004.
Cheng, et al., “Feasibility Study of Splitting Pitch Technology on 45nm Contact Patterning with 0.93 NA”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Chow, et al., “The Design of a SRAM-Based Field-Programmable Gate Array—Part II: Circuit Design and Layout”, 1999, IEEE, vol. 7 # 3 pp. 321-330, Sep. 1, 1999.
Clark et al. “Managing Standby and Active Mode Leakage Power in Deep Sub-Micron Design”, Aug. 9, 2004, ACM.
Cobb et al. “Using OPC to Optimize for Image Slope and Improve Process Window”, 2003, SPIE vol. 5130, Apr. 16, 2003.
Devgan “Leakage Issues in IC Design: Part 3”, 2003, ICCAD, Nov. 9, 2003.
DeVor, et al., “Statistical Quality Design and Control”, 1992, Macmillan Publishing Company, pp. 264-267, Jan. 3, 1992.
Dictionary.com, “channel,” in Collins English Dictionary—Complete & Unabridged 10th Edition. Source location: HarperCollins Publishers. Sep. 3, 2009.
Dusa, et al. “Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
El-Gamal, “Fast, Cheap and Under Control: The Next Implementation Fabric”, Jun. 2, 2003, ACM Press, pp. 354-355.
Firedberg, et al., “Modeling Within-Field Gate Length Spatial Variation for Process-Design Co-Optimization,” 2005 Proc. of SPIE vol. 5756, pp. 178-188, Feb. 27, 2005.
Frankel, “Quantum State Control Interference Lithography and Trim Double Patterning for 32-16nm Lithography”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 27, 2007.
Garg, et al. “Lithography Driven Layout Design”, 2005, IEEE VLSI Design 2005, Jan. 3, 2005.
Grobman et al. “Reticle Enhancement Technology Trends: Resource and Manufacturability Implications for the Implementation of Physical Designs” Apr. 1, 2001, ACM.
Grobman et al. “Reticle Enhancement Technology: Implications and Challenges for Physical Design” Jun. 18, 2001, ACM.
Gupta et al. “Enhanced Resist and Etch CD Control by Design Perturbation”, Oct. 4, 2006, Society of Photo-Optical Instrumentation Engineers.
Gupta et al. “A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology”, 2005, Sixth International Symposium on Quality Electronic Design (ISQED), Mar. 21, 2005.
Gupta et al. “Detailed Placement for Improved Depth of Focus and CD Control”, 2005, ACM, Jan. 18, 2005.
Gupta et al. “Joining the Design and Mask Flows for Better and Cheaper Masks”, Oct. 14, 2004, Society of Photo-Optical Instrumentation Engineers.
Gupta et al. “Manufacturing—Aware Physical Design”, ICCAD 2003, Nov. 9, 2003.
Gupta et al. “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control”, Jun. 7, 2004, ACM.
Gupta et al. “Wafer Topography—Aware Optical Proximity Correction for Better DOF Margin and CD Control”, Apr. 13, 2005, SPIE.
Gupta, Puneet, et al., “Manufacturing—aware Design Methodology for Assist Feature Correctness,” SPIE vol. 5756, May 13, 2005.
Ha et al., “Reduction in the Mask Error Factor by Optimizing the Diffraction Order of a Scattering Bar in Lithography,” Journal of the Korean Physical Society, vol. 46, No. 5, May 5, 2005, pp. 1213-1217.
Hakko, et al., “Extension of the 2D-TCC Technique to Optimize Mask Pattern Layouts,” 2008 Proc. of SPIE vol. 7028, 11 pages, Apr. 16, 2008.
Halpin et al., “Detailed Placement with Net Length Constraints,” Publication Year 2003, Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, pp. 22-27, Jun. 30, 2003.
Hayashida, et al., “Manufacturable Local Interconnect technology Fully Compatible with Titanium Salicide Process”, Jun. 11, 1991, VMIC Conference.
Heng, et al., “A VLSI Artwork Legalization Technique Base on a New Criterion of Minimum Layout Perturbation”, Proceedings of 1997 International Symposium on Physical Design, pp. 116-121, Apr. 14, 1997.
Heng, et al., “Toward Through-Process Layout Quality Metrics”, Mar. 3, 2005, Society of Photo-Optical Instrumentation Engineers.
Hu, et al., “Synthesis and Placement Flow for Gain-Based Programmable Regular Fabrics”, Apr. 6, 2003, ACM Press, pp. 197-203.
Hur et al., “Mongrel: Hybrid Techniques for Standard Cell Placement,” Publication Year 2000, IEEE/ACM International Conference on Computer Aided Design, ICCAD-2000, pp. 165-170, Nov. 5, 2000.
Hutton, et al., “A Methodology for FPGA to Structured—ASIC Synthesis and Verification”, 2006, EDAA, pp. 64-69, Mar. 6, 2006.
Intel Core Microarchitecture White Paper “Introducing the 45 nm Next-Generation Intel Core Microarchitecture,” Intel Corporation, 2007 (best available publication date).
Jayakumar, et al., “A Metal and VIA Maskset Programmable VLSI Design Methodology using PLAs”, 2004, IEEE, pp. 590-594, Nov. 7, 2004.
Jhaveri, T. et al., Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity, Proc. of the SPIE vol. 6156, Feb. 19, 2006.
Kang, S.M., Metal-Metal Matrix (M3) for High-Speed MOS VLSI Layout, IEEE Trans. on CAD, vol. CAD-6, No. 5, Sep. 1, 1987.
Kawashima, et al., “Mask Optimization for Arbitrary Patterns with 2D-TCC Resolution Enhancement Technique,” 2008 Proc. of SPIE vol. 6924, 12 pages, Feb. 24, 2008.
Kheterpal, et al., “Design Methodology for IC Manufacturability Based on Regular Logic-Bricks”, DAC, Jun. 13, 2005, IEEE/AMC, vol. 6520.
Kheterpal, et al., “Routing Architecture Exploration for Regular Fabrics”, DAC, Jun. 7, 2004, ACM Press, pp. 204-207.
Kim, et al., “Double Exposure Using 193nm Negative Tone Photoresist”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Kim, et al., “Issues and Challenges of Double Patterning Lithography in DRAM”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Koorapaty, et al., “Exploring Logic Block Granularity for Regular Fabrics”, 2004, IEEE, pp. 1-6, Feb. 16, 2004.
Koorapaty, et al., “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabric”, 13th International Conference on Field Programmable Logic and Applications (FPL) 2003, Lecture Notes in Computer Science (LNCS), Sep. 1, 2003, Springer-Verlag, vol. 2778, pp. 426-436.
Koorapaty, et al., “Modular, Fabric-Specific Synthesis for Programmable Architectures”, 12th International Conference on Field Programmable Logic and Applications (FPL—2002, Lecture Notes in Computer Science (LNCS)), Sep. 2, 2002, Springer-Verlag, vol. 2438 pp. 132-141.
Kuh et al., “Recent Advances in VLSI Layout,” Proceedings of the IEEE, vol. 78, Issue 2, pp. 237-263, Feb. 1, 1990.
Lavin et al. “Backend DAC Flows for “Restrictive Design Rules””, 2004, IEEE, Nov. 7, 2004.
Li, et al., “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, 2002, IEEE, pp. 1-6, Mar. 4, 2002.
Li, et al., “Nonlinear Distortion Analysis Via Linear-Centric Models”, 2003, IEEE, pp. 897-903, Jan. 21, 2003.
Liebmann et al., “Integrating DfM Components into a Cohesive Design-to-Silicon Solution,” Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, Feb. 27, 2005.
Liebmann et al., “Optimizing Style Options for Sub-Resolution Assist Features,” Proc. of SPIE vol. 4346, Feb. 25, 2001, pp. 141-152.
Liebmann, et al., “High-Performance Circuit Design for the RET-Enabled 65nm Technology Node”, Feb. 26, 2004, SPIE Proceeding Series, vol. 5379 pp. 20-29.
Liebmann, L. W., Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity?, International Symposium on Physical Design, Apr. 6, 2003.
Liu et al., “Double Patterning with Multilayer Hard Mask Shrinkage for Sub 0.25 kl Lithography,” Proc. SPIE 6520, Optical Microlithography XX, Feb. 25, 2007.
Mansfield et al., “Lithographic Comparison of Assist Feature Design Strategies,” Proc. of SPIE vol. 4000, Feb. 27, 2000, pp. 63-76.
Miller, “Manufacturing—Aware Design Helps Boost IC Yield”, Sep. 9, 2004, http://www.eetimes.com/showArticle.jhtml?articleID=47102054.
Mishra, P., et al., “FinFET Circuit Design,” Nanoelectronic Circuit Design, pp. 23-54, Dec. 21, 2010.
Mo, et al., “Checkerboard: A Regular Structure and its Synthesis, International Workshop on Logic and Synthesis”, Department of Electrical Engineering and Computer Sciences, UC Berkeley, California, pp. 1-7, Jun. 1, 2003.
Mo, et al., “PLA-Based Regular Structures and Their Synthesis”, Department of Electrical Engineering and Computer Sciences, IEEE, pp. 723-729, Jun. 1, 2003.
Mo, et al., “Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design”, Kluwer Academic Publishers, Entire Book, Jun. 1, 2002.
Moore, Samuel K., “Intel 45-nanometer Penryn Processors Arrive,” Nov. 13, 2007, IEEE Spectrum, http://spectrum.ieee.org/semiconductors/design/intel-45nanometer-penryn-processors-arrive.
Mutoh et al. “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”, 1995, IEEE, Aug. 1, 1995.
Op de Beek, et al., “Manufacturability issues with Double Patterning for 50nm half pitch damascene applications, using RELACS® shrink and corresponding OPC”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Or-Bach, “Programmable Circuit Fabrics”, Sep. 18, 2001, c-ASIC, pp. 1-36.
Otten, et al., “Planning for Performance”, DAC 1998, ACM Inc., pp. 122-127, Jun. 15, 1998.
Pack et al. “Physical & Timing Verification of Subwavelength-Scale Designs—Part I: Lithography Impact on MOSFETs”, 2003, SPIE vol. 5042, Feb. 23, 2003.
Pandini, et al., “Congestion—Aware Logic Synthesis”, 2002, IEEE, pp. 1-8, Mar. 4, 2002.
Pandini, et al., “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, ISPD Apr. 7, 2002, ACM Press, pp. 131-136.
Patel, et al., “An Architectural Exploration of Via Patterned Gate Arrays, ISPD 2003”, Apr. 6, 2003, pp. 184-189.
Pham, D., et al., “FINFET Device Junction Formation Challenges,” 2006 International Workshop on Junction Technology, pp. 73-77, Aug. 1, 2006.
Pileggi, et al., “Exploring Regular Fabrics to Optimize the Performance—Cost Trade-Offs, Proceedings of the 40th ACM/IEEE Design Automation Conference (DAC) 2003”, Jun. 2, 2003, ACM Press, pp. 782-787.
Poonawala, et al., “ILT for Double Exposure Lithography with Conventional and Novel Materials”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Qian et al. “Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis” 2003 IEEE, Mar. 24, 2003.
Ran, et al., “An Integrated Design Flow for a Via-Configurable Gate Array”, 2004, IEEE, pp. 582-589, Nov. 7, 2004.
Ran, et al., “Designing a Via-Configurable Regular Fabric”, Custom Integrated Circuits Conference (CICC). Proceedings of the IEEE, Oct. 1, 2004, pp. 423-426.
Ran, et al., “On Designing Via-Configurable Cell Blocks for Regular Fabrics” Proceedings of the Design Automation Conference (DAC) 2004, Jun. 7, 2004, ACM Press, s 198-203.
Ran, et al., “The Magic of a Via-Configurable Regular Fabric”, Proceedings of the IEEE International Conference on Computer Design (ICCD) Oct. 11, 2004.
Ran, et al., “Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics”, 2005, IEEE, pp. 25-32, Sep. 1, 2006.
Reis, et al., “Physical Design Methodologies for Performance Predictability and Manufacturability”, Apr. 14, 2004, ACM Press, pp. 390-397.
Robertson, et al., “The Modeling of Double Patterning Lithographic Processes”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Rosenbluth, et al., “Optimum Mask and Source Patterns to Print a Given Shape,” 2001 Proc. of SPIE vol. 4346, pp. 486-502, Feb. 25, 2001.
Rovner, “Design for Manufacturability in Via Programmable Gate Arrays”, May 1, 2003, Graduate School of Carnegie Mellon University.
Sengupta, “An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators”, 1998, Thesis for Rice University, pp. 1-101, Nov. 1, 1998.
Sengupta, et al., “An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators”, 1996, SPIE Proceeding Series, vol. 2726; pp. 244-252, Mar. 10, 1996.
Sherlekar, “Design Considerations for Regular Fabrics”, Apr. 18, 2004, ACM Press, pp. 97-102.
Shi et al., “Understanding the Forbidden Pitch and Assist Feature Placement,” Proc. of SPIE vol. 4562, pp. 968-979, Mar. 11, 2002.
Smayling et al., “APF Pitch Halving for 22 nm Logic Cells Using Gridded Design Rules,” Proceedings of SPIE, USA, vol. 6925, Jan. 1, 2008, pp. 69251E-1-69251E-7.
Socha, et al., “Simultaneous Source Mask Optimization (SMO),” 2005 Proc. of SPIE vol. 5853, pp. 180-193, Apr. 13, 2005.
Sreedhar et al. “Statistical Yield Modeling for Sub-Wavelength Lithography”, 2008 IEEE, Oct. 28, 2008.
Stapper, “Modeling of Defects in Integrated Circuit Photolithographic Patterns”, Jul. 1, 1984, IBM, vol. 28 # 4, pp. 461-475.
Taylor, et al., “Enabling Energy Efficiency in Via-Patterned Gate Array Devices”, Jun. 7, 2004, ACM Press, pp. 874-877.
Tian et al. “Model-Based Dummy Feature Placement for Oxide Chemical—Mechanical Polishing Manufacturability” IEEE, vol. 20, Issue 7, Jul. 1, 2001.
Tong, et al., “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA), Custom Integrated Circuits Conference”, Sep. 21, 2003, Proceedings of the IEEE, pp. 53-56.
Vanleenhove, et al., “A Litho-Only Approach to Double Patterning”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Wang, et al., “Performance Optimization for Gridded-Layout Standard Cells”, vol. 5567 SPIE, Sep. 13, 2004.
Wang, J. et al., Standard Cell Layout with Regular Contact Placement, IEEE Trans. on Semicon. Mfg., vol. 17, No. 3, Aug. 9, 2004.
Webb, Clair, “45nm Design for Manufacturing,” Intel Technology Journal, vol. 12, Issue 02, Jun. 17, 2008, ISSN 1535-864X, pp. 121-130.
Webb, Clair, “Layout Rule Trends and Affect upon CPU Design”, vol. 6156 SPIE, Feb. 19, 2006.
Wenren, et al., “The Improvement of Photolithographic Fidelity of Two-dimensional Structures Though Double Exposure Method”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Wilcox, et al., “Design for Manufacturability: A Key to Semiconductor Manufacturing Excellence”, 1998 IEEE, pp. 308-313, Sep. 23, 1998.
Wong, et al., “Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation,” J. Micro/Nanolith. MEMS MOEMS, Sep. 27, 2007, vol. 6(3), 2 pages.
Wu, et al., “A Study of Process Window Capabilities for Two-dimensional Structures under Double Exposure Condition”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Xiong, et al., “The Constrained Via Minimization Problem for PCB and VLSI Design”, 1988 ACM Press/IEEE, pp. 573-578, Jun. 12, 1998.
Yamamaoto, et al., “New Double Exposure Technique without Alternating Phase Shift Mask”, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Yamazoe, et al., “Resolution Enhancement by Aerial Image Approximation with 2D-TCC,” 2007 Proc. of SPIE vol. 6730, 12 pages, Sep. 17, 2007.
Yang, et al., “Interconnection Driven VLSI Module Placement Based on Quadratic Programming and Considering Congestion Using LFF Principles”, 2004 IEEE, pp. 1243-1247, Jun. 27, 2004.
Yao, et al., “Multilevel Routing With Redundant Via Insertion”, Oct. 23, 2006, IEEE, pp. 1148-1152.
Yu, et al., “True Process Variation Aware Optical Proximity Correction with Variational Lithography Modeling and Model Calibration,” J. Micro/Nanolith. MEMS MOEMS, Sep. 11, 2007, vol. 6(3), 16 pages.
Zheng, et al.“Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, DAC, Jun. 10, 2002, ACM Press, pp. 395-398.
Zhu, et al., “A Stochastic Integral Equation Method for Modeling the Rough Surface Effect on Interconnect Capacitance”, 2004 IEEE, Nov. 7, 2004.
Zhu, et al., “A Study of Double Exposure Process Design with Balanced Performance Parameters for Line/Space Applications”, 2007, SPIE Proceeding Series, vol. 6520; Feb. 25, 2007.
Zuchowski, et al., “A Hybrid ASIC and FPGA Architecture”, 2003 IEEE, pp. 187-194, Nov. 10, 2002.
Alam, Syed M. et al., “A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits,” Mar. 21, 2002.
Alam, Syed M. et al., “Layout-Specific Circuit Evaluation in 3-D Integrated Circuits,” May 1, 2003.
Aubusson, Russel, “Wafer-Scale Integration of Semiconductor Memory,” Apr. 1, 1979.
Bachtold, “Logic Circuits with Carbon,” Nov. 9, 2001.
Baker, R. Jacob, “CMOS: Circuit Design, Layout, and Simulation (2nd Edition),” Nov. 1, 2004.
Baldi et al., “A Scalable Single Poly EEPROM Cell for Embedded Memory Applications,” pp. 1-4, Fig. 1, Sep. 1, 1997.
Cao, Ke, “Design for Manufacturing (DFM) in Submicron VLSI Design,” Aug. 1, 2007.
Capodieci, Luigi, “From Optical Proximity Correction to Lithography-Driven Physical Design (1996-2006): 10 years of Resolution Enhancement Technology and the roadmap enablers for the next decade,” Proc. SPIE 6154, Optical Microlithography XIX, 615401, Mar. 20, 2006.
Chang, Leland et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond,” Jun. 16, 2005.
Cheung, Peter, “Layout Design,” Apr. 4, 2004.
Chinnery, David, “Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design,” Jun. 30, 2002.
Chou, Dyiann et al., “Line End Optimization through Optical Proximity Correction (OPC): A Case Study,” Feb. 19, 2006.
Clein, Dan, “CMOS IC Layout: Concepts, Methodologies, and Tools,” Dec. 22, 1999.
Cowell, “Exploiting Non-Uniform Access Time,” Jul. 1, 2003.
Das, Shamik, “Design Automation and Analysis of Three-Dimensional Integrated Circuits,” May 1, 2004.
Dehaene, W. et al., “Technology—Aware Design of SRAM Memory Circuits,” Mar. 1, 2007.
Deng, Liang et al., “Coupling—aware Dummy Metal Insertion for Lithography,” p. 1, col. 2, Jan. 23, 2007.
Devoivre et al., “Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC),” Jul. 12, 2002.
Enbody, R. J., “Near-Optimal n-Layer Channel Routing,” Jun. 29, 1986.
Ferretti, Marcos et al., “High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells,” Apr. 23, 2004.
Garg, Manish et al., “Litho-driven Layouts for Reducing Performance Variability,” p. 2, Figs. 2b-2c, May 23, 2005.
Greenway, Robert et al., “32nm 1-D Regular Pitch SRAM Bitcell Design for Interference-Assisted Lithography,” Oct. 6, 2008.
Gupta et al., “Modeling Edge Placement Error Distribution in Standard Cell Library,” Feb. 23, 2006.
Grad, Johannes et al., “A standard cell library for student projects,” Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education, Jun. 2, 2003.
Hartono, Roy et al., “Active Device Generation for Automatic Analog Layout Retargeting Tool,” May 13, 2004.
Hartono, Roy et al., “IPRAIL—Intellectual Property Reuse-based Analog IC Layout Automation,” Mar. 17, 2003.
Hastings, Alan, “The Art of Analog Layout (2nd Edition),” Jul. 4, 2005.
Hurata et al., “A Genuine Design Manufacturability Check for Designers,” Feb. 19, 2006.
Institute of Microelectronic Systems, “Digital Subsystem Design,” Oct. 13, 2006.
Ishida, M. et al., “A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable beyond 0.18 pm Generation and Desirable for Ultra High Speed Operation,” IEDM 1998, Dec. 6, 1998.
Jakusovszky, “Linear IC Parasitic Element Simulation Methodology,” Oct. 1, 1993.
Jangkrajarng, Nuttorn et al., “Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts,” Nov. 5, 2006.
Kahng, Andrew B., “Design Optimizations DAC-2006 DFM Tutorial, part V),” Jul. 24, 2006.
Kang, Sung-Mo et al., “CMOS Digital Integrated Circuits Analysis & Design,” Oct. 29, 2002.
Kottoor, Mathew Francis, “Development of a Standard Cell Library based on Deep Sub-Micron SCMOS Design Rules using Open Source Software (MS Thesis),” Aug. 1, 2005.
Kubicki, “Intel 65nm and Beyond (or Below): IDF Day 2 Coverage (available at http://www.anandtech.com/show/1468/4),” Sep. 9, 2004.
Kuhn, Kelin J., “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS,” p. 27, Dec. 12, 2007.
Kurokawa, Atsushi et al., “Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills, Proc. of ISQED,” pp. 586-591, Mar. 21, 2005.
Lavin, Mark, “Open Access Requirements from RDR Design Flows,” Nov. 11, 2004.
Liebmann, Lars et al., “Layout Methodology Impact of Resolution Enhancement Techniques,” pp. 5-6, Apr. 6, 2003.
Liebmann, Lars et al., “TCAD development for lithography resolution enhancement,” Sep. 1, 2001.
Lin, Chung-Wei et al., “Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability,” Jan. 26, 2007.
McCullen, Kevin W., “Layout Techniques for Phase Correct and Gridded Wiring,” pp. 13, 17, Fig. 5, Dec. 1, 2006.
MOSIS, “Design Rules MOSIS Scalable CMOS (SCMOS) (Revision 8.00),” Oct. 4, 2004.
MOSIS, “MOSIS Scalable CMOS (SCMOS) Design Rules (Revision 7.2),” Jan. 1, 1995.
Muta et al., “Manufacturability—Aware Design of Standard Cells,” pp. 2686-2690, Figs. 3, 12, Dec. 1, 2007.
Na, Kee-Yeol et al., “A Novel Single Polysilicon EEPROM Cell With a Polyfinger Capacitor,” Nov. 30, 2007.
Pan et al., “Redundant Via Enhanced Maze Routing for Yield Improvement,” DAC 2005, Jan. 18, 2005.
Park, Tae Hong, “Characterization and Modeling of Pattern Dependencies in Copper Interconnects for Integrated Circuits,” Ph.D. Thesis, MIT, May 24, 2002.
Patel, Chetan, “An Architectural Exploration of Via Patterned Gate Arrays (CMU Master's Project),” May 1, 2003.
Pease, R. Fabian et al., “Lithography and Other Patterning Techniques for Future Electronics,” IEEE 2008, vol. 96, Issue 2, Jan. 16, 2008.
Serrano, Diego Emilio, Pontificia Universidad Javeriana Facultad De Ingenieria, Departamento De Electronica, “Diseño De Multiplicador 4 X 8 en VLSI, Introduccion al VLSI,” 2006 (best available publication date).
Pramanik, “Impact of layout on variability of devices for sub 90nm technologies,” 2004 (best available publication date).
Pramanik, Dipankar et al., “Lithography-driven layout of logic cells for 65-nm node (SPIE Proceedings vol. 5042),” Jul. 10, 2003.
Roy et al., “Extending Aggressive Low-K1 Design Rule Requirements for 90 and 65 Nm Nodes Via Simultaneous Optimization of Numerical Aperture, Illumination and Optical Proximity Correction,” J.Micro/Nanolith, MEMS MOEMS, 4(2), 023003, Apr. 26, 2005.
Saint, Christopher et al., “IC Layout Basics: A Practical Guide,” Chapter 3, Nov. 5, 2001.
Saint, Christopher et al., “IC Mask Design: Essential Layout Techniques,” May 24, 2002.
Scheffer, “Physical CAD Changes to Incorporate Design for Lithography and Manufacturability,” Feb. 4, 2004.
Smayling, Michael C., “Part 3: Test Structures, Test Chips, In-Line Metrology & Inspection,” Jul. 24, 2006.
Spence, Chris, “Full-Chip Lithography Simulation and Design Analysis: How OPC is changing IC Design, Emerging Lithographic Technologies IX,” May 6, 2005.
Subramaniam, Anupama R., “Design Rule Optimization of Regular layout for Leakage Reduction in Nanoscale Design,” pp. 474-478, Mar. 24, 2008.
Tang, C. W. et al., “A compact large signal model of LDMOS,” Solid-State Electronics 46(2002) 2111-2115, May 17, 2002.
Taylor, Brian et al., “Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks,” Jun. 8, 2007.
Tian, Ruiqi et al., “Dummy Feature Placement for Chemical—Mechanical Uniformity in a Shallow Trench Isolation Process,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 1, pp. 63-71, Jan. 1, 2002.
Tian, Ruiqi et al., “Proximity Dummy Feature Placement and Selective Via Sizing for Process Uniformity in a Trench-First-Via-Last Dual-Inlaid Metal Process,” Proc. of IITC, pp. 48-50, Jun. 6, 2001.
Torres, J. A. et al., “RET Compliant Cell Generation for sub-130nm Processes,” SPIE vol. 4692, Mar. 6, 2002.
Uyemura, John P., “Introduction to VLSI Circuits and Systems,” Chapters 2, 3, 5, and Part 3, Jul. 30, 2001.
Uyemura, John, “Chip Design for Submicron VLSI: CMOS Layout and Simulation,” Chapters 2-5, 7-9, Feb. 8, 2005.
Verhaegen et al., “Litho Enhancements for 45nm-nod MuGFETs,” Aug. 1, 2005.
Wong, Ban P., “Bridging the Gap between Dreams and Nano-Scale Reality (DAC-2006 DFM Tutorial),” Jul. 28, 2006.
Wang, Dunwei et al., “Complementary Symmetry Silicon Nanowire Logic: Power-Efficient Inverters with Gain,” Aug. 17, 2006.
Wang, Jun et al., “Effects of grid-placed contacts on circuit performance,” pp. 135-139, Figs. 2, 4-8, Feb. 28, 2003.
Wang, Jun et al., “Standard cell design with regularly placed contacts and gates (SPIE vol. 5379),” Feb. 22, 2004.
Wang, Jun et al., “Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates,” J. Micro/Nanolith, MEMS MOEMS, 4(1), 013001, Mar. 16, 2005.
Watson, Bruce, “Challenges and Automata Applications in Chip-Design Software,” pp. 38-40, Jul. 16, 2007.
Weste, Neil et al., “CMOS VLSI Design: A Circuits and Systems Perspective, 3rd Edition,” May 21, 2004.
Wingerden, Johannes van, “Experimental verification of improved printability for litho-driven designs,” Mar. 14, 2005.
Wong, Alfred K., “Microlithography: Trends, Challenges, Solutions,, and Their Impact on Design,” Micro IEEE vol. 23, Issue 2, Apr. 29, 2003.
Xu, Gang, “Redundant-Via Enhanced Maze Routing for Yield Improvement,” Proceedings of ASP-DAC 2005, Jan. 18, 2005.
Yang, Jie, “Manufacturability Aware Design,” pp. 93, 102, Fig. 5.2, Jan. 16, 2008.
Yongshun, Wang et al., “Static Induction Devices with Planar Type Buried Gate,” Chinese Journal of Semiconductors, vol. 25, No. 2, Feb. 1, 2004.
Zobrist, George (editor), “Progress in Computer Aided VLSI Design: Implementations (Ch. 5),” Ablex Publishing Corporation, Feb. 1, 1990.
Petley, Graham, “VLSI and ASIC Technology Standard Cell Library Design,” from website www.vlsitechnology.org, Jan. 11, 2005.
Liebmann, Lars, et al., “Layout Optimization at the Pinnacle of Optical Lithography,” Design and Process Integration for Microelectronic Manufacturing II, Proceedings of SPIE vol. 5042, Jul. 8, 2003.
Kawasaki, H., et al., “Challenges and Solutions of FinFET Integration in an SRAM Cell and a Logic Circuit for 22 nm node and beyond,” Electron Devices Meeting (IEDM), 2009 IEEE International, IEEE, Piscataway, NJ, USA, Dec. 7, 2009, pp. 1-4.

Related Publications (1)

	Number	Date	Country
	20160079381 A1	Mar 2016	US

Provisional Applications (1)

	Number	Date	Country
	60781288	Mar 2006	US

Continuations (4)

	Number	Date	Country
Parent	13774919	Feb 2013	US
Child	14946292		US
Parent	12572225	Oct 2009	US
Child	13774919		US
Parent	12212562	Sep 2008	US
Child	12572225		US
Parent	11683402	Mar 2007	US
Child	12212562		US

Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same

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