SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Abstract

The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are sectional views showing a configuration of a semiconductor device according to a first embodiment;

FIGS. 2A and 2B are sectional views showing a manufacturing process of the semiconductor device according to the first embodiment;

FIGS. 3A and 3B are sectional views showing a manufacturing process of a conventional semiconductor device.

FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a second embodiment;

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device according the second embodiment;

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 7 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 8 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 9 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 10 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 11 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

FIGS. 13A and 13B are sectional views showing a manufacturing process of a semiconductor device according a third embodiment;

FIGS. 14A and 14B are sectional views showing a manufacturing process of the semiconductor device according the third embodiment;

FIG. 15 is a sectional view showing a configuration of the semiconductor device according a fourth embodiment;

FIG. 16 is a sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment;

FIG. 17 is a sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment;

FIG. 18 is a sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment;

Claims

1. A semiconductor device, comprising at least one MISFET which has: a full-silicide gate electrode, formed on a semiconductor substrate via a gate insulating film, and fully silicided; andside walls, each formed on the side surfaces of said gate insulating film and said full-silicide gate electrode,wherein the top end of said full-silicide gate electrode is lower than the top end of said side wall.

2. The semiconductor device according to claim 1, wherein said at least one MISFET has a P-type MISFET and an N-type MISFET, andthe top end of said full-silicide gate electrode in said P-type MISFET is lower than the top end of said full-silicide gate electrode in said N-type MISFET.

3. The semiconductor device according to claim 1, wherein said at least one MISFET has a plurality of MISFETs with different gate lengths.

4. The semiconductor device according to claim 3, wherein said plurality of MISFETs are identical conductive-types.

5. A semiconductor device, comprising at least one MISFET which has: a full-silicide gate electrode, formed on a semiconductor substrate via a gate insulating film, and fully silicided; andside walls, each formed on the side surface of said full-silicide gate electrode,wherein said at least one MISFET has:a first MISFET in which the top end of said full-silicide gate electrode is formed so as to be lower than the top end of said side wall; anda second MISFET in which the top end of said full-silicide gate electrode is formed so as to be higher the top end of said side wall.

6. The semiconductor device according to claim 5, wherein said first MISFET includes an N-type MISFET, and said second MISFET includes a P-type MISFET.

7. A method for manufacturing a semiconductor device, which comprises the steps of: (a) preparing a semiconductor substrate which comprises on its main surface a structure having a polysilicon gate electrode formed via a gate insulating film, and side walls each formed on the side surfaces of said gate insulating film and the polysilicon gate electrode;(b) adjusting the height of the top end of said polysilicon gate electrode by etching;(c) forming a metal film so as to cover said polysilicon gate electrode subsequently to said process (b); and(d) making a silicide reaction between said metal film and said polysilicon gate electrode by thermal treatment to fully silicide said polysilicon gate electrode for formation of a full-silicide gate electrode, and which forms at least one MISFET having said side walls each formed on side surfaces of said gate insulating film and said full-silicide gate electrode,wherein said step (b) includes a step of adjusting the top end of said full-silicide gate electrode so as to be lower than the top end of said side wall.

8. The method for manufacturing a semiconductor device according to claim 7, wherein said at least one MISFET has a P-type MISFET and an N-type MISFET, andsaid step (b) includes a step of adjusting the top end of said polysilicon gate electrode in said P-type MISFET so as to be lower than the top end of said polysilicon gate electrode in said N-type MISFET.

9. The method for manufacturing a semiconductor device according to claim 7, wherein said step (a) includes a step of preparing the semiconductor substrate comprising a plurality of structures with different gate lengths.

10. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of etching said side walls such that the top end of said polysilicon gate electrode is higher than the top end of said side wall, prior to said step (c).