The present application claims priority from Japanese patent application No. 2005-258091 filed on Sep. 6, 2005, the content of which is hereby incorporated by reference into this application.
The present invention relates to a semiconductor device and a manufacturing technology thereof, in particular, to a technology effective when applied to a semiconductor device using wafer process package (WPP) and a manufacturing technology thereof.
Examples of the conventionally known technologies include a technology of forming a via made of an aluminum film over a lower-level copper interconnect and then forming an upper-level copper interconnect through the via (refer to, for example, Japanese Unexamined Patent Publication No. Hei 11(1999)-121615); a technology of forming an upper-level interconnect made of a film stack of a chromium film and a copper film over an aluminum interconnect through a polyimide film (refer to, for example, Japanese Unexamined Patent Publication No. 2003-234348); a technology of forming an upper-level interconnect made of a film stack of a chromium film and a copper film over an aluminum pad through a polyimide film and then coating the upper-level interconnect with nickel (refer to, for example, Japanese Unexamined Patent Publication No. 2003-234429); a technology of forming a via for connecting a lower-level copper interconnect to an upper-level copper interconnect by using a material (such as Ti, Zr, Ta, Sn or Mg) which can be dispersed easily in copper (refer to, for example, Japanese Unexamined Patent Publication No. Hei 11(1999)-204644), and a technology of connecting an upper-level copper interconnect to a lower-level interconnect by a via made of a copper film (refer to, for example, Japanese Unexamined Patent Publication No. 2004-165234).
A technology of integrating a package process (latter step) and a wafer process (former step) and finishing packaging while in the wafer stage, which is a so-called wafer process package (WPP), is a technology of applying a wafer process even to the packaging. This WPP technology is advantageous because it needs far fewer steps than the conventional method in which package process is performed for each of semiconductor chips cut out from a semiconductor wafer.
When WPP is adopted, a semiconductor device is manufactured by the following steps. First, semiconductor elements such as MISFET (Metal Insulator Semiconductor Field Effect Transistor) are formed over the main surface of a semiconductor wafer, followed by the formation of a plurality of interconnect layers over the semiconductor elements. These interconnect layers are, for example, made of a copper film and can be formed by forming a trench in an interlayer insulating film and then filling a conductor film in the trench. Over the uppermost-level interconnect formed at the uppermost layer of the interconnect layers, a film stack made of a silicon nitride film and a silicon oxide film is formed, whereby the silicon nitride film and the silicon oxide film are formed over the uppermost-level interconnect made of a copper film and the interlayer insulating film having the uppermost-level interconnect buried in the trench.
After formation of a polyimide resin film over the silicon oxide film, the silicon nitride film, silicon oxide film and polyimide resin film are patterned to form an opening portion having a bottom surface from which the uppermost-level interconnect is exposed.
A thin electrode layer (seed layer) is formed over the polyimide resin film including the inside of the opening portion and a redistribution interconnect is formed over the electrode layer by using the plating process. The redistribution interconnect is made of, for example, a film stack of a copper film and a nickel film. After formation of a polyimide resin film over the redistribution interconnect, patterning is conducted to expose an end portion of the redistribution interconnect. A bump electrode is then formed over the exposed one end portion of the redistribution interconnect. In such a manner, the redistribution interconnect and the bump electrode connected thereto are formed while the semiconductor wafer is intact.
In high-speed SRAM (Static Random Access Memory) or CMOS (Complementary Metal Oxide Semiconductor) logic products, for example, the above-described WPP is employed for the purpose of a reduction in package cost and speed up and they have a package structure so as to permit flip chip connection to a mounting substrate via a bump electrode made of a solder. The WPP used in such semiconductor devices employs a structure as illustrated in
Similar to ordinary products, a semiconductor device having such a structure is subjected to a reliability test (selection test) in which it is operated repeatedly under temperature cycling between −50° C. to 125° C. Repeated applications of a thermal load to the semiconductor device cause expansion and contraction of films constituting the semiconductor device. In particular, a contraction stress occurs in the nickel film 9 and polyimide resin film 5, which are portions of the redistribution interconnect 7, owing to the influence of the temperature cycling in the reliability test. As illustrated in
The reliability test is followed by an electrical characteristics test. In this test, a voltage is applied to the uppermost-level interconnect 1. When a voltage is applied, copper constituting the uppermost-level interconnect 1 starts drifting in the peeled portion which has appeared at the interface of the interlayer insulating film 2 and the silicon nitride film 3 and causes conduction between two adjacent uppermost-level interconnects 1. This leads to occurrence of a short-circuit fault. Such a phenomenon is not a problem in aluminum interconnection, while it becomes a problem in copper (Cu) interconnection because copper moves very easily by an electric field.
An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit fault between uppermost-level interconnects.
The above-described and the other objects and novel features of the present invention will be apparent by the description herein and accompanying drawings.
Outline of typical inventions, of the inventions disclosed by the present application, will next be described briefly.
In one aspect of the present invention, there is thus provided a semiconductor device comprising (a) a semiconductor substrate, (b) an interlayer insulating film formed over the semiconductor substrate, (c) an uppermost-level interconnect formed so as to bury it in the interlayer insulating film, (d) a buffer layer formed over the uppermost-level interconnect, (e) a redistribution interconnect formed over the buffer layer, and (f) a bump electrode formed over one end portion of the redistribution interconnect.
In another aspect of the present invention, there is also provided a manufacturing method of a semiconductor device, which comprises the steps of: (a) forming an interlayer insulating film over a semiconductor substrate, (b) forming an uppermost-level interconnect so as to bury it in the interlayer insulating film, (c) forming a first insulating film over the interlayer insulating film having the uppermost-level interconnect buried therein, (d) forming a first opening portion in the first insulating film to expose the uppermost-level interconnect from the first opening portion, (e) forming a first conductor film over the first insulating film including the inside of the first opening portion, (f) patterning the first conductor film to form a buffer layer, (g) forming a second insulating film over the buffer layer, (h) forming a second opening portion in the second insulating film to expose the buffer layer from the second opening portion, (i) forming a second conductor film over the second insulating film including the inside of the second opening portion, and (j) patterning the second conductor film to form a redistribution interconnect.
Advantages available by the typical inventions, among the inventions disclosed by the present application, will next be described briefly.
The present invention makes it possible to improve the reliability of a semiconductor device using WPP by reducing short-circuit faults between uppermost-level interconnects caused by heating cycle.
In the below-described embodiments, a description will be made after divided in plural sections or in plural embodiments if necessary for convenience's sake. These plural sections or embodiments are not independent each other, but in a relation such that one is a modification example, details or complementary description of a part or whole of the other one unless otherwise specifically indicated.
In the below-described embodiments, when a reference is made to the number of elements (including the number, value, amount and range), the number of elements is not limited to a specific number but can be greater than or less than the specific number unless otherwise specifically indicated or in the case it is principally apparent that the number is limited to the specific number.
Moreover in the below-described embodiments, it is needless to say that the constituting elements (including element steps) are not always essential unless otherwise specifically indicated or in the case where it is principally apparent that they are essential.
Similarly, in the below-described embodiments, when a reference is made to the shape or positional relationship of the constituting elements, that substantially analogous or similar to it is also embraced unless otherwise specifically indicated or in the case where it is utterly different in principle. This also applies to the above-described value and range.
Embodiments of the present invention will hereinafter be described specifically based on accompanying drawings. In all the drawings for describing the below-described embodiments, elements having like function will be identified by like reference numerals and overlapping descriptions will be omitted.
The n channel MISFET Q1 is formed over the p well 22. This n channel MISFET Q1 has the following structure. Described specifically, a gate insulating film 24 is formed over the p well 22. Over the gate insulating film 24, a gate electrode 25a is formed. The gate insulating film 24 is made of, for example, a silicon oxide film but may be made of a film having a higher dielectric constant than that of the silicon oxide film. The gate electrode 25a is made of, for example, a polysilicon film. For example, an n type impurity has been introduced into this polysilicon film in order to reduce the threshold voltage of the n channel MISFET Q1.
Sidewalls 26 are formed over the side walls on both sides of the gate electrode 25a. In the p well 22 below these sidewalls 26, a low-concentration n type impurity diffusion region 27a is formed. Outside this low-concentration n-type impurity diffusion region 27a, a high-concentration n-type impurity diffusion region 28a is formed. The low-concentration n-type impurity diffusion region 27a and high-concentration n-type impurity diffusion region 28a are semiconductor regions having an n type impurity introduced therein. An n type impurity has been introduced at a higher concentration into the high-concentration n-type impurity diffusion region 28a than into the low-concentration n-type impurity diffusion region 27a. By these low-concentration n-type impurity diffusion region 27a and high-concentration n-type impurity diffusion region 28a, a source region or a drain region of the n channel MISFET Q1 is formed. A so-called LDD (Lightly Doped Drain) structure is formed by constituting the source region or drain region from the low-concentration n-type impurity diffusion region 27a and high-concentration n-type impurity diffusion region 28a. This enables to relax the electric field concentration below the gate electrode 25a.
Over the n well 23, the p channel MISFET Q2 is formed. This p channel MISFET Q2 has almost a similar constitution to that of the n channel MISFET Q1. Described specifically, a gate insulating film 24 is formed over an n well 23 and a gate electrode 25b is formed over this gate insulating film 24. The gate electrode 25b is made of, for example, a polysilicon film and has a p type impurity introduced therein. The threshold voltage of the p channel MISFET Q2 can be reduced by introducing the p type impurity into the gate electrode 25b. In this Embodiment 1, an n type impurity is introduced into the gate electrode 25a of the n channel MISFET Q1, while a p type impurity is introduced into the gate electrode 25b of the p channel MISFET Q2. This enables reduction in the threshold voltage in both the n channel MISFET Q1 and p channel MISFET Q2.
Sidewalls 26 are formed over the side walls on both sides of the gate electrode 25b. In the n well 23 below the sidewalls 26, a low-concentration p type impurity diffusion region 27b is formed. Outside this low-concentration p-type impurity diffusion region 27b, a high-concentration p-type impurity diffusion region 28b is formed. The low-concentration p-type impurity diffusion region 27b and high-concentration p-type impurity diffusion region 28b are semiconductor regions having a p type impurity introduced therein. A p type impurity has been introduced at a higher concentration into the high-concentration p-type impurity diffusion region 28b than into the low-concentration p-type impurity diffusion region 27b. By these low-concentration p-type impurity diffusion region 27b and high-concentration p-type impurity diffusion region 28b, a source region or drain region of the p channel MISFET Q2 is formed.
In the semiconductor device according to Embodiment 1, the n channel MISFET Q1 and p channel MISFET Q2 having the above-described respective structures are formed over the semiconductor substrate 20.
A multilevel interconnect structure of the semiconductor device according to Embodiment 1 will next be described. As illustrated in
Over the silicon oxide film 33 having the plug 34 formed therein, a silicon oxide film 35 which will be an interlayer insulating film is formed and a first copper interconnect 36 is formed so as to bury it in the silicon oxide film 35. This first copper interconnect 36 is made of a film stack of a barrier metal film for preventing the diffusion of copper and a copper film. Over the first copper interconnect 36, a silicon nitride film 37a is formed to prevent diffusion of copper. Over this silicon nitride film 37a, a silicon oxide film 37b is formed. Over the silicon oxide film 37b, a silicon nitride film 38a and a silicon oxide film 38b are stacked one after another. A second copper interconnect 39 is formed so as to bury it in the silicon nitride film 38a and silicon oxide film 38b. This second copper interconnect 39 is electrically connected to the first copper interconnect 36 formed therebelow. A third copper interconnect 40 and plug 41 are formed over the second copper interconnect 39 in a similar manner. The third copper interconnect 40 and plug 41 are also made of a film stack of a barrier metal film and a copper film. Over the interlayer insulating film having the plug 41 formed therein, an interlayer insulating film made of a silicon nitride film 42a and a silicon oxide film 42b is formed. Uppermost-level interconnects (pads) 43a and 43b are formed so as to bury them in the interlayer insulating film. Similar to the other copper interconnects, the uppermost-level interconnects 43a and 43b are made of a film stack of a barrier metal film and a copper film.
In Embodiment 1, as described above, the multilevel interconnect is formed of the tungsten interconnect 32 and four copper interconnect layers. These copper interconnects can be formed using, for example, the damascene process. The multilevel interconnect has a role of electrically connecting a plurality of semiconductor elements, thereby forming a circuit. The higher-level interconnects have a greater thickness.
The structure over the multilevel interconnect of the semiconductor device according to Embodiment 1 will next be described referring to
Over the silicon oxide film 45 including the upper surface of the buffer layer 47, a polyimide resin film (second insulating film) 48 is formed. This polyimide resin film 48 has an opening portion (second opening portion) 49 formed therein. From the bottom of this opening portion 49, the buffer layer 47 is exposed. A redistribution interconnect 50 is formed so as to bury it in this opening portion 49. In other words, the redistribution interconnect 50 is disposed so as to connect to the buffer layer 47 exposed from the opening portion 49 formed in the polyimide resin film 48. The redistribution interconnect 50 is disposed to complete the packaging while the semiconductor wafer is intact and it has a function of connecting the uppermost-level interconnect 43 to a bump electrode 56 which will be described later. In short, the redistribution interconnect 50 plays a role of a lead interconnect for connecting the uppermost-level interconnect 43a to the bump electrode 56, in other words, it has a function as an interposer for converting the space of the uppermost-level interconnect 43a to the space of the bump electrode 56.
The redistribution interconnect 50 is made of, for example, a film stack of a copper film 51 and a nickel film 52. Over this redistribution interconnect 50, a polyimide resin film (third insulating film) 53 is formed. The polyimide resin film 53 has an opening portion (third opening portion) 54 formed therein. The redistribution interconnect 50 is exposed from the bottom of the opening portion 54 and a gold film 55 is formed over this exposed redistribution interconnect 50. A bump electrode 56 made of, for example, a solder is formed over the gold film 55.
The semiconductor device of Embodiment 1 has the above-described structure. One of the characteristics of the present invention will next be described. The one of the characteristics of the present invention resides in that the buffer layer 47 is disposed over the uppermost-level interconnect 43a of the multilevel interconnect and the redistribution interconnect 50 is formed over the buffer layer 47, in short, a three-layer structure of the multilevel interconnect, buffer layer 47 and redistribution interconnect 50 is adopted.
Without the buffer layer 47, the phenomenon as described below occurs. When a semiconductor device is completed, a reliability test is conducted by checking its operation while exposing it to a drastic temperature change. At this reliability test, a stress appears as a result of expansion and contraction of films. As illustrated in
In Embodiment 1, on the other hand, stress concentration on a triple point X as illustrated in
Particularly when the uppermost-level interconnects 43a and 43b are made of a copper film, copper, which is more diffusible than aluminum, moves easily via a peeled portion if the peeled portion appears at the interface Y between the silicon oxide film 42b having the uppermost-level interconnects 43a and 43b buried therein and the silicon nitride film 44. Short-circuit faults due to copper drifting between the uppermost-level interconnects 43a and 43b then tend to occur. The present invention in which the buffer layer 47 is disposed to prevent the peeling at the interface Y is significantly effective when the uppermost-level interconnects 43a and 43b are made of a copper film. The present invention is however not limited to the uppermost-level interconnects 43a and 43b made of a copper film, but is also effective for the uppermost-level interconnects 43a and 43b made of an aluminum film or a tungsten film because the disposal of the buffer layer 47 can relax the stress which will otherwise cause peeling at the interface Y.
In Embodiment 1, the multilevel interconnect, buffer layer 47 and redistribution interconnect 50 are indicated separately because of the following reason. The multilevel interconnect only functions as an interconnect and a multilevel interconnect shown in
The buffer layer 47 has, in addition to the function as an interconnect, an important function of relaxing a stress generated by the redistribution of an interconnect. This stress relaxing function is imparted to the buffer layer intentionally. Of the constituent elements of the semiconductor device of Embodiment 1, only the buffer layer 47 is imparted with a stress relaxing function intentionally. By intentionally disposing the buffer layer 47, a stress concentrated on the triple point X can be relaxed sufficiently. The buffer layer 47 is treated as an independent element in order to express this intention.
Moreover, as described above, the redistribution interconnect 50 has, in addition to a function as an interconnect, a function of completing the packaging in the stage of a semiconductor wafer. It is different in the function from a simple interconnect for the point that it converts the space of the uppermost-level interconnect 43a to the space of the bump electrode 56 and leads the uppermost-level interconnect 43a to the bump electrode 56. The redistribution interconnect 50 is therefore described separately from the multilevel interconnect. The redistribution interconnect 50 is sufficiently thicker than interconnects constituting the multilevel interconnect, which suggests that a stress generated at the redistribution interconnect 50 increases and peeling at the interface Y just below the triple point X tends to occur.
The constitution of the buffer layer 47 in Embodiment 1 will next be described. The buffer layer 47 preferably has a width greater than that of the uppermost-level interconnect 43a to which the buffer layer 47 is connected and greater than that of the opening portion 49. When the width of the buffer layer 47 is greater than that of the uppermost-level interconnect 43a, the buffer layer 47 can be laid just above the interface Y between the uppermost-level interconnect 43a and uppermost-level interconnect 43b and the transmission of a stress to the interface Y can be prevented fully. This makes it possible to prevent the peeling at the interface Y due to the stress and moreover, prevent short-circuit faults which will otherwise occur between the uppermost-level interconnects 43a and 43b. In addition, by adjusting the width of the buffer layer 47 greater than that of the opening portion 49, the buffer layer 47 can be formed just below the triple point X on which a stress is concentrated. This makes it possible to sufficiently relax the transmission of the stress from the triple point X on which a stress is concentrated to a position just below the triple point X. This also prevents the peeling at the interface Y due to stress.
A manufacturing method of a semiconductor device according to Embodiment 1 will next be described. First, an n channel MISFET Q1 and a p channel MISFET Q2 as illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
A reliability test (selection test) in which the semiconductor device thus manufactured is operated in repetition while applying to it a temperature change, for example, between −50° C. to 125° C. is then performed. At this time, a heat load is added to the semiconductor device repeatedly, which causes expansion and contraction of films constituting the semiconductor device. In particular, a contraction stress occurs in the nickel film 52 which is a portion of the redistribution interconnect 50 and the polyimide resin film 48 as illustrated in
The reliability test is followed by the electrical characteristics test of the semiconductor device. Although there occurs a potential difference between the uppermost-level interconnect 43a and uppermost-level interconnect 43b, drifting of copper between the uppermost-level interconnect 43a and uppermost-level interconnect 43b does not occur because peeling at the interface Y is prevented. Accordingly, a short-circuit fault resulting from the conduction between the uppermost-level interconnect 43a and uppermost-level interconnect 43b does not occur. The semiconductor device thus manufactured has therefore improved reliability.
A modification example of the semiconductor device of Embodiment 1 will next be described.
The uppermost-level interconnect 43a is formed below the opening portion 46 and another uppermost-level interconnect 43b is formed close to the uppermost-level interconnect 43a. When peeling occurs at the interface Y between the silicon oxide film 42b and silicon nitride film 44 which is present in the vicinity of the opening portion 46, the drifting of copper inevitably causes short-circuit between the uppermost-level interconnect 43a and uppermost-level interconnect 43b. In particular when the buffer layer 47 is not disposed, the redistribution interconnect 50 is formed via the opening portion 46. Then, the interface Y inevitably exists just below the triple point X and peeling at the interface Y tends to occur by a stress. Here, as illustrated in Embodiment 1, by disposing the buffer layer 47, even if the interface Y exists below the triple point X, it is possible to prevent peeling at the interface Y due to a stress relaxing effect and increase of distance between the triple point X and interface Y. Moreover, in the modification example, the buffer layer 47 is extended in the lateral direction of
In Embodiment 1, the buffer layer 47 is disposed on the uppermost-level interconnect 43a by using the opening portion 46 as illustrated in
The semiconductor device of Embodiment 2 has the below-described structure. The manufacturing method of it will next be described referring to some drawings.
Steps after the formation of the uppermost-level interconnects 43a and 43b will next be described. As illustrated in
A trench penetrating the silicon nitride film 44 and silicon oxide film 45 and reaching the uppermost-level interconnect 43a is formed using photolithography and etching. A tungsten film is formed over the silicon oxide film 45 including the inside of the trench. This tungsten film can be formed using, for example, CVD. The surface of the tungsten film is then polished by, for example, CMP to remove an unnecessary portion of the tungsten film. By this step, the plug 60 is formed by burying the tungsten film in the trench.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
In Embodiment 2, an example of forming an interlayer insulating film between the buffer layer 47 and redistribution interconnect from the film stack of the silicon oxide film 61, silicon nitride film 62 and polyimide resin film 48 was described. The interlayer insulating film may be composed alone of the polyimide resin film 48 without forming the silicon oxide film 61 and silicon nitride film 62.
The present invention was described specifically based on some embodiments of the present invention. It is needless to say that the invention is not limited to or by these embodiments and changes may be made without departing from the scope of the present invention.
The present invention can be used widely in the manufacturing industry of semiconductor devices.
Number | Date | Country | Kind |
---|---|---|---|
2005-258091 | Sep 2005 | JP | national |