Patent Application
20170162519
The present application makes reference to, claims priority to, and claims the benefit of Korean Patent Application No. 10-2015-0172532, filed on Dec. 4, 2015, in the Korean Intellectual Property Office and titled “SEMICONDUCTOR DEVICE,” the contents of which are hereby incorporated herein by reference in their entirety.
Present semiconductor devices and methods for manufacturing semiconductor devices are inadequate, for example resulting in excess cost, decreased reliability, or package sizes that are too large. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.
Various aspects of this disclosure provide a semiconductor package and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor package, and a semiconductor package resulting therefrom, that comprises attaching at least one semiconductor die to a metal plate, encapsulating the at least one semiconductor die on the metal plate using an encapsulant, and dicing the metal plate and the encapsulant.
The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like.
As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.”
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as “upper,” “above,” “lower,” “below,” “side,” and the like, may be used in distinguishing one element from another element in a relative manner. It should be understood, however, that components may be oriented in different manners, for example a semiconductor device may be turned sideways so that its “top” surface is facing horizontally and its “side” surface is facing vertically, without departing from the teachings of the present disclosure.
In the drawings, the thickness or size of layers, regions, and/or components may be exaggerated for clarity. Accordingly, the scope of this disclosure should not be limited by such thickness or size. Additionally, in the drawings, like reference numerals may refer to like elements throughout the discussion.
It will also be understood that when an element A is referred to as being “connected to” or “coupled to” an element B, the element A can be directly connected to the element B or indirectly connected to the element B (e.g., an intervening element C (and/or other elements) may be present between the element A and the element B).
Various aspects of the present disclosure relates to a semiconductor device and a manufacturing method thereof.
Certain embodiments of the disclosure relate to a method for fabricating a semiconductor package and a semiconductor package using the same.
Recently, with the trend toward smaller and lighter terminals for mobile communication, such as a cellular phone or a smart phone, or small-sized electronic devices, such as a tablet PC, a notebook PC, a MP3 player, or a digital camera, semiconductor packages constructing the small-sized electronic devices are also becoming smaller and lighter in weight. According to the miniaturization of electronic products, methods for reducing sizes of the semiconductor packages are being intensively researched. However, mechanical strengths of products may be compromised and it may also be difficult to support a semiconductor die by focusing on the miniaturization of products.
Embodiments of the present disclosure provide a method for fabricating a semiconductor package and a semiconductor package using the same, which can improve reliability of the package while reducing warpage.
According to an aspect of the present disclosure, there is provided a method for fabricating a semiconductor package, the method including preparing at least one semiconductor die having a conductive bump formed on its top surface, attaching the at least one semiconductor die to a metal plate, encapsulating the at least one semiconductor die on the metal plate using an encapsulant, and dicing the metal plate and the encapsulant to fabricate the semiconductor package.
According to another aspect of the present disclosure, there is provided a semiconductor package using the method for fabricating a semiconductor package, the semiconductor package including a semiconductor die having a conductive bump formed on its top surface, a metal plate formed under the semiconductor die, and an encapsulant encapsulating the semiconductor die on the metal plate.
Various advantages, aspects and novel features of the present disclosure, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.
Hereinafter, examples of embodiments of the disclosure will be described in detail with reference to the accompanying drawings such that they can readily be made and used by those skilled in the art.
Referring to
In the preparing of the semiconductor die (S10), the semiconductor die 150 as a basic element of the semiconductor package according to an embodiment of the present disclosure is prepared. In detail, the preparing of the semiconductor die (S10) includes forming a redistribution layer (S11), grinding (S12) and first dicing (S13).
In the forming of the redistribution layer (S11), the redistribution layer 110 is formed on the wafer 10. Note that the redistribution layer 110 may also be referred to herein as a redistribution structure. As illustrated in
The redistribution layer 110 (e.g., one or more conductive layers thereof) may be made of one selected from the group consisting of copper, aluminum, gold, silver, palladium and equivalents thereof using electroless plating, electroplating and/or sputtering, but aspects of the present disclosure are not limited to such materials and/or processes. In addition, patterning or routing of the first redistribution layer 111 and/or second redistribution layer 112 may be performed by photolithography using a photoresist, but aspects of the present disclosure are not limited thereto.
The dielectric layer 120 may be made of one selected from the group consisting of oxide, nitride, polyimide, benzocyclobutene, polybenzoxazole, bismaleimide triazine (BT), phenol resin, epoxy, and equivalents thereof, but aspects of the present disclosure are not limited thereto. In addition, the dielectric layer 120 may be formed by one selected from the group consisting of spin coating, spray coating, dip coating, rod coating, chemical vapor deposition (CVD) and equivalents thereof, but aspects of the present disclosure are not limited thereto.
In addition, in the forming of the redistribution layer (S11), after forming the redistribution layer 110, the conductive bump 130 may be formed on the redistribution layer 110. The conductive bump 130 may be formed on the second redistribution layer 112 exposed to the outside by the second dielectric layer 122. The conductive bump 130 may be made of a eutectic solder (Sn37Pb), a high lead solder (Sn95Pb), a lead-free solder (SnAg, SnAu, SnCu, SnZn, SnZnBi, SnAgCu, or SnAgBi), and equivalents thereof, but aspects of the present disclosure are not limited thereto. In addition, the conductive bump 130 may be formed on the redistribution layer 110 by a reflow process, a solder ball drop process and/or an equivalent thereof, but aspects of the present disclosure are not limited thereto. As an example, the conductive bump 130 may include a solder ball, a conductive pillar such as a copper pillar, and/or a conductive post having a solder cap formed on a copper pillar.
In the grinding (S12), a bottom surface of the wafer 10 is grinded. As illustrated in
In the first dicing (S13), the wafer 10′ is diced to fabricate an individual semiconductor die 150. In the first dicing (S13), the wafer 10′ may be diced along dotted lines, as illustrated in
In the attaching of the semiconductor die (S20), the semiconductor die 150 is attached to the metal plate 160. As illustrated in
The metal plate 160 is shaped of a flat plate made of a metal. The metal plate 160 may be made of one selected from the group consisting of stainless steel (SUS), copper, aluminum, and equivalents thereof, but the scope of the present disclosure is not limited thereto. The metal plate 160 is preferably made of stainless steel (SUS). Here, the stainless steel (SUS) refers to a kind of steel including at least 11% chrome added to iron to reinforce corrosion resistance. In addition, the stainless steel (SUS) is classified into various types according to contents of chrome, nickel, molybdenum, etc. As an example, the stainless steel (SUS) may be exemplified as SUS201, SUS303, SUS303Se, SUS304, SUS304L, SUS305, SUS309S, SUS310S, SUS316, SUS316L, SUS317, SUS317L, SUS312, SUS321, SUS347, SUS409L, SUS410L, SUS430, SUS434, SUS436L, SUS444, and so on, but aspects of the present disclosure are not limited thereto. The metal plate 160 may serve to reinforce mechanical strength of the semiconductor die 150 while rapidly emitting heat generated from the semiconductor die 150 to the outside. In addition, the metal plate 160 is capable of preventing the semiconductor package from shrinking at high temperature and can reduce a warpage phenomenon occurring during fabrication of the semiconductor package, thereby improving reliability of the semiconductor package.
In the encapsulating (S30), an encapsulant 170 encapsulates the semiconductor die 150 positioned on the metal plate 160. As illustrated in
In the second dicing (S40), the metal plate 160 and the encapsulant 170 are diced. As illustrated in
The semiconductor package 100 fabricated by the method according to the present disclosure includes the semiconductor die 150 having the conductive bump 130 formed on its top surface, the metal plate 160 formed under the semiconductor die 150, the adhesive member 140 interposed between the semiconductor die 150 and the metal plate 160, and the encapsulant 170 encapsulating the semiconductor die 150 on the metal plate 160.
Referring to
In the forming of the redistribution layer (S11), a redistribution layer 110 (or redistribution structure) having a multi-layered structure and a dielectric layer 120 covering the redistribution layer 110 are formed on a wafer 10. Since the forming of the redistribution layer (S11) is the same as that illustrated in
In the grinding (S12), a bottom surface of the wafer 10 is grinded. As illustrated in
In the first dicing (S13), the wafer 10′ is diced to fabricate an individual semiconductor die 250. In the first dicing (S13), the wafer 10′ may be diced along dotted lines, as illustrated in
In the attaching of the semiconductor die (S20), as illustrated in
The metal plate 160 is shaped of a flat plate made of a metal. The metal plate 160 may be made be made of one selected from the group consisting of stainless steel (SUS), copper, aluminum, and equivalents thereof. The metal plate 160 is preferably made of stainless steel (SUS). The metal plate 160 may serve to reinforce mechanical strength of the semiconductor die 250 while rapidly emitting heat generated from the semiconductor die 250 to the outside. In addition, the metal plate 160 is capable of preventing the semiconductor package from shrinking at high temperature and can reduce a warpage phenomenon occurring during fabrication of the semiconductor package, thereby improving reliability of the semiconductor package.
In the encapsulating (S30), an encapsulant 170 encapsulates the semiconductor die 250 positioned on the metal plate 160. As illustrated in
In the second dicing (S40), the metal plate 160 and the encapsulant 170 are diced. As illustrated in
The semiconductor package 200 fabricated by the method according to the present disclosure includes the semiconductor die 250 having the conductive bump 130 formed on its top surface, the metal plate 160 formed under the semiconductor die 250, the adhesive member 240 interposed between the semiconductor die 250 and the metal plate 160, and the encapsulant 170 encapsulating the semiconductor die 250 on the metal plate 160
The discussion herein included numerous illustrative figures that showed various portions of an electronic device assembly and method of manufacturing thereof. For illustrative clarity, such figures did not show all aspects of each example assembly. Any of the example assemblies and/or methods provided herein may share any or all characteristics with any or all other assemblies and/or methods provided herein.
In summary, various aspects of this disclosure provide a semiconductor package and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor package, and a semiconductor package resulting therefrom, that comprises attaching at least one semiconductor die to a metal plate, encapsulating the at least one semiconductor die on the metal plate using an encapsulant, and dicing the metal plate and the encapsulant. While the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, it is intended that the disclosure not be limited to the particular example(s) disclosed, but that the disclosure will include all examples falling within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2015-0172532 | Dec 2015 | KR | national |
