Patent Application
20250031417
This application claims priority to Chinese Patent Application No. 202310901540.6, titled “METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE,” filed on Jul. 21, 2023 with the China National Intellectual Property Administration, which is incorporated herein by reference in its entirety.
The present disclosure relates to the technical field of semiconductor, and in particular to a semiconductor device and a method for manufacturing the same.
With continuous development of the technology node and key techniques in integrated circuits, nanosheet gate-all-around field-effect transistors (NS GAAFETs) would replace conventional fin field-effect transistors (FinFETs) at the 3 nm and more advanced nodes. Furthermore, the next generation of three-dimensional stacked field-effect transistors (3DS FETs) would become a main technical route after entering the 1 nm node.
Currently, there are mainly two manners for achieving the 3DS FETs. One is sequential integration, and the other is self-aligned simultaneous integration. The sequential integration is simpler in processing and has more applicable materials and techniques, but is limited due to performances and costs. The self-aligned simultaneous integration can achieve a higher degree of integration and better performances, but are subject to a complicated integration process and various processing challenges.
In addition, an increasing attention has been drawn by the backside power distribution network (BS-PDN) techniques, in which a power distribution network (PDN) traditionally fabricated in a backend of line (BEOL) is disposed at a back of a wafer through appropriate processing. In comparison with the front-side power distribution network (FS-PDN), semiconductor devices manufactured through BS-PDN have a higher integration density and smaller voltage loss of a power source due to a voltage drop on interconnections. An urgent problem is how to manufacture novel semiconductor devices through combining the 3DS FETs and the PDN fabrication to increase the integration density.
In view of at least the above issues, a semiconductor device and a method for manufacturing the semiconductor device are provided according to embodiments of present disclosure. An integration density of semiconductor devices is increased with fewer fabrication processes and fewer difficulties.
In a first aspect, a method for manufacturing a semiconductor device is provided according to an embodiment of the present disclosure. The method comprises: forming a first field-effect transistor disposed on a substrate and a first isolation layer disposed on the first field-effect transistor; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first field-effect transistor; forming a second isolation layer which is disposed on the first isolation layer and the metal layer; and forming a second field-effect transistor which is disposed on the second isolation layer, where a second through hole is disposed in the second field-effect transistor and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer.
In an embodiment, forming the first field-effect transistor disposed on the substrate and the first isolation layer disposed on the first field-effect transistor comprises: forming stacking layers on the substrate, where the stacking layers comprise at least one first semiconductor layer and at least one second semiconductor layer which are alternately stacked; etching the stacking layers and the substrate to form a fin, where the substrate of a partial thickness is removed in the etching; forming a dummy gate, a first spacer, and a mask layer on the fin; etching the stacking layers by using at least the first spacer as a mask; etching the at least one first semiconductor layer from a side surface of the etched stacking layers to form at least one cavity; forming at least one second spacer in the at least one cavity; forming a source and a drain at two sides of the stacking layers; forming a third isolation layer on the source and the drain; removing the dummy gate and the etched at least one first semiconductor layer to release the at least one second semiconductor layer as a channel; forming a gate surrounding the channel; forming a third through hole running in the third isolation layer, where a metal material filled in the third through hole serves as a second contact plug, and the second contact plug is configured to connect the metal layer electrically.
In an embodiment, before forming the second isolation layer which is disposed on the first isolation layer and the metal layer, the method further comprises: planarizing the metal layer until a top surface of the metal layer is flush with a top surface of the first isolation layer.
In an embodiment, a material of the metal layer comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.
In an embodiment, a thickness or width of the metal layer ranges from 1 nm to 10000 nm.
In an embodiment, the metal layer comprises only a single layer or comprises multiple layers.
In an embodiment, the first field-effect transistor and the second field-effect transistor each is a nanosheet gate-all-around field-effect transistor.
In a second aspect, a semiconductor device is provided according to embodiments of the present disclosure. The semiconductor device comprises: a first field-effect transistor, a first isolation layer, a second isolation layer, and a second field-effect transistor, which are stacked on a substrate according to the above-listed sequence; where a metal layer is disposed in the first isolation layer, the metal layer is electrically connected to the first field-effect transistor, a first contact plug is disposed in the second field-effect transistor, and the first contact plug is electrically connected to the metal layer.
In an embodiment, a material of the metal layer comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.
In an embodiment, a thickness or width of the metal layer ranges from 1 nm to 10000 nm.
The semiconductor device and the method for manufacturing the semiconductor device are provided according to embodiments of the present disclosure. The first field-effect transistor is formed on the substrate, the first isolation layer is formed on the first field-effect transistor, the first through hole is formed in the first isolation layer, and the metal layer is deposited in the first through hole to serve as a power distribution supply network. The power distribution supply network is configured to transmit power to field-effect transistors. The metal layer is electrically connected to the first field-effect transistor, and hence is capable to transmit power to the first field-effect transistor. A front-side power distribution network (FS-PDN) structure of the first field-effect transistor is formed since the first field-effect transistor and the power distribution supply network are disposed at the same side of the substrate. The second isolation layer is formed on the first isolation layer and the metal layer, and the second field-effect transistor is formed on the second isolation layer. The second through hole runs through the second field-effect transistor and the second isolation layer, and is filled with metal material to form a first contact plug. The first contact plug is electrically connected to the metal layer, such that the metal layer can transmit power to the second field-effect transistor. Thereby, a backside power distribution network (BS-PDN) structure of the second field-effect transistor is formed. The BS-PDN structure occupies little space, and can downscale the semiconductor device. In addition, the first field-effect transistor and the second field-effect transistor share the same metal layer for power supply, which improves an integration density of semiconductor devices without thinning the substrate. The whole process has fewer steps and is less difficult.
In order to clarity illustration of the technical solutions according to embodiments of the present disclosure or conventional technology, hereinafter the drawings to be applied in embodiments of the present disclosure or technology are briefly described. Apparently, the drawings in the following descriptions are only some embodiments of the present disclosure, and other drawings may be obtained by those skilled in the art based on the provided drawings without creative efforts.
In order to elucidate and clarify objectives, features and advantages of the present disclosure, hereinafter embodiments of the present disclosure are described in detail in conjunction of the drawings.
Various details are set forth in the following description to facilitate comprehensive understanding of the present disclosure. The present disclosure may further implemented in other ways different from those described herein. Those skilled in the art can deduce other implementations without deviating from concepts of the present disclosure, and hence the present disclosure is not limited to the following embodiments.
The present disclosure is described in detail in conjunction with schematic diagrams. When describing an embodiment, a device structure may not be partially enlarged to scale in a diagram showing a cross section of such device structure, so as to facilitate illustration. The schematic diagrams are only exemplary and shall not be construed as limitations on a protection scope of the present disclosure. In practice, the device structure shall have three-dimensional dimensions, e.g., a length, a width, and a depth.
In order to facilitate understanding, hereinafter a semiconductor device and a method for manufacturing the semiconductor device according to embodiments of the present disclosure are illustrated in detail in conjunction with the drawings.
Reference is made to
In S101, a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first field-effect transistor, are formed.
Herein a substrate may be provided, and the substrate may be Si or SiGe. The substrate may be made of bulk silicon and may be doped. In an embodiment, dopants are injected into the bulk silicon substrate, diffused, and then annealed, so as to form a highly-doped well region which has a desired well depth. In case of a p-type FET, the highly-doped well region comprises a n-type well, and injected dopants are n-type impurity ions, such as phosphorus (P) ions. In case of a n-type FET, the highly-doped well region comprises a p-type well, and injected dopants are p-type impurity ions, such as boron (B) ions.
In order to facilitate illustration, an upward direction refers to a direction pointing from the substrate to the first FET, and a downward direction refers to a direction pointing from the first FET to the substrate. Such definitions are for convenience and are not necessarily indicate a relationship with a direction of gravity.
In an embodiment, the first FET is formed on the substrate, and the first FET may be a nanosheet gate-all-around FET, or another type of FET, which is not limited herein. Then, the first isolation layer may be formed on a surface of the first FET. The first isolation layer is configured to isolate the first FET from the second FET.
In an embodiment, the semiconductor device may be a three-dimensional stacked FET (3DS FET) or a vertical FET (VFET). The 3DS FET may be a complementary FET (CFET). It is appreciate that other types of FETs may be used. Reference is made to
In S102, a first through hole is formed in the first isolation layer, where a metal layer is deposited in the first through hole.
Herein a through hole formed in the first isolation layer 20 is called the first through hole. The first through hole may run through the first isolation layer 20. A shape of the first through hole is not specifically limited herein. For example, the first through hole may comprise a first portion and a second portion, which are physically connected. The first portion is disposed at a top surface of the first isolation layer 20, and a second part runs from the first portion to a bottom surface the first isolation layer 20. A lateral dimension of the first part may be larger than that of the second part. The first portion may be configured to form a power distribution supply network, and the second portion may be configured to connect the first portion and the first FET.
The metal layer 30 may be deposited in the first through hole, such that the metal layer 30 serves as the power distribution supply network and is electrically connected to the first FET 10. Thereby, the power distribution supply network can transmit power to the first FET 10. The first FET 10 and the power distribution supply network are disposed on the same side of the substrate 100, and hence an FS-PDN structure of the first FET is formed.
In an embodiment, a material of the metal layer 30 may include at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag. Hence, the metal layer has good heat resistance and low electrical resistance, which facilitate conducting a large current.
In an embodiment, a thickness of the metal layer 30 may be greater than or equal to 1 nm, and less than or equal to 10000 nm. A width of the metal layer 30 can also be greater than or equal to Inm, and less than or equal to 10000 nm. Those skilled in the art can select specific dimensions according to an actual situation.
In an embodiment, the metal layer 30 may be a single layer or comprise multiple layers, which depends on a specific circuit design. In a case that the metal layer 30 comprise multiple layers, whether the multiple layers are interconnected may be configured based on an actual situation.
In S103, a second isolation layer disposed on the first isolation layer and the metal layer is formed.
Herein the second isolation layer 40 may be formed on the first isolation layer 20 and the metal layer 30. A material of the second isolation layer 40 can be identical to or different from that of the first isolation layer 20. The second isolation layer 40 is configured to isolate the metal layer 30 form the second FET 60. After being formed, the second isolation layer 40 may be planerized through chemical-mechanical planarization (CMP).
In an embodiment, before the second isolation layer 40 is formed on the first isolation layer 20 and the metal layer 30, the metal layer 30 may be planerized until a top surface of the metal layer 30 is flush with the top surface of the first isolation layer 20. Thereby, performances of the semiconductor device are improved.
In S104, a second FET disposed on the second isolation layer is formed.
In an embodiment, the second FET 60 is formed on the second isolation layer 40. A process of manufacturing the second FET 60 may refer to that of manufacturing the first FET 10. A channel material of the second FET 60 and a channel material of the first FET 10 may be identical or different. The second FET 60 may also be a gate-all-around FET or another type of FET.
In an embodiment, a through hole may be formed in the second FET 60 and the second isolation layer 40, and is called a second through hole. The second through hole may be filled with a metal material, so as to form a first contact plug 50. The first contact plug 50 may be electrically connected to the metal layer 30, such that the metal layer 30 can further transmit power to the second FET 60. Thereby, a BS-PDN structure of the second FET is formed. The BS-PDN structure occupies less space, which reduces a dimension of the semiconductor device and increases an integration density of semiconductor devices. In addition, the first FET 10 and the second FET 60 share the same metal layer 30 for power supply, and thus it is not necessary to provide separate metal layers for the FETs, which reduces a quantity of metal layers and increases the integration density of semiconductor devices.
Herein sequential integration is adopted to manufacture the semiconductor device, and materials and processing can be selected from a variety of candidates. When manufacturing conventional BS-PDN structures, it is necessary to thin a wafer having a large thickness of approximate hundreds of microns to approximate ten to twenty microns. In technical solutions provided herein, the buried metal layer 30 is formed in the isolation layers between an upper layer and a lower layer of FETs to provide the power distribution supply network. A total thickness of the first isolation layer 20 and the second isolation layer 40 is as small as several microns or several nanometers, and thus the thinning is not necessary, which reduces steps in the processing and renders the manufacture less difficult.
Hereinafter the first FET 10 being a nanosheet gate-all-around FET is taken as an example for a brief illustration of forming the first FET 10 and the first isolation layer 20 that are sequentially stacked on the substrate 100.
Reference is made to
In an embodiment, stacking layers are grown through epitaxy on the substrate, and the stacking layers comprises least one first semiconductor layer and at least one second semiconductor layer which are alternately stacked. Reference is made to
In an embodiment, a material of the first semiconductor layer 101 and a material of the second semiconductor layer 102 may be configured on requirement. The first semiconductor layer 101 may be a germanium-based film. The germanium-based film may include an epitaxial germanium layer, an epitaxial silicon germanium layer, or a combination of the two. The second semiconductor layer 102 can be an epitaxial silicon layer. For example, the stacking layers of the first semiconductor layer(s) and the second semiconductor layer(s) are SiGe/Si layers, and the SiGe/Si layers are grown through epitaxy as periodic superlattice. The epitaxy may be reduced pressure epitaxy, molecular beam epitaxy, or the like.
Then, the stacking layers and the substrate may be etched to form a fin, where the substrate of a partial thickness is removed during the etching. Reference is made to
In one embodiment, a sacrificial layer 103 covering the stacking layers is formed. The sacrificial layer 103 may be made of polycrystalline silicon (PolySi, or p-si) or amorphous silicon (a-si). A part of the sacrificial layer is removed through etching, and then a third spacer 104 is deposited. The third spacer 104 may be made of silicon nitride (SiNx) or silicon oxide.
Afterwards, the remaining sacrificial layer 103 is removed through anisotropic etching, such that only the third spacer 104 remains on the stacking layers. The third spacer 104 may serve as a hard mask in subsequent photolithography. That is, the epitaxial stacking layers is then etched by using the third spacer 104 as the hard mask to form the fin which also has a stacking structure. Then, the third spacer 104 is removed, and thus the formed fin may be as shown in
In an embodiment, shallow trench isolation (STI) 105 may be then formed around the fin, so as to separate adjacent transistors. In such step, a cross-sectional view along the Y-Y direction and a cross-section view along the X-X direction may be as shown in
In an embodiment, a dummy gate 107, first spacers 109, and a mask layer 108 may be then formed on the fin, as shown in
In an embodiment, the stacking layers may be then etched from its surface by using the first spacers 109 as a mask, and only the stacking layers disposed beneath the dummy gate 107 and the first spacers 109 remains after the etching. Then, the first semiconductor layer(s) 101 are etched from a side surface of the etched stacking layers, so as to form cavities at two sides of the first semiconductor layer(s), and second spacers 116 are formed in the cavities. In such step, a cross-sectional view along the X-X direction and a cross-sectional view along the Y-Y direction may be as shown in
The second spacers 116 may be formed at a periphery of the fin through deposition. After being deposited, a material for forming the second spacers 116 may be etched until it is flush with the second semiconductor layer 102 at a side surface of the fin. Thereby, the second spacers 116 are formed at two ends of the first semiconductor layer 101.
In an embodiment, a source and a drain may be then formed through epitaxy and doping. In case of a p-type FET, a material of the source and the drain may be boron-doped SiGe (SiGe: B). In case of an n-type FET, a material of the source and the drain may be phosphorus-doped silicon (Si: P). Thereby, first source-or-drain regions 110 are formed. In such step, a cross-sectional view along the X-X direction and a cross-sectional view along the Y-Y direction may be shown in
Afterwards, a third isolation layer (ILD) 111 is deposited on a surface of the first source-or-drain regions 110, as shown in
Afterwards, the dummy gate 107 mad of polycrystalline silicon (PolySi, p-si) or amorphous silicon (a-si) and the gate dielectric layer 106 made of a dielectric are selectively etched or eroded, as a shown in
Afterwards, a first gate 113 surrounding the channel is formed, as shown in
Reference is made to
Herein the first isolation layer 20 may be deposited on the nanosheet gate-all-around FET, as shown in
In an embodiment, the second FET 60 may comprise a third semiconductor layer 602 which serves as a channel, fourth spacers 609, fifth spacers 616, second source-or-drain regions 610, a second interface layer 612, a second gate 613, a fifth isolation layer 611, a sixth isolation layer 615, and a third contact plug 614. In order to form the third contact plug 614, the sixth isolation layer 615 and the fifth isolation layer 611 may be etched to form through hole(s) reaching the second source-or-drain region(s) 610. At the same time, the sixth isolation layer 615, the fifth isolation layer 611, the second source-or-drain regions 610 and the second isolation layer 40 may be sequentially etched to form a through silicon via (TSV), and a metal material is deposited in the TSV to form the first contact plug 50. That is, the second FET 60 and the PDN are interconnected via the TSV. A cross-sectional view of such structure along the X-X direction is as shown in
The method for manufacturing the semiconductor device is provided according to embodiments of the present disclosure. The first FET is formed on the substrate, the first isolation layer is formed on the first FET, the first through hole is formed in the first isolation layer, and the metal layer is deposited in the first through hole to serve as a power distribution supply network. The power distribution supply network is configured to transmit power to FETs. The metal layer is electrically connected to the first FET, and hence is capable to transmit power to the first FET. The FS-PDN structure of the first FET is formed since the first FET and the power distribution supply network are disposed at the same side of the substrate. The second isolation layer is formed on the first isolation layer and the metal layer, and the second FET is formed on the second isolation layer. The second through hole runs through the second FET and the second isolation layer, and is filled with metal material to form a first contact plug. The first contact plug is electrically connected to the metal layer, such that the metal layer can transmit power to the second FET. Thereby, the BS-PDN structure of the second FET is formed. The BS-PDN structure occupies little space, and can downscale the semiconductor device. In addition, the first FET and the second FET share the same metal layer for power supply, which improves an integration density of semiconductor devices without thinning the substrate. The whole process has fewer steps and is less difficult.
On a basis of the foregoing embodiment, a semiconductor device is provided according to an embodiment of the present disclosure. Reference is made to
The semiconductor device may comprise a first FET 10, a first isolation layer 20, a second isolation layer 40, and a second FET 60, which are stacked on the substrate 100 according to the above-listed sequence. A metal layer 30 is disposed in the first isolation layer 20, and is electrically connected to the first FET 10. A first contact plug 50 is disposed in the second FET 60, and is electrically connected to the metal layer 30.
In an embodiment, the first FET 10 and the second FET 60 each may be a nanosheet gate-all-around FET, as shown in
In an embodiment, a material of the metal layer comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.
In an embodiment, a thickness or a width of the metal layer is greater than or equal to 1 nm, and less than or equal to 10000 nm.
The semiconductor device is provided according to an embodiment of the present disclosure The semiconductor device comprises the first FET, the first isolation layer, the second isolation layer, and the second FET, which are stacked on the substrate according to the above-listed sequence. The metal layer is disposed in the first isolation layer and is electrically connected to the first FET. The first contact plug is disposed in the second FET, and is electrically connected to the metal layer. The metal layer can serve as a power distribution supply network configured to transmit power to the FETs. The metal layer is electrically connected to the first FET, and hence the metal layer can transmit power to the first FET. The FS-PDN structure of the first FET is formed since the first FET and the power distribution supply network are disposed at the same side of the substrate. The metal layer can transmit power to the second FET, and thereby the BS-PDN structure of the second FET is formed. The BS-PDN structure occupies little space, and can downscale the semiconductor device. In addition, the first FET and the second FET share the same metal layer for power supply, which improves an integration density of semiconductor devices without thinning the substrate. The whole process has fewer steps and is less difficult.
The embodiments of the present disclosure are described in a progressive manner, and each embodiment places emphasis on the difference from other embodiments. Therefore, one embodiment can refer to other embodiments for the same or similar parts. Since the semiconductor devices disclosed in the embodiments corresponds to the methods disclosed in the embodiments, the description of the semiconductor devices is simple, and reference may be made to the relevant part of the methods.
The foregoing embodiments disclosed above are only preferable embodiments of the present disclosure, and are not intended to limit the present disclosure. With the method and technical content disclosed above, those skilled in the art can make some variations and improvements to the technical solutions of the present disclosure, or make some equivalent variations on the embodiments without departing from the scope of technical solutions of the present disclosure. All simple modifications, equivalent variations and improvements made based on the technical essence of the present disclosure without departing the content of the technical solutions of the present disclosure fall within the protection scope of the technical solutions of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310901540.6 | Jul 2023 | CN | national |
