Patent Application
20160071801
In general, various semiconductor devices such as resistors, transistors, and diodes are formed on or within a semiconductor substrate. These semiconductor devices are formed from conductor layers and dielectric layers. Etching processes are applied to expose a contact region of the conductor layers to electrically connect one semiconductor device to another. The conventional etching process generally needs an etch stop layer with a significant thickness to prevent over-etching. However, the etch stop layer results in high resistance-capacitance time delay (RC delay).
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.
Embodiments of the present disclosure are directed to providing an etching method for fabricating a semiconductor device. In the etching method, an etch stop layer is used to prevent over-etching. The etch stop layer includes a metallic nitride layer, and the etch stop layer can be formed with a relatively small thickness so as to decrease resistance-capacitance time delay (RC delay) of the semiconductor device. Compared with a conventional etching stop layer with a thickness of 250 Angstroms, the etch stop layer including the metallic nitride layer can be formed with a smaller thickness, such as 60 Angstroms. As a result, the semiconductor device using the etching stop layer including the metallic nitride layer has a relatively small resistance-capacitance time delay. In one embodiment, the etch stop layer has a multi-layer structure. The etch stop layer includes a metallic nitride layer and a diffusion barrier layer. The diffusion barrier layer is used to prevent diffusion of a conductor material disposed under the etch stop layer.
The semiconductor substrate 110 is defined as any construction including semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.
The first dielectric layer 120 and the second dielectric layer 130 include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the low-k dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond™ (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, other proper materials, or combinations thereof. In some embodiments, the first dielectric layer 120 and the second dielectric layer 130 include a multilayer structure having multiple dielectric materials.
The conductor M is a conductor line for transmitting signals and includes a conductive material, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or an alloy thereof.
The etch stop layer 140 includes a diffusion barrier layer 142 and a metallic nitride layer 144. The diffusion barrier layer 142 is used to prevent diffusion of the material of the conductor M when the semiconductor device 100 is fabricated. The metallic nitride layer 144 is used to prevent over-etching when an etching process is performed for fabricating the semiconductor device 100. The metallic nitride layer 144 is formed with a group III metal nitride material, such as GaN or AN. The material forming the diffusion barrier layer 142 is selected in accordance with the material of the conductor M. In some embodiments, the diffusion barrier layer 142 is formed from a silicon carbon based material, such as SiCN, SiCO or SiCON.
The etch stop layer 140 can be formed with a relatively small thickness so as to decrease resistance-capacitance time delay of the semiconductor device 100. In one embodiment, the thickness of the diffusion barrier layer 142 ranges from 30 Angstroms to 60 Angstroms, and the thickness of the metallic nitride layer 144 ranges from 5 Angstroms to 15 Angstroms. In some embodiments, the thickness of the diffusion barrier layer 142 is 50 Angstroms, and the thickness of the metallic nitride layer 144 is 10 Angstroms.
Referring to
As shown in
As shown in
Referring to
At operation 330, the diffusion barrier layer 232 is formed on the first dielectric layer 220 and the first conductor M1 to prevent diffusion of the material of the first conductor M1, as shown in
At operation 350, the second dielectric layer 240 is formed on the metallic nitride layer 234, as shown in
Comparing with the conventional material forming a conventional etch stop layer, the etch stop layer formed from metallic nitride in the embodiments of the present disclosure can be formed with a relatively small thickness, thereby decreasing RC delay of the semiconductor device.
It is noted that the diffusion barrier layer used in the embodiments can be saved when a diffusion coefficient of the material of the first conductor M1 is acceptable.
The dielectric layer 420 is formed on the semiconductor substrate 410, and the etch stop layer 430 is formed between the dielectric layer 420 and the semiconductor substrate 410. In this embodiment, the etch stop layer 430 includes a metallic nitride layer 432 to prevent over-etching. The conductor 440 is used as a conductor line passing through the dielectric layer 420 and the etch stop layer 430 to contact with the contact region 412 of the semiconductor substrate 410.
In this embodiment, the etch stop layer 430 does not include a diffusion barrier layer, and thus a thickness of the etch stop layer 430 can be further decreased. Comparing with the semiconductor device 100, the semiconductor device 400 has a relatively small resistance-capacitance time (RC) delay because the etch stop layer 430 has a relatively small thickness. In one embodiment, a thickness of the etch stop layer 430 ranges from 5 Angstroms to 15 Angstroms.
Referring to
As shown in
Referring to
At operation 630, the dielectric layer 530 is formed on the metallic nitride layer 520, as shown in
In accordance with some embodiments, the present disclosure discloses an etching method. In the etching method, at first, a semiconductor substrate including a contact region is provided. Then, a metallic nitride layer is formed on the semiconductor substrate. Thereafter, a dielectric layer is formed on the metallic nitride layer. Then, an etching process is performed to form an opening passing through the dielectric layer and the metallic nitride layer to expose the contact region.
In accordance with certain embodiments, the present disclosure discloses a semiconductor device including a semiconductor substrate, a first dielectric layer, a second dielectric layer, an etch stop layer and a conductor. The first dielectric layer is formed on the semiconductor substrate, in which the first dielectric layer has a first opening. The second dielectric layer is formed on the first dielectric layer, in which the second dielectric layer has a second opening. The etch stop layer is formed between the first dielectric layer and the second dielectric layer, in which the etch stop layer has a third opening connecting the first opening to the second opening, and includes a metallic nitride layer. The conductor is formed in the first opening, the second opening and the third opening.
In accordance with certain embodiments, the present disclosure discloses a method for fabricating a semiconductor device. In the method, at first, a semiconductor substrate is provided. Then, a first dielectric layer and a first conductor are formed on the semiconductor substrate, in which the first dielectric layer has a first opening, and the first conductor is located in the first opening. Thereafter, a metallic nitride layer is formed on the first dielectric layer and the first conductor. Then, a second dielectric layer is formed on the metallic nitride layer. Thereafter, an etching process is performed to form a second opening passing through the diffusion barrier layer, the metallic nitride layer and the second dielectric layer to expose the first conductor. Then, a second conductor is formed in the second opening to enable the first conductor to be connected to the second conductor.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
