Patent Application
20230402361
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices are now widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic products, including for example digital cameras, digital music players, video game consoles, computer SSDs, PDAs and cellular telephones.
While many varied packaging configurations are known, flash memory semiconductor devices may in general be assembled as system-in-a-package (SIP) or multichip modules (MCM), where a plurality of semiconductor dies are mounted and interconnected to an upper surface of substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Once the dies are mounted and electrically connected to each other and the substrate, this assembly may be encapsulated in a molding compound.
One popular semiconductor memory package is a MicroSD card, which may be removably inserted into the slot of a host device. The MicroSD card has an outline having curves and straight edges. In order to singulate cards that are formed simultaneously from the same substrate, lasers are often used to cut the curved portions of the package outline, and saw blades are used to cut the straight portions of the package outline.
It has been determined that the laser generates mechanical stresses in the semiconductor package, and that cracks can form in the substrate at the beginning and/or end of laser cuts of the curved portions of the semiconductor package. Cracks can also form at discontinuous points of the package outline (i.e., where lines or curves come together at a non-zero angle). These cracks can sever electrical traces, damage semiconductor dies and otherwise damage or cause failure of the semiconductor package.
Moreover, modern day, high frequency semiconductor packages generate a lot of heat, and it is desirable to provide the molding compound with a high thermal conductivity. However, mold compounds of high thermal conductivity often have less strength, which exacerbates the cracking of the package substrate at curves or discontinuous points.
The present technology will now be described with reference to the figures, which in embodiments, relate to a semiconductor device including a substrate, semiconductor dies, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions where mechanical stresses develop in the device, such as at curves and/or discontinuous points around the outline of the substrate.
When the semiconductor device is singulated, the reinforcing blocks add strength to these mechanical stress points to prevent cracking of the substrate during singulation. The reinforcing blocks may be formed or mounted on a top and/or bottom surface of the substrate, at the substrate outline so that portions of the reinforcing blocks remain in the completed semiconductor device when the device is singulated from the substrate panel. The reinforcing blocks further allow a low strength, high thermal conductivity molding compound to be used to improve heat dissipation from the semiconductor device.
It is understood that the present technology may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the technology to those skilled in the art. Indeed, the technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be clear to those of ordinary skill in the art that the present technology may be practiced without such specific details.
The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal” as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially,” “approximately” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is 0.15 mm or alternatively ±2.5% of a given dimension.
For purposes of this disclosure, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when a first element is referred to as being connected, affixed, mounted or coupled to a second element, the first and second elements may be directly connected, affixed, mounted or coupled to each other or indirectly connected, affixed, mounted or coupled to each other. When a first element is referred to as being directly connected, affixed, mounted or coupled to a second element, then there are no intervening elements between the first and second elements (other than possibly an adhesive or melted metal used to connect, affix, mount or couple the first and second elements).
An embodiment of the present technology will now be explained with reference to the flowchart of
The substrate 100 is an example of a chip carrier medium provided to transfer signals, data and/or information between one or more semiconductor dies mounted on the chip carrier medium and a host device as explained below. Other examples of chip carrier mediums may be used, including a printed circuit board (PCB), a leadframe or a tape automated bonded (TAB) tape. The substrate may be formed of one or more core layers, each sandwiched between two conductive layers. The conductive layers may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42Fe/58Ni), copper plated steel, or other metals and materials suitable for use on substrate panels. The one or more core layers may be formed of various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like. The one or more core layers may be ceramic or organic in alternative embodiments.
The two or more conductive layers may be etched into conductance patterns comprising electrical connectors in step 202. These electrical connectors may be formed in one or both of the first major planar surface 104 and the second major planar surface 105 of the substrate 100, shown in the views of the substrate 100 in
As shown in the bottom view of
The substrate 100 may undergo a variety of further processing steps, including solder masking (step 204), electroplating of exposed contact pads (step 206), inspection and operational testing (step 208). Additional or alternative processing steps are contemplated.
In one example, the outline of each substrate may have straight sections and curved sections which meet each other. For example,
In accordance with aspects of the present technology, reinforcing blocks 122 may be formed on the substrate in step 210. As noted in the Background section and discussed below, mechanical stress points may develop in the substrates 100 when the substrates are singulated from the panel 102. In order to reinforce these points and help dissipate the stresses to prevent cracking of the substrate, the substrate 100 may built up at (at least) the points where mechanical stresses occur in the substrate. In one embodiment, these mechanical stress points occur at the beginning and end of laser-cut curved sections of the outline of the substrate (116a, 116b, 118a, 118b), and possibly along the curved sections as well (116). Mechanical stresses may also or alternatively occur at points of discontinuities (120).
The discrete point reinforcing blocks 122 in
As explained below, a molding compound may be applied to the first major surface 104 of substrate 100, which molding compound may extend for example 0.5 mm above surface 104. The discrete point reinforcing blocks 122 in
Instead of discrete point reinforcing blocks, the reinforcing blocks 122 may be applied in sections, each covering multiple stress points for example at the beginning and end of a curve. This embodiment is shown in
As a further example, the reinforcing block 122 may be applied as a ring around the entire outline of each substrate 100, as shown in
Once the reinforcing block or blocks have been formed on the substrate 100, components may be mounted on the substrate to form a completed semiconductor device 140. For example, in step 214, passive components 123 may be affixed to the substrate 100 as shown in the top view of
In step 216, one or more semiconductor dies may be mounted on the first major planar surface 104 of the substrate 100. For example,
Where multiple semiconductor dies 124 are included, the semiconductor dies 124 may be stacked atop each other in an offset stepped configuration to form a die stack. The number of dies 124 shown in the stack is by way of example only, and embodiments may include different numbers of semiconductor dies, including for example 1, 2, 4, 8, 16, 32 or 64 die. There may be other numbers of dies in further embodiments. The one or more dies may be affixed to the substrate and/or each other using a die attach film. As one example, the die attach film may be cured to a B-stage to preliminarily affix the dies 124 in the stack, and subsequently cured to a final C-stage to permanently affix the dies 124 to the substrate 100.
In step 220, the semiconductor dies 124 may be electrically interconnected to each other and to the substrate 100.
In step 222, a controller die 130 may be affixed on in the first major planar surface 104 of substrate 100 as shown in
In the embodiments shown in
In step 224, the panel 102 of semiconductor devices 140 may be encapsulated in a mold compound 134 as shown in the top and side views of
After assembly and encapsulation of the semiconductor devices 140, the semiconductor devices 140 may be singulated from each other and panel 102 in step 226 to form individual finished semiconductor devices 140, such as the one shown in the top and side views of
As noted in the Background section, where the curved sections of the semiconductor device 140 are singulated, mechanical stress points may develop at the beginning and/or end of a cut. Mechanical stresses may also develop along the curve, and/or at points of discontinuity, where two cuts come together at some non-zero angle. The reinforcing blocks 122 function to add strength and rigidity to the semiconductor device 140 at these mechanical stress points during the singulation process and in the completed semiconductor device 140. The material and thickness of the reinforcing blocks 122 may be selected depending on the degree of strength and rigidity desired in the semiconductor device 140. As shown in
It is known that controller semiconductor dies generate large amounts of heat, especially when operating at the higher frequencies of present-day memory devices. In embodiments, it is a further feature of the reinforcing blocks 122 that then enable the use of a lower strength, higher heat conduction material as the molding compound 134. In this way, the present technology also improves the ability of the semiconductor device 140 to dissipate heat.
In summary, in one example, the present technology relates to a semiconductor device configured to withstand cracking at one or more mechanical stress points, comprising: a substrate; one or more semiconductor dies mounted on the substrate; electrical interconnections electrically coupling the one or more semiconductor dies to the substrate; molding compound encapsulating the one or more semiconductor dies and electrical interconnections; and one or more reinforcing blocks, mounted on the substrate at the one or more mechanical stress points and severed during singulation of the semiconductor device, the one or more reinforcing blocks configured to add strength and rigidity to the semiconductor device.
In another example, the present technology relates to a semiconductor device singulated from a panel and configured to withstand cracking at one or more mechanical stress points generated during singulation, comprising: a substrate comprising a first major planar surface comprising contact pads configured to receive bond wires, and a second major planar surface, opposite the first major planar surface, the second major planar surface comprising contact fingers configured to couple the semiconductor device to a host device; components mounted on the first major planar surface of the substrate, the components comprising one or more semiconductor dies; bond wires electrically coupling the one or more semiconductor dies to the substrate the contact pads on the first major planar surface of the substrate; molding compound encapsulating the one or more semiconductor dies and bond wires; and one or more reinforcing blocks, the one or more reinforcing blocks mounted at one or more positions on one or more of the first and second major planar surfaces, each of the one or more positions determined to be a position of a mechanical stress point of the one or more mechanical stress points, and each of the one or more positions determined to be a position that does not to interfere with positions of the components, the contact pads and the contact fingers.
In a further example, the present technology relates to a semiconductor device singulated from a panel and configured to withstand cracking at one or more mechanical stress points generated during singulation, comprising: a substrate comprising a first major planar surface comprising contact pads configured to receive bond wires, and a second major planar surface, opposite the first major planar surface, the second major planar surface comprising contact fingers configured to couple the semiconductor device to a host device; components mounted on the first major planar surface of the substrate, the components comprising one or more semiconductor dies; bond wires electrically coupling the one or more semiconductor dies to the substrate the contact pads on the first major planar surface of the substrate; molding compound encapsulating the one or more semiconductor dies and bond wires; and means for strengthening the substrate at the one or more mechanical stress points, the means positioned on one or more of the first and second major planar surfaces that do not interfere with positions of the components, the contact pads and the contact fingers.
The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the technology be defined by the claims appended hereto.
