1. Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to providing through-package vias and back side coupling in an encapsulated device package by using pre-formed signal conduits and conductive balls.
2. Related Art
Semiconductor and other types of electronic devices are often encapsulated wholly or partly in resin to provide environmental protection and facilitate external connection to the devices. Subsequent to encapsulation, interconnect structures can be built up on one or both sides of the encapsulated devices to allow for package-on-package arrangements. For packages having electrical contacts on both top and bottom surfaces (e.g., a double-sided buildup), through-vias are often made to provide contacts between bottom side and top side interconnect structures. Traditionally, through package vias are made after encapsulation using a drilling and filling/metallization process that includes steps for via drill, via fill/metallization, polish and taping, and so on. Further, the formation of buildup layers on both sides of the package to create coupling pads involves many additional steps. This process of post-encapsulation via and interconnect formation introduces complexities to the manufacturing process that have a variety of manufacturing and reliability challenges. Further, costs associated with materials, processes and additional tooling to generate the through vias and interconnects can be high. In addition, through mold vias with double sided buildup allow for more complex system-in-package designs which may not be needed for simple package-on-package arrangements.
It is therefore desired to have a process for creating electrical couplings on a top side of a semiconductor package without adding significant cost or process steps. It is further desired that the through via creation process be simplified or eliminated along with many of the panelization steps relating to double-sided interconnect buildup. In addition, providing contacts on a top side of a semiconductor package without a complex buildup process will also allow for a thinner package for the device and, ultimately, a thinner package-on-package stack.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.
A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors or similar structures (e.g., gold studs) are attached to a major surface of a substrate that provides at least an electrical conduit (e.g., conductive pillars) from the ball conductor to an opposite major surface of the substrate. In addition, the substrate can provide a two-dimensional interconnect between ball conductors. The combination of ball conductors and substrate is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while the opposite major surface of the device package is back grinded (or the equivalent) to expose a portion of the ball conductors. The conductive pathway of ball conductors and signal conduits are then used as through vias, providing signal-bearing pathways between the bottom and top major surfaces of the package. The “pads” created by the back grinded ball conductors can be used to form a package-on-package structure by being coupled with contacts from another package. The ball conductor/substrate combination can be provided in a variety of geometries and materials, depending upon the nature of the application.
For convenience of explanation, and not intended to be limiting, the present invention is described for semiconductor devices, but persons of skill in the art will understand that the present invention applies to any type of electronic device that is substantially planar. Accordingly, such other types of devices including the non-limiting examples given below, are intended to be included in the terms “device,” “semiconductor device,” and “integrated circuit” whether singular or plural, and the terms “device,” “die,” and “chip” are intended to be substantially equivalent. Non-limiting examples of suitable devices are semiconductor integrated circuits, individual semiconductor devices, piezoelectric devices, solid-state filters, magnetic tunneling structures, integrated passive devices such as capacitors, resistors and inductors, and combinations and a raise of any and all of these types of devices and elements. Further, embodiments of the present invention do not depend upon the types of die or chips being used nor the materials of which they are constructed provided that such materials withstand the encapsulation process.
The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. In some examples, the signal conduit for passing a signal from one side of the device package to another is described as a conductive via or pillar. It should be recognized that such examples are not intended to limit embodiments of the present invention to electrically conductive materials, as the signal conduit can include additional materials such as waveguide for passing optical signals.
Signal conduits 120 can be made from a variety of electrically conductive materials including, for example, copper, gold, silver, aluminum, tungsten, and alloys thereof to include solder, doped materials (e.g., phosphorus, boron-doped polysilicon), superconducting materials and ceramics (e.g., copper oxide materials (such as HgBa2Ca2Cu3Ox, and Bi2Sr2Ca2Cu3O10 (BSCCO)), iron-based materials (such as SmFeAs(O,F)) and other metallic-based materials (such as Nb3Sn)), the choice of which is dependent upon the nature of the application. Signal conduits 120 could also be made of more than one type of material depending on the process to create the conduits, assembly and particular package structures.
Substrate 110 can be provided in a variety of shapes, depending upon the nature of the application and the package layout (e.g., strips and squares). Signal conduits 120 can be attached to the substrate through a molding process, pressing, deposition, or other methodologies appropriate to the nature of the materials of both the conduits and the substrate.
An insulating layer 510 can be deposited over the bottom surface of the encapsulated die, signal conduits and encapsulation molding material. Insulating layer 510 can be made from organic polymers, for example, in liquid or dry film and can include a wide range of other materials used for interlayer dielectrics as known in the art (e.g., silicon dioxide, silicon nitride, silicon oxynitride, or any combination of such layers providing electrical isolation). Insulating layer 510 can be patterned to expose bonding pads 180 and 185, as well as the ends of signal conduits 120.
A conductive layer 520 can then be deposited to provide an interconnect between the bonding pads and signal conduits. Conductive layer 520 can include materials such as metal, metal alloy, doped semiconductor, semi-metals, or combinations thereof as known in the art (e.g., amorphous silicon, doped polysilicon, aluminum, copper, silver, gold, tantalum, titanium, tungsten, or any metal alloy, nitride or silicide). Through the use of a conductive layer, any number of bonding pads can be interconnected in any combination to the same or other die and to the vias formed in insulating layer 510 by electrically conductive signal conduits. The interconnect illustrated in
An additional interconnect layer can be provided by forming additional insulating layers (e.g., insulating layer 530) and patterning those insulating layers with vias to receive additional conductive layers (e.g., conductive layer 540). The range of materials that can be used for subsequent insulating layers and conductive layers can include those listed for insulating layer 510 and conductive layer 520, and each type of layer can be the same or different materials as required by the nature of the application. Further, as illustrated, a set of conductive ball connectors can be provided by forming insulating layer 550, patterning that layer to expose pads formed in conductive layer 540, and forming and placing conductive balls 560 using standard techniques and materials.
An additional interconnect layer can be provided by forming additional insulating layers (e.g., insulating layer 660) and patterning those insulating layers to receive additional conductive layers (e.g., conductive layer 670). Further, as illustrated, a set of conductive ball connectors can be provided by forming insulating layer 680, patterning that layer to expose pads formed in conductive layer 670, and forming and placing conductive balls 690 using standard techniques and materials. The range of materials that can be used for the insulating layers and conductive layers of device 600 can include those listed for insulating layer 510 and conductive layer 520 of device 100, and each type of layer can be the same or different materials as required by the nature of the application.
Conductive balls 690 are in a configuration that matches one or more of the conductive surfaces (320) of device 100 formed from the grinded ball conductors 140. The conductive balls and the conductive surfaces can be affixed to one another using typical means (e.g., solder reflow and the like). An advantage of using a solder ball for a ball conductor 140 is that the solder ball will provide a solderable finish after the grinding step.
Embodiments of the present invention are not limited to the particular type of process illustrated in the figures. As shown, embodiments of the present invention are used in a fan-out wafer level package, (e.g. redistributed chip packaging process (RCP)), but embodiments of the present invention are not limited to fan-out wafer level package. It should be realized, however, that steps discussed above may require modification for different types of processes.
It should further be noted that embodiments of the present invention do not depend on the exact nature of the embedded component (e.g., 170 and 610). The component can be, for example, integrated circuits, individual devices, filters, magnetostrictive devices, electro-optical devices, electro-acoustic devices, integrated passive devices such as resistors, capacitors and inductors, or other types of elements and combinations thereof, and can be formed of any materials able to withstand the encapsulation process. Non-limiting examples of materials are various organic and inorganic semiconductors, type IV, III-V and II-VI materials, glasses, ceramics, metals, semi-metals, inter-metallics and the like.
Embodiments of the present invention avoid a need for processing steps related to forming an interconnect on the “back side” or top side (as illustrated) of packaged devices. In addition, incorporation of ball conductors and signal conduits that provide a signal path from one major surface of the packaged device to the other save the need for post-encapsulation via drilling and filling steps. Incorporation of the ball conductors and substrate occurs at the same stage in processing as other pick and place operations, or before pick and place. Buildup on the top side (as illustrated) is not needed as the ground surface provides a connection configuration that matches the top package for assembly. Further, the process provides consistent quality signal paths through the depth of the package that do not depend upon a quality of a fill operation.
By now it should be appreciated that a method for packaging an electronic device assembly has been provided that includes: providing an interconnect assembly including a substrate, a plurality of signal conduits embedded in the substrate and extending to a first major surface of the substrate, a substrate interconnect formed on the substrate and electrically coupling two or more of the plurality of signal conduits, and one or more conductive balls electrically coupled to the substrate interconnect at a second major surface of the interconnect assembly; placing the interconnect assembly in a first area for the electronic device assembly; placing a first electronic device in a second area for the electronic device assembly; forming an encapsulant over and around sides of the first electronic device and over and around sides of the interconnect assembly; and, exposing a portion of the one or more conductive balls where the exposing removes a portion of the encapsulant and the exposed portion of the one or more conductive balls provide electrical contacts to the interconnect assembly on a first major surface of the electronic device assembly.
One aspect of the above embodiment further includes exposing an end of the one or more signal conduits at a second major surface of the electronic device assembly, and forming a package interconnect on the second major surface of the electronic device assembly. The exposing is performed subsequent to forming the encapsulant. The package interconnect is electrically coupled to the exposed ends of the one or more signal conduits and electrical contacts of the first electronic device. In a further aspect, the package interconnect is electrically coupled to one or more of the conductive balls via one or more of the signal conduits and the substrate interconnect.
Another aspect of the above embodiment further includes providing an adhesive layer disposed on a carrier. Placing the interconnect assembly includes placing the interconnect assembly on the adhesive layer with the first major surface of the interconnect assembly in contact with the adhesive layer, and placing the first electronic device includes placing the first electronic device active side down on the adhesive layer. In a further aspect, exposing the end of the one or more signal conduits includes removing the adhesive layer from the encapsulated electronic device assembly.
In another aspect of the above embodiment, exposing the portion of the one or more conductive balls includes grinding the encapsulant from the electronic device assembly to a predetermined depth. In a further aspect the predetermined depth includes a depth resulting in a desired diameter of the exposed portion of a conductive ball of the one or more conductive balls.
In another aspect of the above embodiment, a conductive ball is a solder ball. Another aspect of the above embodiment further includes forming a package-on-package assembly. Forming the package-on-package assembly includes placing a second electronic device assembly in contact with the first major surface of the electronic device assembly, and forming an electrical contact between one or more contacts of the second electronic device assembly with one or more corresponding exposed portions of the one or more conductive balls.
In another embodiment a packaged device assembly has been provided that includes an electronic device, and interconnect assembly, encapsulant over and around the electronic device and over and around the interconnect assembly which forms an encapsulated region of the packaged device assembly, and a first interconnect structure formed on the bottom surface of the packaged device assembly. The interconnect assembly includes a substrate, a plurality of signal conduits embedded in the substrate and extending to a first major surface of the substrate, a substrate interconnect formed on the substrate and electrically coupling two or more of the plurality of signal conduits, and one or more conductive balls electrically coupled to the substrate interconnect and a second major surface of the interconnect assembly. A portion of the encapsulant is removed to expose a portion of the one or more conductive balls on a top surface of the packaged device assembly. The exposed portions of the conductive balls are electrically coupled to the first interconnect structure by one or more of the substrate interconnect and a signal conduit of the one or more signal conduits.
One aspect of the above embodiment provides for a conductive ball to be a solder ball. In another aspect, the exposed portion of the one or more conductive balls is an area sufficient to provide a coupling point for a second package device assembly attached to the top of the package device assembly. In still another aspect, the packaged device assembly further includes a second package device assembly including one or more coupling points on the major surface of the second device assembly. The one or more coupling points are coupled to the exposed portion of the one or more conductive balls on the top surface of the package device assembly and the coupled package device assembly and the second package device assembly form a package-on-package assembly.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details are not explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.