Patent Application
20250174516
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2023-201310, filed on Nov. 29, 2023, the entire contents of which are incorporated herein by reference.
The embodiment discussed herein relates to a semiconductor device.
There are proposed semiconductor devices in which a semiconductor module is disposed on a cooling module via a joining member to dissipate heat (see, for example, Japanese Laid-open Patent Publication No. 2023-103785). The joining member contains, for example, an organic resin or solder as a major component (see, for example, Japanese Laid-open Patent Publications No. 2018-046166 and No. 2021-111765).
According to an aspect, there is provided a semiconductor device including a semiconductor module including a metal plate at a back surface thereof, the metal plate having a bottom surface; a cooling module including a cooling surface on which the bottom surface of the metal plate is placed; and an adhesion member provided between the bottom surface of the metal plate and the cooling surface, the adhesion member containing electrically conductive fillers that connect the bottom surface and the cooling surface.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
An embodiment will be described below with reference to the accompanying drawings. In the following, the terms “front surface” and “top surface” refer to the X-Y plane facing upward (the +Z direction) in a semiconductor device of the drawings. Similarly, the term “upper” refers to the upward direction (the +Z direction) of the illustrated semiconductor device. On the other hand, the terms “back surface” and “bottom surface” refer to the X-Y plane facing downward (the −Z direction) in the illustrated semiconductor device. Similarly, the term “lower” refers to the downward direction (the −Z direction) of 41 the illustrated semiconductor device. These terms have the same orientational relationships in all drawings if needed. “High” and “upper” in position refer to upper positions (the +Z direction) in the illustrated semiconductor device. On the other hand, “low” and “lower” in position refer to lower positions (the −Z direction) in the illustrated semiconductor device. The terms “front surface”, “top surface”, “upper”, “back surface”, “bottom surface”, “lower”, and “lateral surface” are simply expedient expressions used to specify relative positional relationships, and are not intended to limit the technical ideas of the embodiment described herein. For example, the terms “upper” and “lower” do not necessarily imply the vertical directions to the ground surface. That is, the “upper” and “lower” directions are not defined in relation to the direction of the gravitational force. In addition, the term “major component” in the following refers to a constituent having a concentration equal to 80 vol % or higher. The phrase “substantially the same” refers to where two or more things being compared have a difference of no more than ±10%. In addition, the terms “perpendicular”, “orthogonal”, and “parallel” may also include substantially perpendicular, substantially orthogonal, and substantially parallel, as appropriate, which may include a margin of error of ±10° or less.
A semiconductor device 1 according to an embodiment is described next with reference to
The semiconductor device 1 includes a semiconductor module 2, the cooling module 3, and the adhesion member 4 for fixing the semiconductor module 2 and the cooling module 3. Note that the semiconductor device 1 may include other needed components in addition to the aforementioned ones.
The semiconductor module 2 includes semiconductor chips 10a, 10b, 10d, and 10e, an insulated circuit board 20, a printed circuit board 30, and a sealing member 35 for sealing the foregoing components. The semiconductor chips 10a, 10b, 10d, and 10e may be power metal-oxide-semiconductor field-effect transistors (power MOSFETs) whose major component is silicon carbide. In each power MOSFET, a body diode may function as a free wheeling diode (FWD). The semiconductor chips 10a, 10b, 10d, and 10e each have, for example, an input electrode (drain electrode) functioning as a main electrode on the back surface, and an output electrode (source electrode) functioning as a main electrode and control electrodes (gate electrode) on the front surface. The control electrodes may be provided at the center of one side of the front surface of the individual semiconductor chips 10a, 10b, 10d, and 10e, or may be provided offset from the center along the side.
Alternatively, the semiconductor chips 10a, 10b, 10d, and 10e may include a switching element containing silicon as a major component. The switching element is, for example, a reverse-conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT is a semiconductor element having a single-chip structure with a circuit where an IGBT is connected antiparallel with an FWD.
Each of the above semiconductor chips 10a, 10b, 10d, and 10e has an input electrode (collector electrode) functioning as a main electrode on the back surface, and an output electrode (emitter electrode) functioning as a main electrode and control electrodes (gate electrode) on the front surface. The control electrodes may be provided at the center of one side of the front surface of each of the semiconductor chips 10a, 10b, 10d, and 10e, or may be provided offset from the center along the side, as in the case of the power MOSFETs described above.
Alternatively, the semiconductor chips 10a, 10b, 10d, and 10e may, for example, be semiconductor chips containing silicon as a major component and each including a switching element or a diode element. Specifically, the semiconductor chips 10a and 10d may be switching elements while the semiconductor chips 10b and 10e may be diode elements. The switching elements are, for example, power MOSFETS or IGBTs. Each semiconductor chip including a switching element has, for example, an input electrode (drain electrode in the case of a power MOSFET; and collector electrode in the case of an IGBT) functioning as a main electrode on the back surface, and a gate electrode functioning as control electrodes and an output electrode (source electrode in the case of a power MOSFET; and emitter electrode in the case of an IGBT) functioning as a main electrode on the front surface. As for the diode elements, for example, Schottky barrier diodes (SBD) or P-intrinsic-N (PiN) diodes are used as FWDs. Each semiconductor chip including a diode element has an output electrode (cathode electrode) functioning as a main electrode on the back surface, and an input electrode (anode electrode) functioning as a main electrode on the front surface.
The semiconductor chips 10a and 10b and the semiconductor chips 10d and 10e described above are individually bonded to conductive patterns 23a and 23b (to be described later), respectively, with solder 12. The solder 12 is made up of solder components. The solder components constituting the solder 12 include lead-free solder containing a predetermined alloy as a major component. The predetermined alloy includes tin. Such an alloy is, for example, at least one of the followings: a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, and a tin-antimony alloy. Further, the solder components may include an additive, such as nickel, germanium, cobalt, or silicon. Thus, the solder components are, for example, made of tin and at least one of silver, zinc, copper, bismuth, indium, and antimony. Further, the solder components may include at least one of nickel, germanium, cobalt, and silicon, for example. The thickness of the solder 12 is 50 μm or more and 300 μm or less. Note that the solder components of solder 32 described below are the same as those of the solder 12. Sintered compacts may be used instead of the solder 12. A sintered material of the sintered compacts used in bonding here is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.
The insulated circuit board 20 includes an insulating plate 21, the metal plate 22, and the conductive patterns 23a and 23b. The insulating plate 21 and the metal plate 22 have a rectangular shape in plan view. In addition, the insulating plate 21 and the metal plate 22 may have R- or C-chamfered corners.
The insulating plate 21 is made of, for example, The resin may be a material with low thermal a resin. resistance and high insulation capability. For example, a thermosetting resin exhibits such properties. The thermosetting resin may contain fillers. The thermal resistance of the insulating plate 21 may be further reduced by controlling the material and content of the fillers. Further, according to the fillers, the linear expansion coefficient of the insulating plate 21 and those of the metal plate 22 and the conductive patterns 23a and 23b described later may be made approximately equal. Reducing the difference in linear expansion coefficients suppresses the occurrence of warpage in the insulated circuit board 20 due to the difference in the linear expansion coefficients even if the insulated circuit board 20 is subject to thermal changes. In this case, the difference in linear expansion coefficients may be within a margin of error of 10% or more and 50% or less.
Such a thermosetting resin is, for example, at least one of the following: epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenol resin, melamine resin, silicone resin, maleimide resin, acrylic resin, and polyamide resin. The fillers are made of at least one of oxide and nitride. Example of the oxide include silicon oxide and aluminum oxide. Examples of the nitride include silicon nitride, aluminum nitride, and boron nitride. Furthermore, hexagonal boron nitride may be used as the fillers. The thickness of the insulating plate 21 depends on the rated voltage of the semiconductor device 1. That is, the thickness of the insulating plate 21 needs to be increased as the rated voltage of the semiconductor device 1 is higher. On the other hand, the thickness of the insulating plate 21 needs to be as thin as possible from the viewpoint of lowering thermal resistance.
The insulating plate 21 may be a ceramic substrate instead of a resin plate. The ceramic substrate is made of ceramic with excellent thermal conductivity. The ceramic here is made of a material containing, for example, aluminum oxide, aluminum nitride, or silicon nitride as a major component. As the insulated circuit board 20 including the insulating plate 21 having such a composition, for example, a direct copper bonding (DCB) board or an active metal brazed (AMB) board may be used.
Note that, according to this embodiment, the insulating plate 21 is made of resin, and the difference between the linear expansion coefficient of the insulating plate 21 and the linear expansion coefficients of the metal plate 22 and the conductive patterns 23a and 23b is designed to be small.
The metal plate 22 is made of a metal having excellent thermal conductivity. The material is, for example, copper, aluminum, or an alloy made of at least one of these. Here, the material contains copper. Plating may be applied to coat the surfaces of the metal plate 22 in order to provide improved corrosion resistance. In this case, a material used for plating contains nickel. Such a plating material is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. Note that the bottom surface 22a of the metal plate 22 is also the bottom surface of the insulated circuit board 20. The bottom surface 22a of the metal plate 22 is exposed from a bottom surface 35a of the sealing member 35 to be described later. In this case, the bottom surface 22a of the metal plate 22 may protrude outward from the bottom surface 35a of the sealing member 35, or may be flush with the bottom surface 35a of the sealing member 35. According to this embodiment, the bottom surface 22a of the metal plate 22 is flush with the bottom surface 35a of the sealing member 35. The thickness of the metal plate 22 may be three times or more and fifteen times or less than the thickness of the insulating plate 21.
On the conductive patterns 23a and 23b, the semiconductor chips 10a and 10b and the semiconductor chips 10d and 10e, respectively, are disposed. The conductive patterns 23a and 23b are formed all over the insulating plate 21, except for its rims. In plan view, edges of the conductive patterns 23a and 23b, facing the outer periphery of the insulating plate 21, may coincide with edges of the metal plate 22, facing the outer periphery of the insulating plate 21. In this case, in the insulated circuit board 20, stress balance with the metal plate 22 placed on the back surface of the insulating plate 21 is maintained. This reduces damage to the insulating plate 21, such as excessive warpage and crack formation.
The conductive patterns 23a and 23b are made of a material with excellent electrical conductivity. The material is, for example, copper, aluminum, or an alloy made of at least one of these. Plating may be applied to the conductive patterns 23a and 23b using a material with excellent corrosion resistance. In this case, the material used for plating is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The conductive patterns 23a and 23b on the insulating plate 21 are created by forming a metal plate on the front surface of the insulating plate 21 and performing etching or the like on the metal plate. Alternatively, the conductive patterns 23a and 23b preliminarily cut out of a metal plate are bonded to the front surface of the insulating plate 21. Note that the conductive patterns 23a and 23b included in the semiconductor device 1 of the embodiment are merely an example, and appropriate changes may be made to the number of conductive patterns, their shape, size and so on, on an as-needed basis.
The printed circuit board 30 includes an insulating layer and multiple upper circuit pattern layers formed on the front surface of the insulating layer. The printed circuit board 30 may also include multiple lower circuit pattern layers on the back surface of the insulating layer. The printed circuit board 30 with such a configuration opposes the front surface of the insulated circuit board 20 in plan view. In addition, the printed circuit board 30 is electrically connected to the output electrodes, input electrodes, and control electrodes of the semiconductor chips 10a, 10b, 10d, and 10e. Note that conductive posts 31a, 31b, 31d, and 31e depicted in
For example, the printed circuit board 30 is electrically connected to the output electrodes on the front surfaces of the semiconductor chips 10a and 10b through the conductive posts 31a and 31b, and is also electrically connected to the output electrodes on the front surfaces of the semiconductor chips 10d and 10e through the conductive posts 31d and 31e.
The printed circuit board 30 is electrically connected to the input electrodes on the back surfaces of the semiconductor chips 10a and 10b via a conductive post 31c and the conductive pattern 23a, and is also electrically connected to the input electrodes on the back surfaces of the semiconductor chips 10d and 10e via a conductive post 31f and the conductive pattern 23b.
The printed circuit board 30 is electrically connected to the control electrodes of the semiconductor chips 10a and 10b via a conductive post (not illustrated), and is also electrically connected to the control electrodes of the semiconductor chips 10d and 10e via a conductive post (not illustrated).
The sealing member 35 seals the insulated circuit board 20, the semiconductor chips 10a, 10b, 10d, and 10e, and the printed circuit board 30 as a whole. Various terminals, for example, for input, output, and control, may protrude from the top surface of the sealing member 35 if needed. The sealing member 35 may be, for example, a rectangular parallelepiped, and includes the flat bottom surface 35a. The bottom surface 22a of the metal plate 22 of the insulated circuit board 20 is exposed from the bottom surface 35a of the sealing member 35.
The foregoing sealing member 35 may be a thermosetting resin containing fillers. That is, the sealing member 35 is made of insulating fillers and a resin (thermosetting resin) to be described later as major components. In this case, the thermosetting resin is, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The fillers may be made of ceramic having insulting properties and high thermal conductivity as a major component. Such fillers are, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. The content of the fillers is 10 volume % or more and 70 volume % or less of the entire sealing member 35.
The semiconductor module 2 having such a configuration is merely an example. The semiconductor module 2 may be formed, for example, in the following order: disposing a DCB board and semiconductor chips on a heat dissipation base in order; wiring the DBC board and the semiconductor chips; disposing a case on the heat dissipation base such as to surround the DBC board and the semiconductor chips; and sealing the inside of the case with a sealing member. In this case, the bottom surface of the heat dissipation base corresponds to the bottom surface 22a of the metal plate 22.
The cooling module 3 has the cooling surface 3a on its top surface, on which the semiconductor module 2 is placed. The cooling surface 3a is flat and wider than the back surface of the semiconductor module 2. The cooling module 3 may be, for example, a heat dissipation base having heat dissipation fins, or a cooling device with a refrigerant circulating therein.
The adhesion member 4 is provided between the bottom surface 22a of the metal plate 22 of the semiconductor module 2 and the cooling surface 3a of the cooling module 3 to bond these two surfaces. Herewith, the adhesion member 4 fixes the semiconductor module 2 and the cooling module 3 and also thermally connects the metal plate 22 and the cooling module 3. The adhesion member 4 simply needs to be in contact with at least the entire bottom surface 22a of the metal plate 22 of the semiconductor module 2. The adhesion member 4 illustrated in
The foregoing adhesion member 4 is an organic resin adhesive containing thermosetting resin as a major component and includes the electrically conductive fillers 4a (see
The fillers 4a of the adhesion member 4 may contain a conductive metal. The metal is, for example, silver, copper, gold, nickel, chromium, aluminum, or an alloy containing at least one of these. The fillers 4a may be, for example, spherical or flake shaped. The amount of the fillers 4a filled in the adhesion member 4 is 80% by weight or more. Note that the fillers 4a may mainly contain such a metal, and may contain inorganic fillers other than the metal. Such inorganic fillers are, for example, ceramic with high insulation and high thermal conductivity. The ceramic is, for example, at least one of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride.
Within the adhesion member 4, the fillers 4a connect the bottom surface 22a of the metal plate 22 and the cooling surface 3a of the cooling module 3 together, as depicted in
The thermal conductivity of the adhesion member 4 containing the foregoing fillers 4a may be 10 W/mK or more. The material and amount of the fillers 4a may be selected so as to obtain the thermal conductivity. The adhesion member 4 may have lower elastic modulus than the solder 12 and 32 and the sintered material, for example, 10 GPa or less. The thickness of the adhesion member 4 may be 50 μm or more and 150 μm or less. On the other hand, the adhesion member 4 needs to be as thin as possible to offer low thermal resistivity (i.e., high thermal conductivity). However, if the thickness is less than 50 μm, the stress of the adhesion member 4 becomes large. Also, with the thickness being less than 50 μm, paths for volatile gas generated in the adhesion member 4 to escape are reduced, making it difficult to release the gas.
Here, as a reference example, a case will be described in which a joining member made of a different material is used in place of the adhesion member 4 of the semiconductor device 1. In the following description, a thermal interface material (hereinafter, TIM) is referred to as the joining member, and a case of using a TIM is described. Examples of the TIM include various materials, such as thermal conductive grease, an elastomer sheet, room temperature vulcanization (RTV) rubber, gel, and a phase change material.
When the joining member of the reference example is thermal conductive grease, which is a common TIM, the thermal conductivity is less than 5 W/mK. With such a joining member, there is a limit to reduction of thermal resistance even if the thickness of the joining member is further reduced.
In the semiconductor device 1 including the joining member of the reference example, when the cooling surface 3a of the cooling module 3 is deformed due to, for example, changes in temperature, the joining member between the bottom surface 22a of the metal plate 22 and the cooling surface 3a is likely to flow out from therebetween. When such a pump-out phenomenon occurs, the thermal conductivity from the semiconductor module 2 to the cooling module 3 decreases, thus leading to a decrease in the performance of the semiconductor module 2.
In addition, common TIMs provide poor adhesion. Using such a TIM as the joining member needs the use of a different structure and parts to fix the semiconductor module 2 and the cooling module 3. This makes the semiconductor device 1 a complicated structure and therefore increases manufacturing costs.
On the other hand, in the case of using an adhesive as the joining member, a common adhesive has insulating properties and a thermal conductivity of about 5 W/mK. Therefore, even if the common adhesive may be able to fix the semiconductor module 2 and the cooling module 3, it is difficult to reduce the thermal resistance, thus reducing the heat dissipation performance of the semiconductor device 1.
It is also possible to use solder or a sintered material as the joining member. However, solder and sintered materials have high joining temperatures. Therefore, when heat is applied to join the semiconductor module 2 and the cooling module 3 with such a joining member, the solder or sintered material in the semiconductor module 2 may melt. Furthermore, solder and sintered materials exhibit high elastic moduli. Therefore, in the semiconductor device 1 including the semiconductor module 2 and the cooling module 3 joined with such a joining member, stress is generated in the joining member during heat cycles, which leads to decreased reliability.
The semiconductor device 1 of the above embodiment includes the semiconductor module 2, the cooling module 3, and the adhesion member 4. The semiconductor module 2 includes the metal plate 22 having the bottom surface 22a on the back surface side. The cooling module 3 includes the cooling surface 3a on which the bottom surface 22a of the metal plate 22 is disposed. The adhesion member 4 is provided between the bottom surface 22a of the metal plate 22 and the cooling surface 3a, and contains the electrically conductive fillers 4a, which connect the bottom surface 22a and the cooling surface 3a to each other. In the foregoing semiconductor device 1, the semiconductor module 2 and the cooling module 3 are readily fixed only using the adhesion member 4 without a complicated structure. Further, the adhesion member 4 reduces the thermal resistivity between the semiconductor module 2 and the cooling module 3, thereby improving the heat dissipation performance of the semiconductor device 1.
In addition, because the adhesion member 4 has a low elastic modulus, even if the semiconductor device 1 undergoes heat cycles, stress generated in the adhesion member 4 is mitigated. Further, in the case where the insulating plate 21 of the insulated circuit board 20 is made of resin, the occurrence of warpage in the insulated circuit board 20 is suppressed even if the semiconductor device 1 undergoes heat cycles. Therefore, stress generated in the adhesion member 4 is further reduced. This makes it possible to reduce the thickness of the adhesion member 4 and thus render the adhesion member 4 low thermal resistance.
Next described is a method for manufacturing the foregoing semiconductor device 1, with reference to
Next, a semiconductor module assembly step is performed to assemble the semiconductor module 2 (step S2). In the semiconductor module assembly step, the following steps are further performed. First, the semiconductor chips 10a, 10b, 10d, and 10e are bonded to the insulated circuit board 20 (step S2a). Step S2a is described with reference to
The semiconductor chips 10a, 10b, 10d, and 10e are bonded to the conductive patterns 23a and 23b of the insulated circuit board 20 via the solder 12. Conventional solder bonding is used here. In this manner, a structure is obtained in which the semiconductor chips 10a and 10b are joined to the conductive pattern 23a of the insulated circuit board 20 via the solder 12 while the semiconductor chips 10d and 10e are bonded to the conductive pattern 23b via the solder 12, as depicted in
Then, the conductive posts 31a, 31b, 31c, 31d, 31e, and 31f of the printed circuit board 30 are individually bonded to the semiconductor chips 10a and 10b, the conductive pattern 23a of the insulated circuit board 20, the semiconductor chips 10d and 10e, and the conductive pattern 23b of the insulated circuit board 20 (step S2b). Step S2b is described with reference to
The printed circuit board 30 is in advance provided with the conductive posts 31a, 31b, 31c, 31d, 31e, and 31f. The foregoing conductive posts 31a, 31b, 31c, 31d, 31e, and 31f are bonded by conventional soldering. In this manner, a structure is obtained in which the printed circuit board 30 is attached to the insulated circuit board 20, to which the semiconductor chips 10a, 10b, 10d, and 10e have been bonded, as depicted in
At the end of step S2, a sealing step is performed using the sealing member 35 (step (S2c). Step S2c is described with reference to
The structure obtained in step S2b is set, for example, in a predetermined mold. The sealing member 35 is filled into the mold to seal the structure. By removing the mold, the semiconductor module 2 depicted in
Next, an application step is performed to apply the adhesion member 4 (step S3). The adhesion member 4 may be applied to either the back surface of the semiconductor module 2 or the cooling surface 3a of the cooling module 3. For example, the application of the adhesion member 4 may be performed as follows. First, a mask with a predetermined opening corresponding to an application area is set on the application surface. The adhesion member 4 is applied into the opening with a squeegee. The mask is then removed, and thus the adhesion member 4 is transferred to the application area. According to the embodiment, the adhesion member 4 corresponding to the size of the back surface of the semiconductor module 2 is applied to the placement area of the semiconductor module 2 on the cooling surface 3a of the cooling module 3. The adhesion member 4 may be applied with a dispenser.
Next, a setting step is performed in which the back surface of the semiconductor module 2 is set on the cooling surface 3a of the cooling module 3 via the adhesion member 4 (step S4). Here, the cooling module 3 is fixed to a predetermined fixing base, and the back surface of the semiconductor module 2 is placed onto the adhesion member 4 transferred to the cooling module 3.
Next, a heating step is performed to heat the adhesion member 4 (step S5). The heating step is described with reference to
Alternatively, during heating described above, pressure may be applied such that the back surface of the semiconductor module 2 and the cooling surface 3a of the cooling module 3 come close to each other, as depicted in
In this case, while the adhesion member 4 is heated, pressure is applied so that the bottom surface 22a of the metal plate 22 comes closer to the cooling surface 3a, whereby the fillers 4a contained in the adhesion member 4 are compressed together. Then, the fillers 4a may be partially sintered, as depicted in
According to an aspect, it is possible to readily fix the semiconductor module and the cooling module and also improve heat dissipation.
All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one embodiment of the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-201310 | Nov 2023 | JP | national |
