Patent Application
20210234029
The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2020-011462 filed on Jan. 28, 2020, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
The disclosure relates to a semiconductor device.
As a semiconductor device using a nitride semiconductor, a large number of reports have been made on field effect transistors, particularly high electron mobility transistors (HEMT) As such high HEMTs having a nitride semiconductor, HEMTs having a GaN layer as a channel layer and an AlGaN layer as a barrier layer are known. In such GaN-based HEMTs, the AlGaN layer is strained due to the difference between the lattice constant for AlGaN and GaN. This strain is followed by piezoelectric polarization, and a high concentration of a two-dimensional electron gas (2DEG) is then generated near a top face of the GaN layer beneath the AlGaN layer. This results in a high power output.
In HEMT, the concentration of 2DEG may preferably be changed between the source and drain electrodes. For example, the concentration of 2DEG may be preferably higher between the gate and source electrodes than between the gate and drain electrodes in order to maintain both reduction in on-resistance and enhancement in drain breakdown voltage. It is often preferable that there be very little 2DEG present beneath the gate electrode in order to achieve a normally-off operation/
Related art technologies propose a semiconductor device having a stress film on a barrier layer, or a semiconductor device having a p-type GaN layer or an InGaN layer beneath a gate electrode in order to modulate the concentration of 2DEG.
According to one aspect of the present disclosure, a semiconductor device includes an electron transit layer; an electron supply layer disposed on or above the electron transit layer; and a capping layer disposed on or above the electron supply layer, wherein a first lattice constant of the electron transit layer is greater than a second lattice constant of the electron supply layer in a direction parallel to a main surface of the electron transit layer.
The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
In the related art configurations of the semiconductor devices, modulation of the concentration of two-dimensional electron gas (2DEG) may appear to affect other properties.
Thus, according to an aspect of the present disclosure, a semiconductor device capable of easily modulating the concentration of a two-dimensional electron gas is provided.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the present specification and the drawings, duplicated descriptions of components having substantially the same functional structures may be omitted by providing the same reference numerals.
A first embodiment will be described. The first embodiment relates to a semiconductor device having a high-electron-mobility transistor (HEMT)
In the semiconductor device 100 according to the first embodiment, a nitride semiconductor stacked structure 107 is, as illustrated in
The substrate 101 is, for example, a semi-insulating SiC substrate. The nucleation layer 102 is, for example, an AlN layer with a thickness of 5 nm to 150 nm. The channel layer 103 is, for example, a GaN layer with a thickness of 1 μm to 5 μm. The spacer layer 104 is, for example, an Alx1Ga1-x1N layer (0.40≤x1≤1.00) with a thickness of 0.5 nm to 3 nm. That is, the spacer layer 104 is an AlGaN layer having a thickness of, for example, 0.5 nm to 3 nm and an Al composition x1 of greater than or equal to 0.40 and less than or equal to 1.00. The barrier layer 105 is, for example, an Alx2Ga1-x2N layer (0.30≤x2≤0.70) with a thickness of 4 nm to 8 nm. That is, the barrier layer 105 is an AlGaN layer having a thickness of, for example, 4 nm to 8 nm and an Al composition x2 of greater than or equal to 0.30 and less than or equal to 0.70. The capping layer 106 is, for example, a GaN layer with a thickness of 8 nm to 12 nm.
The channel layer 103, the spacer layer 104, the barrier layer 105, and the capping layer 106 each have an a-axis in a direction parallel to a main surface of the channel layer 103, and also have a c axis in a direction perpendicular to the main surface of the channel layer 103. In the absence of external forces and strain, a lattice constant aGaN in an a-axis direction of GaN is 3.189 Å, the lattice constant aAlN in the a-axis direction of AlN is 3.112 Å, and a lattice constant aAlGaN in the AlyGa1-yN with the Al composition y is expressed by the following equation (1).
a
AlGaN
=a
GaN−(aGaN−aAlN)×y (1)
In the a-axis direction, a lattice constant a103 of the channel layer 103 is the lattice constant aGaN.
The spacer layer 104 is lattice-matched to the channel layer 103. The spacer layer 104 is strained in a tensile direction due to the effect of the channel layer 103. In the a-axis direction, a lattice constant a104 of the spacer layer 104 is equivalent to the lattice constant a103 of the channel layer 103.
The barrier layer 105 is lattice-matched to neither the spacer layer 104 nor the channel layer 103. The barrier layer 105 is strained in the tensile direction due to the effects of the channel layer 103 and the spacer layer 104, but the tensile strain of the barrier layer 105 is less than the tensile strain of the spacer layer 104. That is, the tensile strain of the barrier layer 105 is partially relaxed. The percentage of the tensile strain relaxation is, for example, approximately 10% to 30%. In the a-axis direction, a lattice constant a105 of the barrier layer 105 is less than the lattice constant a104 of the spacer layer 104, and is less than the lattice constant a103 of the channel layer 103. Also, the lattice constant a105 of the barrier layer 105 is greater than the lattice constant aAlGaN obtained by substituting x2 for y in the above equation (1) Accordingly, the lattice constant a105 of the barrier layer 105 is greater than the lattice constant aAlGaN and less than the lattice constant aGaN. For example, a main surface of the barrier layer 105 may include crystal defects such as dislocations, with the main surface of the barrier layer 105 being oriented toward the channel layer 103. Note that when percentage of the relaxation is 0%, the lattice constant a105 of the barrier layer 105 matches the lattice constant aGaN, and when percentage of the relaxation is 100%, the lattice constant a105 of the barrier layer 105 matches the lattice constant aAlGaN.
The capping layer 106 is lattice-matched to the barrier layer 105. The capping layer 106 is strained in a compression direction. In the a-axis direction, the lattice constant a106 of the capping layer 106 is equivalent to the lattice constant a105 of the barrier layer 105.
Thus, in the a-axis direction (in a direction parallel to the main surface of the channel layer 103), the lattice constant a103 of the channel layer 103 is greater than the lattice constant a105 of the barrier layer 105.
An element separation region is formed in a nitride semiconductor stacked structure 107. The element separation region defines an element region. Within the element region, an opening 106s for the source and an opening 106d for the drain are defined in the capping layer 106. Then, a source electrode 108 is formed in the opening 106s, and a drain electrode 109 is formed in the opening 106d. An insulating film 110 that covers the source and drain electrodes 108 and 109 is formed over the capping layer 106. An opening 110g is defined in the insulating film 110 between the source electrode 108 and the drain electrode 109 in a plan view, and a gate electrode 111 is formed on the insulating film 110 through the opening 110g so as to be in contact with the capping layer 106.
The source and drain electrodes 108 and 109 each include, for example, a 10 nm to 50 nm thick Ta film and a 100 nm to 500 nm thick Al film on the Ta film. The source and drain electrodes 108 and 109 are each in ohmic contact with the nitride semiconductor stacked structure 107. The gate electrode 111 includes, for example, a 10 nm to 50 nm thick Ni film and a 300 nm to 500 nm thick Au film on the Ni film. The gate electrode 111 is in Schottky contact with the nitride semiconductor stacked structure 107. The insulating film 110 includes, for example, a nitride layer having Si, Al, Hf, Zr, Ti, Ta or W, and the insulating film 110 preferably includes a Si nitride (SiN) layer. The thickness of the insulating film 110 may be, for example, 2 nm to 500 nm, and is preferably approximately 100 nm.
Next, working effects of the barrier layer 105, the capping layer 106, and the insulating film 110 will be described with reference to three types of stacked structures illustrated in
A first stacked structure illustrated in
In the first stacked structure (
The third stacked structure (
Thus, the concentration of the 2DEG 150 may be adjusted only with or without the addition of the insulating film 110 to the first stacked structure, thereby adjusting the sheet resistance.
In the semiconductor device 100 according to the first embodiment, an insulating film 110 is formed on the capping layer 106, an opening 110g is defined in the insulating film 110, and the gate electrode 111 contacts the capping layer 106 through the opening 110g. Thus, 2DEG 150 is present at high concentration near the top face of the channel layer 103, except beneath the opening 110g. The concentration of 2DEG 150 is extremely low beneath the opening 110g. Thus, the concentration of 2DEG 150 may be easily modulated by the semiconductor device 100. In addition, modulation of the concentration of the 2DEG 150 may achieve a normally-off operation while keeping the on-resistance low.
As illustrated in
Next, a method for fabricating the semiconductor device 100 according to the first embodiment will be described.
First, as illustrated in
Hereinafter, growth conditions of the barrier layer 105 will be described in detail. During the growth of the barrier layer 105, a N2 gas is used as a carrier gas, and a lower temperature of 700° C. to 800° C. is used as the growth temperature. By adopting such conditions, a barrier layer 105 that is not lattice-matched to the spacer layer 104 and the channel layer 103 may be grown. For example, the percentage of the tensile strain relaxation of the barrier layer 105 may be approximately 10% to 30%. This may be because the use of the low-reducing N2 gas as a carrier gas causes dislocation under the low temperatures, and the strain is relaxed by dislocation. As in the first stacked structure (see
After formation of the nitride semiconductor stacked structure 107, an element separation region, defining an element region, is formed in the nitride semiconductor stacked structure 107. In the formation of the element separation region, for example, a photoresist pattern that exposes regions intended to define an element separation region is formed on the nitride semiconductor stacked structure 107, and then ion implantation, such as argon (Ar) ion implantation, is performed using this photoresist pattern as a mask. Dry etching may be performed with a chlorine-based gas using this photoresist pattern as an etching mask.
Thereafter, as illustrated in
Subsequently, as illustrated in
Then, as illustrated in
Subsequently, as illustrated in
Then, as illustrated in
The semiconductor device 100 according to the first embodiment may be fabricated in this manner.
The barrier layer 105 may be in direct contact with channel layer 103 without the formation of the spacer layer 104. The same applies to the following embodiments.
A second embodiment will be described. The second embodiment relates to a semiconductor device having a HEMT.
In the semiconductor device 200 according to a second embodiment, as illustrated in
Other configurations are similar to those of the first embodiment.
The semiconductor device 100 according to the first embodiment employs a Schottky-type gate structure, while the semiconductor device 200 according to the second embodiment employs a MIS (metal-insulator-semiconductor) type gate structure. In the semiconductor device 200, as in the semiconductor device 100, the 2DEG 150 is present at a high concentration near the top face of the channel layer 103 excluding a region beneath the opening 110g, and the concentration of 2DEG 150 is extremely low in the region beneath the opening 110g. Thus, the semiconductor device 200 may readily modulate the concentration of 2DEG 150. In addition, the modulation of the concentration of the 2DEG 150 may achieve a normally-off operation while keeping the on-resistance low.
Next, a method for fabricating the semiconductor device 200 according to the second embodiment will be described.
First, as illustrated in
Thereafter, as illustrated in
The gate electrode 111 is then formed on the gate insulating film 212 as illustrated in
The semiconductor device 200 according to the second embodiment is fabricated in this manner.
A third embodiment will be described. The third embodiment relates to a semiconductor device having a HEMT.
In the semiconductor device 300 according to the third embodiment, a barrier layer 305 is disposed instead of the barrier layer 105 according to the first embodiment, as illustrated in
In addition, an insulating film 310 is disposed instead of the insulating film 110 according to the first embodiment. The insulating film 310 includes an insulating film 331 and an insulating film 332. The insulating film 331 covers a portion of the source electrode 108 and extends toward the drain electrode 109. A drain electrode 109 side-end of the insulating film 331 is spaced apart from the drain electrode 109. The insulating film 332 covers a portion of the drain electrode 109, and extends toward the source electrode 108. A source electrode 108 side-end of the insulating film 332 is spaced apart from the source electrode 108. The drain electrode 109 side-end of the insulating film 331 and the source electrode 108 side-end of the insulating film 332 are separated from each other, and an opening 310g of the insulating film 310 is defined between the drain electrode 109 side-end of the insulating film 331 and the source electrode 108 side-end of the insulating film 332. The gate electrode 111 is disposed on the insulating film 310 between the source electrode 108 and the drain electrode 109, and contacts the capping layer 106 through the opening 310g.
The insulating film 331 is a film that is more likely to generate a positive charge than the insulating film 332, at an interface with the capping layer 106. The insulating film 331 includes, for example, a nitride layer having Si, Al, Hf, Zr, Ti, Ta or W, and the insulating film 331 is preferably a Si nitride (SiN) layer. The thickness of the insulating film 331 may be, for example, 2 nm to 500 nm, and is preferably approximately 100 nm. The insulating film 332 includes, for example, an oxide layer or oxynitride layer. The oxide layer or oxynitride layer has Si, Al, Hf, Zr, Ti, Ta or W. The insulating film 332 is preferably an Al oxide (Al2O3) layer. The thickness of the insulating film 332 is, for example, 5 nm to 20 nm.
Other configurations are similar to those of the first embodiment.
In the semiconductor device 300 according to the third embodiment, the insulating films 331 and 332 are selectively formed on the capping layer 106, and the insulating film 331 is a film that is more likely to generate a positive charge than the insulating film 332, at the interface with the capping layer 106. Thus, the concentration of 2DEG 150 near the top face of the channel layer 103 is higher beneath the insulating film 331 than beneath the insulating film 332. Thus, the concentration of 2DEG 150 may be easily modulated by the semiconductor device 300. Further, modulation of the concentration of 2DEG 150 may improve drain breakdown voltage while keeping on-resistance low.
Next, a method for fabricating the semiconductor device 300 according to the third embodiment will be described.
First, as illustrated in
Thereafter, as illustrated in
Then, as illustrated in
The insulating film 332 is then processed to leave the insulating film 332 between a region intended to define the opening 310g and the drain electrode 109, as illustrated in
In this manner, the insulating film 310 includes the insulating films 331 and 332, and the insulating film 310 has an opening 310g between the insulating film 331 and the insulating film 332. The processing of the insulating film 332 increases the concentration of 2DEG 150 near the top face of the channel layer 103 beneath the opening 110g.
Then, as illustrated in
The semiconductor device 300 according to the third embodiment is fabricated in this manner.
A fourth embodiment will be described. The fourth embodiment relates to a semiconductor device having a HEMT.
In the semiconductor device 400 according to the fourth embodiment, as illustrated in
The insulating film 431 is a film that is more likely to generate a positive charge than the insulating film 332, at the interface with the capping layer 106. The insulating film 431 includes, for example, a nitride layer of Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si nitride (SiN) layer. The thickness of the insulating film 431 may be, for example, 2 nm to 500 nm, and is preferably approximately 100 nm.
Other configurations are the same as in the third embodiment.
In the semiconductor device 300 according to the third embodiment, a Schottky-type gate structure is employed, while in the semiconductor device 400 according to the fourth embodiment, a MIS-type gate structure is employed. Also, in the semiconductor device 400, the insulating films 431 and 332 are selectively formed on the capping layer 106, and the insulating film 431 is a film that is more likely to generate a positive charge than the insulating film 332, at the interface with the capping layer 106. Thus, the concentration of 2DEG 150 near the top face of the channel layer 103 is higher beneath the insulating film 431 than beneath the insulating film 332. Thus, the semiconductor device 400 may easily modulate the concentration of 2DEG 150. Further, modulation of the concentration of 2DEG 150 may improve drain breakdown voltage while keeping on-resistance low. Further, the insulating film 332 is disposed on the capping layer 106 beneath the gate electrode 111 in a plan view, so that the concentration of 2DEG 150 is kept low beneath the gate electrode 111.
Next, a method for fabricating the semiconductor device 400 according to the fourth embodiment will be described.
First, as illustrated in
Thereafter, as illustrated in
Then, as illustrated in
The insulating film 431 is then processed to leave the insulating film 431 so as to cover a portion of the source electrode 108, to extend toward the drain electrode 109, and to overlap an end of the insulating film 332, as illustrated in
In this manner, the insulating film 410 including insulating films 431 and 332 is formed.
The gate electrode 111 is then formed on the insulating film 431 as illustrated in
The semiconductor device 400 according to the fourth embodiment is fabricated in this manner.
Next, a fifth embodiment will be described. The fifth embodiment relates to a discrete package of a HEMT.
In the fifth embodiment, as illustrated in
Such a discrete package may be fabricated, for example, as follows. First, the semiconductor device 1210 is secured to the land 1233 of a lead frame using the die attach material 1234, such as solder. The gate pad 1226g is then connected to the gate lead 1232g of the lead frame by bonding using wires 1235g, 1235d and 1235s, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. Thereafter, the transfer mold process is performed using a mold resin 1231 for sealing. The lead frame is then disconnected.
Next, a sixth embodiment will be described. A sixth embodiment relates to a PFC (Power Factor Correction) circuit with a HEMT.
The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. A drain electrode of the switch element 1251 is connected to an anode terminal of the diode 1252 and one terminal of the choke coil 1253. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to a cathode terminal of the diode 1252. A gate driver is also connected to the gate electrode of the switch element 1251. The AC 1257 is connected between the terminals of the capacitor 1254 via the diode bridge 1256. A DC power supply (DC) is connected between the terminals of the capacitor 1255. In this sixth embodiment, the switch element 1251 is provided with a semiconductor device having the same structure as any of the first to fourth embodiments.
In the fabrication of the PFC circuit 1250, for example, solder or the like is used to connect the switch element 1251 to the diode 1252, the choke coil 1253, and the like.
Next, a seventh embodiment will be described. The seventh embodiment relates to a power supply apparatus having a HEMT suitable for server power supply.
The power supply is provided with a high voltage primary circuit 1261, a low voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.
The primary circuit 1261 is provided with a PFC circuit 1250 according to the sixth embodiment and an inverter circuit, such as a full bridge inverter circuit 1260, which is connected between the terminals of the capacitor 1255 of the PFC circuit 1250. The full bridge inverter circuit 1260 is provided with a plurality (four, in this example) of switch elements 1264a, 1264b, 1264c and 1264d.
The secondary circuit 1262 is provided with a plurality (three, in this example) of switch elements 1265a, 1265b and 1265c.
In this seventh embodiment, a semiconductor device having the same structure as in any of the first to fourth embodiments is used for the switch element 1251 of the PFC circuit 1250, and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260, which form the primary circuit 1261. Conversely, a related art MIS-type FET (field effect transistor) using silicon is used for the switch elements 1265a, 1265b and 1265c of the secondary circuit 1262.
Next, an eighth embodiment will be described. The eighth embodiment relates to an amplifier having a HEMT.
The amplifier is provided with a digital prestrain circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.
The digital prestrain circuit 1271 compensates for a nonlinear strain of input signals. The mixer 1272a mixes non-linear strain compensated input signals, and AC signals. The power amplifier 1273 includes a semiconductor device having the same structure as any of the first to fourth embodiments to amplify an input signal mixed with an alternating current signal. In this embodiment, for example, by switching the switching elements, an output signal may be mixed with an alternating current signal by the mixer 1272b, and the mixed signals may be transmitted to the digital prestrain circuit 1271. The amplifier may be used as a high-frequency amplifier, or a high-power amplifier. The high-frequency amplifier may be used, for example, in transmitting and receiving devices for mobile phone base stations, radar devices, and microwave generators.
The substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate. The substrate may be either electrically conductive, semi-insulating or insulating.
The structures of the gate, source and drain electrodes are not limited to those of the embodiments described above. For example, the structures may be composed of monolayers. In addition, these forming methods are not limited to the lift-off process. Further, if ohmic properties are obtained, the heat treatment after the forming of the source and drain electrodes may be omitted. Heat treatment may be performed after the formation of the gate electrode.
According to the present disclosure, the compositions of semiconductor layers are not limited to those described in the above embodiments. For example, other nitride semiconductors such as InAlN, InGaAlN, and the like may be used. In growing semiconductor layers containing In, a mixture of trimethylindium (TMIn) gas and a NH3 gas may be used as a precursor. The precursor may further include a TMAl gas, may further include a TMGa gas, or may further include a TMAl gas and a TMGa gas.
Although the preferred embodiments have been described in detail above, various alterations and substitutions may be made to the above-described embodiments without departing from the scope of the claims.
In accordance with the present disclosure, a technology for easily modulating concentration of a two-dimensional electron gas is provided.
Preferred embodiments have been described in detail above. However, various alterations and substitutions may be added to the embodiments described above, without limiting by the embodiments described above and without departing from the scope described in the claim.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to illustration of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-011462 | Jan 2020 | JP | national |
