Patent Application
20250151289
This application claims the benefit of priority to Chinese Application No. 202311456332.6, filed on Nov. 2, 2023, which is incorporated herein by reference in its entirety.
The present disclosure relates to semiconductor devices with a plurality of contact structures, three-dimensional (3D) memory devices, and fabrication methods thereof.
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.
A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
In one aspect, a semiconductor device includes a semiconductor layer, a stack structure over the semiconductor layer, a first contact structure, and a second contact structure. The stack structure includes alternating first layers and first dielectric layers. The stack structure includes a first portion and a second portion adjacent to the first portion, the first layers of the first portion include second dielectric layers, and the first layers of the second portion include conductive layers. The first contact structure extends through the first portion and the semiconductor layer. The second contact structure extends through a part of the first portion and connects with one of the conductive layers.
In some implementations, the first contact structure includes a first segment and a second segment connected with the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment. A size of the first end is greater than a size of the second end in a second direction perpendicular to the first direction.
In some implementations, the first segment further includes a third end away from the first end, and the second segment further includes a fourth end away from the second end. A size of the third end is greater than a size of the first end in the second direction, and a size of the second end is greater than a size of the fourth end in the second direction.
In some implementations, the first segment is located on a side of the second segment away from the semiconductor layer.
In some implementations, the second contact structure includes a vertical contact structure and a lateral contact structure connecting to the vertical contact structure. The vertical contact structure extends in a same direction as the first contact structure. The lateral contact structure connects with the one of the conductive layers.
In some implementations, the first contact structure includes a first joint in a first stack pair, and the vertical contact structure extends to the first stack pair. The first stack pair is a pair including one of the first dielectric layers and one of the first layers in contact with the one of the first dielectric layers.
In some implementations, the semiconductor device further includes a third contact structure extending through a portion of the first portion. The third contact structure is connected with a second stack pair, and the first contact structure includes a second joint in the second stack pair.
In some implementations, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer include a same material, and the first conductor layer and the second conductor layer include a same material.
In some implementations, the first contact structure further includes a first filler body surrounded by the first conductor layer.
In some implementations, the second contact structure further includes a second filler body surrounded by the second conductor layer, and the first filler body and the second filler body include a same material.
In some implementations, the semiconductor device further includes channel structures extending through the second portion into the semiconductor layer.
In some implementations, in a vertical direction, a length of the first contact structure is greater than a length of the channel structures.
In some implementations, the second portion includes a first part and a second part separated from the first part. The first portion connects the first part and the second part.
In some implementations, the semiconductor device further includes a peripheral circuit connected with the first contact structure.
In some implementations, the semiconductor device further includes a first connection layer and a second connection layer, the first connection layer connected with the first contact structure, the second connection layer connected with the peripheral circuit. The first connection layer is bonded with the second connection layer.
In some implementations, the peripheral circuit is disposed under the stack structure, and the first contact structure extends through the semiconductor layer to connect with the peripheral circuit.
In another aspect, a memory device includes a first semiconductor structure, a second semiconductor structure, and a first peripheral circuit. The first semiconductor structure includes a first stack structure including alternating first and second dielectric layers and a first contact structure extending through the first stack structure. The second semiconductor structure includes a second stack structure including alternating third and four dielectric layers and a second contact structure extending through the second stack structure. The first peripheral circuit is connected with the first contact structure and the second contact structure.
In some implementations, the first peripheral circuit is bonded with the first semiconductor structure, and the first peripheral circuit includes a first connect structure between the first semiconductor structure and the second semiconductor structure.
In some implementations, the memory device further includes a second peripheral circuit bonded with the second semiconductor structure. The second peripheral circuit includes a second connect structure connecting the second contact structure.
In some implementations, the second semiconductor structure is between the first peripheral circuit and the second peripheral circuit.
In some implementations, the first peripheral circuit further includes a semiconductor layer and an interconnect structure extending through the semiconductor layer.
In some implementations, the first contact structure includes an insulating filler and a conductor layer surrounding the insulating filler, the interconnect structure includes a conductive filler and a spacer surrounding the conductive filler, and the conductor layer is connected with the conductive filler.
In some implementations, the first contact structure includes a first segment and a second segment connected with the first segment in a first direction, the first segment includes a first end contacting the second segment, the second segment includes a second end contacting the first segment, and a size of the first end is greater than a size of the second end in a second direction perpendicular to the first direction.
In some implementations, the first segment further includes a third end away from the first end, the second segment further includes a fourth end away from the second end, a size of the third end is greater than a size of the first end in the second direction, and a size of the second end is greater than a size of the fourth end in the second direction.
In some implementations, the first stack structure is disposed over a semiconductor layer, and the first segment is located on a side of the second segment away from the semiconductor layer.
In some implementations, the first semiconductor structure further includes a third contact structure extending through a part of the first stack structure. The third contact structure includes a vertical contact structure and a lateral contact structure connecting to the vertical contact structure, and the vertical contact structure extends in a same direction as the first contact structure.
In some implementations, the first contact structure includes a first joint in a first stack pair, and the vertical contact structure extends to the first stack pair. The first stack pair is a pair including one of the first dielectric layers and one of the second dielectric layers in contact with the one of the first dielectric layers.
In some implementations, the memory device further includes a fourth contact structure extending through a portion of the first stack structure. The fourth contact structure is connected with a second stack pair, and the first contact structure includes a second joint in the second stack pair.
In some implementations, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The third contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer include a same material, and the first conductor layer and the second conductor layer include a same material.
In some implementations, the first contact structure further includes a first filler body surrounded by the first conductor layer.
In still another aspect, a method of forming a semiconductor device is disclosed. The method includes forming a stack structure including alternating first and second dielectric layers. The method also includes forming a first contact hole extending through the stack structure. The method further includes forming second contact holes extending through a part of the stack structure during the formation of the first contact hole.
In some implementations, forming the first contact hole and forming the second contact holes during the formation of the first contact hole include etching the stack structure with a first mask to form a first opening and one or more second openings which extend into the stack structure, where the second contact holes include the one or more second openings, and etching the first opening with a second mask to form a third opening which extends further through the stack structure, where the first contact hole includes the first and third openings.
In some implementations, forming the second contact holes further includes etching the stack structure with a third mask to form one or more fourth openings which extend into the stack structure. The second contact holes further include the one or more fourth openings.
In some implementations, the method further includes forming a first contact structure in the first contact hole, and forming second contact structures in the second contact holes, respectively, during the formation of the first contact structure.
In some implementations, the first contact structure includes a first spacer, a first conductor layer surrounded by the first spacer, and a first filler body surrounded by the first conductor layer. The second contact structures include second spacers, second conductor layers surrounded by the second spacers, lateral contact structures connected with the second conductor layers, and second filler bodies surrounded by the second conductor layers, respectively.
In some implementations, forming the first contact structure and forming the second contact structures include: forming the first spacer on a sidewall of the first contact hole, and forming the second spacers on sidewalls of the second contact holes, respectively; forming the lateral contact structures of the second contact structures below bottoms of the second contact holes; forming the first conductor layer over the first spacer and a bottom of the first contact hole, and forming the second conductor layers over the second spacers and the lateral contact structures, respectively; and filling a remaining portion of the first contact hole with the first filler body, and filling remaining portions of the second contact holes with the second filler bodies, respectively.
In some implementations, forming the lateral contact structures of the second contact structures below the bottoms of the second contact holes includes removing part of respective second dielectric layers exposed at the bottoms of the second contact holes to form lateral recesses, respectively, and filling the lateral recesses by depositing conductive materials through the second contact holes to form the lateral contact structures, respectively.
In some implementations, forming the first contact structure and forming the second contact structures further include forming a first contact pad on the first conductor layer and the first filler body, and forming second contact pads on the second conductor layers and the second filler bodies, respectively.
In still yet another aspect, a semiconductor device includes a stack structure, a first contact structure, and a second contact structure. The stack structure includes alternating first and second dielectric layers. The first contact structure extends through the stack structure, and includes a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer. The second contact structure extends through a part of the stack structure, and includes a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The first spacer and the second spacer include a first material, and the first conductor layer and the second conductor layer include a second material different from the first material.
In some implementations, the first contact structure includes a first segment and a second segment connected with the first segment in a first direction, the first segment includes a first end contacting the second segment, and the second segment includes a second end contacting the first segment. A size of the first end is greater than a size of the second end in a second direction perpendicular to the first direction.
In some implementations, the first segment further includes a third end away from the first end, and the second segment further includes a fourth end away from the second end. A size of the third end is greater than a size of the first end in the second direction, and a size of the second end is greater than a size of the fourth end in the second direction.
In some implementations, the first stack structure is disposed over a semiconductor layer, and the first segment is located on a side of the second segment away from the semiconductor layer.
In some implementations, the second contact structure includes a vertical contact structure and a lateral contact structure connecting to the vertical contact structure, and the vertical contact structure extends in a same direction as the first contact structure.
In some implementations, the first contact structure includes a first joint in a first stack pair, and the vertical contact structure extends to the first stack pair. The first stack pair is a pair including one of the first dielectric layers and one of the second dielectric layers in contact with the one of the first dielectric layers.
In some implementations, the semiconductor device further includes a third contact structure extending through the stack structure. The third contact structure is connected with a second stack pair, and the first contact structure includes a second joint in the second stack pair.
In some implementations, the semiconductor device further includes a peripheral circuit connected with the first contact structure and the second contact structure.
In still yet another aspect, a memory device includes a first contact structure and a second contact structure. The first contact structure includes an insulating filler and a conductor layer surrounding the insulating filler and extending in a first direction. The second contact structure includes a conductive filler and a spacer surrounding a sidewall of the conductive filler and extending in the first direction. The conductor layer connects with the conductive filler.
In still yet another aspect, a semiconductor device includes a semiconductor layer, a stack structure over the semiconductor layer and including alternating conductive layers and dielectric layers, a first contact structure extending through the stack structure and including a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer, and a second contact structure extending through a portion of the stack structure and including a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The second conductor layer connects with one of the conductive layers, and the first conductor layer and the conductive layers are separated by the first spacer.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.
The present disclosure will be described with reference to the accompanying drawings.
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and/or vertical contacts are formed) and one or more dielectric layers.
In some 3D memory devices, such as 3D NAND memory devices, channel structures are formed in a core array region. Memory cells for storing data are vertically stacked through a stack structure (e.g., a memory stack) in the vertical channel structures. 3D memory devices usually include staircase structures formed in staircase regions (e.g., on one or more sides (edges), or at the center, of the stacked storage structure) for purposes such as word line pick-up/fan-out using word line contacts landed onto different steps/levels of the staircase structures. Through substrate vias (TSVs) may also be formed on the edges or outside of the staircase regions to provide interconnection across the entire stack structure.
Initially, the stack structure may include interleaved first dielectric layers (e.g., silicon oxide layers) and second dielectric layers (e.g., silicon nitride layers). During the formation of the channel structures, all the second dielectric layers in the core array region and parts of the second dielectric layers in the staircase regions are replaced with conductive layers, leaving remainders of the second dielectric layers in the staircase regions. In some applications, the remainders of the second dielectric layers in the staircase regions need to be removed and then replaced by silicon oxide. The regions where the TSVs are located are also filled with silicon oxide. Then, the word line contacts and the TSVs can be formed by firstly etching the silicon oxide to form contact holes in the silicon oxide area and then filling the contact holes with conductive materials. However, with the removal of the remainders of the second dielectric layers in the staircase regions, the manufacturing process can be complicated and with high cost.
To address one or more of the aforementioned issues, the present disclosure introduces a solution that can form a plurality of contact structures in a connection region (a region outside of the core array region) without a need to remove the remainders of the second dielectric layers in the connection region. The plurality of contact structures formed thereof may include contact structures that only extend through a part of the stack structure, contact structures that extend through the whole stack structure and penetrate only a part of a semiconductor layer on which the stack structure is disposed, contact structures that extend through both the stack structure and the semiconductor layer, or any combination thereof. The contact structures that extend through both the stack structure and the semiconductor layer can be used as interconnect structures between stacked dies. Since the contact structures disclosed herein can be formed by etching the first dielectric layers and the remainders of the second dielectric layers, the manufacturing process can be simplified and at low cost.
As shown in
As shown in
As described below in detail, connection region 103 can include conductive portions 105 and dielectric portions 107 arranged in the y-direction. As shown in
As shown in
Stack structure 203 may include alternating first layers and first dielectric layers 224. The first layers and first dielectric layers 224 can alternate in the vertical direction (the z-direction). In some implementations, stack structure 203 can include a plurality of stack pairs which are stacked vertically in the z-direction, and each of the stack pairs includes one of the first layers and one of first dielectric layer 224.
Stack structure 203 may include a first portion and a second portion adjacent to the first portion. The first portion can be in connection region 103. For example, with reference to
In some implementations, semiconductor structure 100 can be part of a NAND Flash memory device, and stack structure 203 can be a stacked storage structure through which NAND memory strings are formed. As shown in
As described below in detail with respect to a fabrication process of
In some implementations, each conductive layer in the second portion of stack structure 203 (within core array region 101 and conductive portion 105 of connection region 103) functions as a gate line of the NAND memory strings (in the forms of channel structures 110) in core array region 101, as well as a word line extending laterally from the gate line and ending in conductive portion 105 of connection region 103 for word line pick-up/fan-out through word line pick-up structures (e.g., contact structures 106). The word lines (i.e., the conductive layers) at different depths/level of the second portion of stack structure 203 each extend laterally in core array region 101 and conductive portion 105 of connection region 103, but are discontinuous (e.g., being replaced by the second dielectric layers 222) in dielectric portion 107 of connection region 103, according to some implementations.
Conductive layers 302 can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. First or second dielectric layers 222, 224 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. First dielectric layers 224 and second dielectric layers 222 can have different dielectric materials, such as silicon oxide and silicon nitride, respectively. In some implementations, conductive layers 302 include metals, such as tungsten, first dielectric layers 224 include silicon oxide, and second dielectric layers 222 include silicon nitride.
By way of examples,
In some implementations, each of second contact structure 106A and third contact structure 106B includes a vertical contact structure (e.g., a conductor layer 202) and a lateral contact structure 206 connecting to the vertical contact structure. The vertical contact structure extends in the same direction as first contact structure 116. Lateral contact structure 206 connects with one of conductive layers 302. For example, each of second contact structure 106A and third contact structure 106B includes conductor layer 202, a spacer 204 circumscribing conductor layer 202, lateral contact structure 206 below and in contact with conductor layer 202. Conductor layer 202 and lateral contact structure 206 can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicides, or any combination thereof. Spacer 204 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some implementations, conductor layer 202 and lateral contact structure 206 include TiN/W, and spacer 204 includes silicon oxide.
In some implementations, each of second contact structure 106A and third contact structure 106B may further include a filler body 208 surrounded by conductor layer 202. Filler body 208 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Each of second contact structure 106A and third contact structure 106B may further include a contact pad 210 on top of and in contact with filler body 208 and conductor layer 202. Contact pad 210 may be electrically connected to conductor layer 202. Contact pad 210 can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicides, or any combination thereof.
First contact structure 116 can be a contact structure which may extend through stack structure 203 and a part of or the entire semiconductor layer 201. For example, first contact structure 116 may penetrate stack structure 203 and a part of semiconductor layer 201. In another example, first contact structure 116 may penetrate both stack structure 203 and semiconductor layer 201, as illustrated in
Referring to
Referring back to
In some implementations, the vertical contact structure (e.g., conductor layer 202) of second contact structure 106A may extend to a first stack pair. The first stack pair can be a pair including (a) one of first dielectric layers 224 and (b) one of the first layers in contact with the one of first dielectric layers 224. For example, as illustrated in
In some implementations, the vertical contact structure (e.g., conductor layer 202) of third contact structure 106B may extend to a second stack pair, as illustrated in
The vertical contact structure (e.g., conductor layer 202) of second contact structure 106A may extend to the first stack pair (first dielectric layer 224A and second dielectric layer 222A). Lateral contact structure 206 of second contact structure 106A may be located in second dielectric layer 222A of the first stack pair. First joint 216 of first contact structure 116 and third joint 219 of third contact structure 106B may be in the first stack pair.
The vertical contact structure (e.g., conductor layer 202) of third contact structure 106B may extend to the second stack pair (first dielectric layer 224B and second dielectric layer 222B). Lateral contact structure 206 of third contact structure 106B may be located in second dielectric layer 222B of the second stack pair. Second joint 217 of first contact structure 116 may be in the second stack pair.
In some implementations, peripheral circuit 330 may further include a connection layer 334 and a bonding layer 335. Connection layer 334 may be connected with device layer 332 to transfer electrical signals to and from device layer 332. As shown in
Semiconductor structure 329 may be divided into at least a core array region 311 and a connection region 315. Connection region 315 may also be divided into a staircase region 316 and a region 313 outside staircase region 316. In core array region 311, semiconductor structure 329 may include a semiconductor layer 301 and a stack structure formed on semiconductor layer 301. The stack structure may include interleaved conductive layers 302 and first dielectric layers 304. Semiconductor structure 329 may also include channel structures 310 extending through the stack structure. Memory cells for storing data are vertically stacked through the stack structure (e.g., a memory stack) in the vertical channel structures.
As shown in
In staircase region 316, semiconductor structure 329 may include staircase structures. Semiconductor structure 329 may also include word line contacts 312 which extend through dielectric materials (e.g., nitride oxide) filled above the staircase structures and land onto different steps/levels of the staircase structures. In region 313 on the edge of or outside staircase region 316, semiconductor structure 329 may further include a TSV 314 which extends through both (a) dielectric materials (e.g., nitride oxide) filled in region 313 and (b) semiconductor layer 301.
As shown in
A fabrication process of semiconductor structure 329 is described briefly herein. Initially, a stack structure including interleaved first dielectric layers 304 (e.g., silicon oxide layers) and second dielectric layers (e.g., silicon nitride layers) can be formed on semiconductor layer 301. Channel structures 310 may be formed to extend through the stack structure and into semiconductor layer 301. Then, all the second dielectric layers in core array region 311 and parts of the second dielectric layers in the staircase structures are replaced with conductive layers 302, leaving remainders of the second dielectric layers in staircase region 316. The remainders of the second dielectric layers in staircase region 316 can be removed and then replaced by silicon oxide. Region 313 is also filled with silicon oxide. As a result, a silicon oxide area 328 can be formed. Then, word line contact 312 in staircase region 316 and TSV 314 in region 313 can be formed by firstly forming contact holes in silicon oxide area 328 and then filling the contact holes with conductive materials. This fabrication process needs to remove the remainders of the second dielectric layers in staircase region 316, which can be complicated.
Semiconductor device 350 may include a semiconductor structure 360 and peripheral circuit 330 stacked on and connected with semiconductor structure 360. Semiconductor structure 360 may be divided into at least core array region 101 and connection region 103. In some implementations, semiconductor structure 360 may include semiconductor layer 201 and stack structure 203 over semiconductor layer 201. Stack structure 203 may include alternating first layers and first dielectric layers 224. Stack structure 203 may include a first portion 362 and a second portion 364 adjacent to first portion 362. In some examples, second portion 364 of stack structure 203 may include a first part in core array region 101A and a second part in core array region 101B separated from the first part (as illustrated in
The first layers of first portion 362 may include second dielectric layers 222, whereas the first layers of second portion 364 may include conductive layers 302. For example, first portion 362 of stack structure 203 may include interleaved second dielectric layers 222 and first dielectric layers 224. Second portion 364 of stack structure 203 may include interleaved conductive layers 302 and first dielectric layers 224.
In some implementations, semiconductor structure 360 may further include (a) first contact structure 116 extending through first portion 362 and semiconductor layer 201 and (b) second contact structure 106 extending through a part of first portion 362 and connecting with one of conductive layers 302. For example, the vertical contact structure (e.g., conductor layer 202) of second contact structure 106 may extend to a first stack pair (e.g., a stack pair including first dielectric layer 224A and second dielectric layer 222A). Lateral contact structure 206 of second contact structure 106 may be located in second dielectric layer 222A and connect with a conductive layer 302A in the same layer (e.g., second dielectric layer 222A and conductive layer 302A are different parts of the same first layer).
Semiconductor structure 360 may further include channel structures 110 extending through second portion 364 into semiconductor layer 201. In the vertical direction (e.g., the z direction), a length of first contact structure 116 can be greater than a length of channel structures 110.
As shown in
In some implementations, peripheral circuit 330 may be connected with first contact structure 116. In some implementations, peripheral circuit 330 may be disposed under stack structure 203, and first contact structure 116 may extend through semiconductor layer 301 to connect with peripheral circuit 330.
Consistent with some aspects of the present disclosure, instead of having staircase structures and word line contacts landed on different levels/stairs of the staircase structures, semiconductor structure 360 can include stack structure 203 with uniform heights (e.g., no staircase) and second contact structure 106 in dielectric portion 107 of connection region 103 for word line pick-up/fan-out. As shown in
Consistent with some aspects of the present disclosure, first contact structure 116 and second contact structure 106 may be formed in the same region or different regions, which is not limited herein. For example, first contact structure 116 may be formed in a neighborhood of a sear ring, whereas second contact structure 106 may be formed in a region close to core array region 101. A semiconductor device disclosed herein may include: (a) a stack structure including alternating first and second dielectric layers; (b) a first contact structure 116 extending through the stack structure, and including a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer; and (c) a second contact structure extending through a part of the stack structure, and including a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The first spacer and the second spacer may include a first material (e.g., dielectric material), and the first conductor layer and the second conductor layer may include a second material (e.g., a conductive material) different from the first material.
For example, first semiconductor device 300A may include a first semiconductor structure 329A and a first peripheral circuit 330A. First semiconductor structure 329A may include a word line contact 312A and a TSV 314A. Second semiconductor device 300B may include a second semiconductor structure 329B and a second peripheral circuit 330B. Second semiconductor structure 329B may include a word line contact 312B and a TSV 314B. It is contemplated that first and second semiconductor structures 329A, 329B may have structures like that of semiconductor structure 329 of
As illustrated in
Memory device 450 may include a first semiconductor device 350A and a second semiconductor device 350B. First and second semiconductor devices 350A, 350B may have structures like that of semiconductor device 350 of
First and second semiconductor devices 350A, 350B may be bonded together to form memory device 450. For example, a bonding layer 454 may be formed between first and second semiconductor devices 350A, 350B to bond the two devices together. Any suitable bonding technologies can be applied in bonding layer 454, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc. An interconnect structure 458 can be formed in bonding layer 454, so that an interconnect structure 452A of first peripheral circuit 330A can be connected with first contact structure 116B of semiconductor structure 360B through interconnect structure 458.
Consistent with some aspects of the present disclosure, memory device 450 may include: (a) first semiconductor structure 360A including first stack structure and contact structure 116A extending through first stack structure 203A; (b) a second semiconductor structure 360B including second stack structure 203B and contact structure 116B extending through second stack structure 203B; and (c) first peripheral circuit 330A connected with contact structures 116A, 116B.
In some implementations, first stack structure 203A may include alternating first and second dielectric layers. Second stack structure 203B may include alternating third and four dielectric layers. The third and fourth dielectric layers may include the same materials as the first dielectric layers and the second dielectric layers, respectively.
In some implementations, first peripheral circuit 330A may be bonded with first semiconductor structure 360A, and first peripheral circuit 330A may include a first connect structure 455A between first semiconductor structure 360A and second semiconductor structure 360B. First connect structure 455A may be filled with a filler body 456A.
In some implementations, memory device 450 may further include second peripheral circuit 330B bonded with second semiconductor structure 360B. Second semiconductor structure 360B can be between first peripheral circuit 330A and second peripheral circuit 330B. Second peripheral circuit 330B may include a second connect structure 455B connecting contact structure 116B. Second connect structure 455B may be filled with a filler body 456B.
In some implementations, first peripheral circuit 330A may further include semiconductor layer 331A and an interconnect structure 452A extending through semiconductor layer 331A. Interconnect structure 452A may include a conductive filler 454A and a spacer 453A surrounding conductive filler 454A. Similarly, second peripheral circuit 330B may further include semiconductor layer 331B and an interconnect structure 452B extending through semiconductor layer 331B. Interconnect structure 452B may include a conductive filler 454B and a spacer 453B surrounding conductive filler 454B.
In some implementations, first contact structure 116A may include an insulating filler (e.g., filler body 218A) and conductor layer 212A surrounding insulating filler, whereas interconnect structure 452A may include conductive filler 454A and spacer 453A surrounding conductive filler 454A. Conductor layer 212A of first contact structure 116A can be connected with conductive filler 454A of interconnect structure 452A. Similarly, second contact structure 116B may include an insulating filler (e.g., filler body 218B) and conductor layer 212B surrounding insulating filler, whereas interconnect structure 452B may include conductive filler 454B and spacer 453B surrounding conductive filler 454B. Conductor layer 212B of second contact structure 116B can be connected with conductive filler 454B of interconnect structure 452B.
Consistent with some aspects of the present disclosure, a memory device disclosed herein may include: (a) a first contact structure (e.g., 116A) including an insulating filler and a conductor layer surrounding the insulating filler and extending in a first direction such as the z direction; and (b) a second contact structure (e.g., 452A) including a conductive filler and a spacer surrounding a sidewall of the conductive filler and extending in the first direction. The conductor layer connects with the conductive filler.
It is contemplated that first contact structure 516 may have a structure like that of first contact structure 116 of
It is contemplated that contact structures 616A, 616B may have a structure like that of first contact structure 116 of
Referring to
Method 700 proceeds to operation 704, as illustrated in
In some implementations, to form a channel structure, a channel hole extending vertically through the stack structure is formed, and a memory layer and a channel layer are sequentially formed over sidewalls of the channel hole. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed over sidewalls of the channel hole. In some implementations, dummy channel structures (e.g., dummy channel structures 112 in
In some implementations, to form channel structures, a plurality of channel holes are opened, such that each channel hole becomes the location for growing an individual channel structure in the later process. In some implementations, fabrication processes for forming channel holes of channel structures include wet etching and/or dry etching, such as deep-ion reactive etching (DRIE). Subsequently, a memory layer (including a blocking layer, a storage layer, and a tunneling layer) and a channel layer are sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, the memory layer is first deposited along the sidewalls and bottom surface of the channel hole, and the semiconductor channel is then deposited over the memory layer. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory layer. The channel layer can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of the memory layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form the memory layer and the channel layer of the channel structure.
In some implementations, a high-k gate dielectric layer is formed before the formation of the memory layer. That is, the high-k gate dielectric layer, memory layer (including the blocking layer, storage layer, and tunneling layer), and the channel layer can be sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surfaces of the channel hole, the memory layer is then deposited over the high-k gate dielectric layer, and the semiconductor channel is then deposited over the memory layer. The high-k gate dielectric layer can be formed by depositing high-k dielectric materials, such as aluminum oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, over the high-k gate dielectric layer to form the memory layer. The channel layer can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of the memory layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form the high-k gate dielectric layer, the memory layer, and the channel layer of the channel structure.
In some implementations, dummy channel structures (e.g., dummy structures 112 in
Method 700 proceeds to operation 706, as illustrated in
At the beginning of the gate replacement process, a slit extending through first dielectric layers 224 and second dielectric layers 222 and across first and second portions 362, 364 of stack structure 203 is formed. In some implementations, the slit extends vertically through the local contact layer as well. The slit can also extend laterally across core array region 101 and connection region 103 in the x-direction (the word line direction). In some implementations, fabrication processes for forming the slit include wet etching and/or dry etching, such as DRIE, of the first dielectric layers and the second dielectric layers. The etching process through the stack structure may not stop at the top surface of the silicon substrate and may continue to etch part of the silicon substrate to ensure that the slit extends vertically all the way through all the first dielectric layers and second dielectric layers of stack structure 203.
Thereafter, the part of the slit in the core array region is covered by a sacrificial layer. In some implementations, the sacrificial layer that is different from the first dielectric layers and the second dielectric layers, such as a polysilicon layer or a carbon layer, is deposited into the slit using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to at least partially fill the slit (covering the exposed first dielectric layers and second dielectric layers in the slit). The sacrificial layer can then be patterned using lithography and wet etching and/or dry etching to remove the part of the sacrificial layer in the connection region, leaving only the part of the sacrificial layer in the core array region to cover only the part of the slit in the core array region.
Subsequently, parts of the second dielectric layers 222 in the connection region 103 of the stack structure 203 are removed through the slit in the connection region 103 of the stack structure 203. The removal can be performed by wet etching to form lateral recesses, leaving the remainders of second dielectric layers 222 in a dielectric portion of the connection region 103 intact. In some implementations, the parts of the second dielectric layers are wet etched by applying a wet etchant through the part of the slit in the connection region that is uncovered by the sacrificial layer, creating lateral recesses interleaved between the first dielectric layers 224. The wet etchant can include phosphoric acid for etching the second dielectric layers including silicon nitride. In some implementations, one or both of the etching rate and etching time are controlled to remove only the parts of the second dielectric layers 222 in the conductive portion (e.g., conductive portion 105 in
Then, the slit in core array region 101 of the stack structure is opened. Specifically, the part of the slit in core array region 101 is re-opened by removing the sacrificial layer to expose the first dielectric layers and the second dielectric layers. In some implementations, the sacrificial layer is selectively etched away from the part of the slit in the core array region, for example, using potassium hydroxide (KOH) for etching the sacrificial layer having polysilicon, to open the part of the slit in the core array region.
After that, the slit in connection region 103 of the stack structure is covered. Specifically, the lateral recesses and the part of the slit in the connection region are covered by another sacrificial layer. In some implementations, the sacrificial layer that is different from the first dielectric layers and the second dielectric layers, such as a polysilicon layer or a carbon layer, is deposited into the lateral recesses and the slit using one or more thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof, to at least partially fill the slit (covering the exposed first dielectric layers and second dielectric layers). The sacrificial layer can then be patterned using lithography and wet etching and/or dry etching to remove the part of the sacrificial layer in the core array region, leaving only the part of the sacrificial layer in the connection region to cover only the lateral recesses and the part of the slit in the connection region, but not in the core array region. It is understood that the lateral recesses may be considered as parts of the slit in the connection region. Thus, even if only the lateral recesses are fully or partially filled by the sacrificial layer, the part of the slit in the connection region may still be considered as being covered.
Later, all the second dielectric layers in core array region 101 of the stack structure are removed through the slit in core array region 101 of the stack structure. Specifically, all the second dielectric layers in core array region 101 are fully removed by wet etching to form lateral recesses. In some implementations, the second dielectric layers are wet etched by applying a wet etchant through the part of the slit in the core array region that is uncovered by the sacrificial layer, creating the lateral recesses interleaved between the first dielectric layers. The wet etchant can include phosphoric acid for etching the second dielectric layers including silicon nitride. In some implementations, one or both of the etching rate and etching time are controlled to ensure that all the second dielectric layers in the core array region are completely etched away. Since the part of the slit in the connection region 103 is covered by the sacrificial layer that is resistant to the etchant for removing the second dielectric layers, the remainders of the second dielectric layers in the dielectric portion 107 of the connection region 103 remain intact.
Afterward, the slit in the connection region of the stack structure is opened. Specifically, the part of the slit in the connection region is re-opened by removing the sacrificial layer to expose the first dielectric layers and the remainders of the second dielectric layers in the connection region. In some implementations, the sacrificial layer is selectively etched away from the part of the slit in the connection region, for example, using KOH for etching the sacrificial layer having polysilicon, to open the part of the slit (and the lateral recesses) in the connection region.
Finally, the conductive layers are deposited into lateral recesses in core array region 101 and conductive portion 105 of connection region 103 through the slit. In some implementations in which high-k gate dielectric layers are not formed in the channel structures, the high-k gate dielectric layers are deposited into the lateral recesses prior to the conductive layers, such that the conductive layers are deposited on and surrounded by the high-k gate dielectric layers. In some implementations in which high-k gate dielectric layers are formed in the channel structures, the high-k gate dielectric layers are not deposited into the lateral recesses prior to the conductive layers, such that the conductive layers are deposited on and surrounded by the first dielectric layers. The conductive layers, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.
As described above, the removal of the second dielectric layers (stack sacrificial layers, e.g., having silicon nitride) can be performed separately in the core array region and the connection region by partially covering the slit in the core array region or the connection region to allow the second dielectric layers to be removed at different scopes (e.g., fully removal in the core array region and partial removal in the connection region). It is understood that in another gate replace process, the removal of the second dielectric layers may be performed first in the core array region, and then in the connection region.
Referring back to
Referring back to
Referring back to
Referring back to
Referring to
Method 900 proceeds to operation 904, as illustrated in
For example, with reference to
With reference to
In some implementations, the stack structure may be further etched with a third mask to form a fourth opening (not shown in the figures) which extends into the stack structure with a depth different from that of opening 1004. The second contact holes may further include the fourth opening. For example, the fourth opening may form a second contact hole for second contact structure 106B of
The method forming openings with different depths is known as a chopping process. As used herein, a “chopping” process is a process that increases the depth of one or more openings extending through a stack structure including interleaved first and second dielectric layers by a plurality of etching cycles. Each etch cycle can include one or more dry etch and/or wet etch processes that etch one pair of first and second dielectric layers, i.e., reducing the depth by one dielectric layer pair. The purpose of the chopping process is to make multiple openings at different depths. Accordingly, depending on the number of openings, a certain number of chopping processes, along with a number of chopping masks, may be needed. It is understood that the number of chopping masks, the sequence of the chopping masks, the design (e.g., the number and pattern of openings) of each chopping mask, and/or the reduced depth by each chopping process (e.g., the number of etching cycles) may affect the specific depth of each opening after the chopping process. A detailed description of the chopping process can be referenced in U.S. patent application Ser. No. 16/881,168, filed on May 22, 2022, and U.S. patent application Ser. No. 16/881,339, filed on May 22, 2022, both of which are incorporated by reference in their entireties herein.
Method 900 proceeds to operation 908, as illustrated in
For example, with reference to
Then, a portion of first spacer 214 on the bottom of the first contact hole is removed to expose the remainder portion of semiconductor layer 201. A portion of second spacer 204 on the bottom of the second contact hole is also removed to expose second dielectric layer 222A. In some implementations, dry etching can be applied to remove the portion of first spacer 214 on the bottom of the first contact hole and the portion of second spacer 204 on the bottom of the second contact hole. For example, the etching rate, direction, and/or duration of RIE are controlled to etch only the portion of first spacer 214 and the portion of second spacer 204 on the bottom surfaces, but not on the sidewalls, i.e., “punching” through first spacer 214 and second spacer 204 in the z-direction to expose the remainder portion of semiconductor layer 201 and second dielectric layer 222A, respectively.
Subsequently, with reference to
With reference to
With reference to
With reference to
Memory device 1104 can be any 3D memory device disclosed herein. In some implementations, memory device 1104 includes a NAND Flash memory.
Memory controller 1106 (a.k.a., a controller circuit) is coupled to memory device 1104 and host 1108 and is configured to control memory device 1104, according to some implementations. For example, memory controller 1106 may be configured to operate the plurality of channel structures via the word lines. Memory controller 1106 can manage the data stored in memory device 1104 and communicate with host 1108. In some implementations, memory controller 1106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 1106 is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 1106 can be configured to control operations of memory device 1104, such as read, erase, and program operations. Memory controller 1106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 1104 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 1106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 1104. Any other suitable functions may be performed by memory controller 1106 as well, for example, formatting memory device 1104. Memory controller 1106 can communicate with an external device (e.g., host 1108) according to a particular communication protocol. For example, memory controller 1106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
Memory controller 1106 and one or more 3D memory devices 1104 can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system 1102 can be implemented and packaged into different types of end electronic products. In one example as shown in
The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311456332.6 | Nov 2023 | CN | national |
