Patent Application
20240387378
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB).
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In
The release layer 104 may be formed of a polymer-based material, which may be removed along with the carrier substrate 102 from the overlying structures (e.g., back-side redistribution structure 106) that will be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be leveled and may have a high degree of planarity.
The dielectric layer 108 may be formed on the release layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104. In some embodiments, the dielectric layer 108 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof.
The metallization pattern 110 may be formed on the dielectric layer 108. As an example to form metallization pattern 110, a seed layer is formed over the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern 110.
The dielectric layer 112 may be formed on the metallization pattern 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer 112 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 112 is then patterned to form openings exposing portions of the metallization pattern 110. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer 112 is a photo-sensitive material, the dielectric layer 112 can be developed after the exposure.
It should be appreciated that the back-side redistribution structure 106 may include any number of dielectric layers and metallization patterns, such as one or more layers of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically couple the various conductive lines.
In
Openings 205 are formed within the second substrate 203 to accommodate the formation of deep trench capacitors using the conductive material 207 and the dielectric material 209. In an embodiment the openings 205 may be formed using one or more photolithographic masking and etching processes, such as the use of a photomask followed by an anisotropic etching process to remove portions of the second substrate 203. However, any suitable process may be utilized.
Once the openings 205 have been formed, a liner 211 may be deposited to line the openings 205, followed by a series of alternating layers of conductive material 207 and dielectric material 209. In an embodiment the liner 211 may be a dielectric material such as silicon oxide, the conductive material 207 may be a conductive material such as titanium nitride, and the dielectric material 209 may be one or more layers of high-k dielectric materials, such as zirconium oxide, aluminum oxide, hafnium oxide, combinations of these, or the like. Each layer may be deposited using a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations of these, or the like, until there are four layers of the conductive material 207 and four layers of the dielectric material 209. However, any suitable materials, processes, and number of alternating layers may be utilized.
Once the layers of the conductive material 207 and the layers of the dielectric material 209 have been formed, the layers may be patterned (e.g., through one or more photolithographic masking and etching processes), a contact etch stop layer may be deposited, and contacts 213 to overlying metallization layers 215 may be formed. In an embodiment the contacts 213 and the overlying metallization layers 215 may be formed using damascene or dual damascene processes, such as by initially depositing a dielectric layer (not separately illustrated), patterning the dielectric layer to expose the underlying conductive material, overfilling the openings with another conductive material, and planarizing the conductive material to form the contacts 213 and the metallization layers 215. However, any suitable methods may be utilized to form the contacts 213 and the metallization layers 215.
Returning now to
In another embodiment, the external die contacts 217 may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the external die contacts 217 are contact bumps, the external die contacts 217 may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the external die contacts 217 is a tin solder bump, the external die contacts 217 may be formed by initially forming a layer of tin through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape.
Once the external die contacts 217 have been formed, a passivation layer 219 may be formed over the external die contacts 217. In an embodiment the passivation layer 219 may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may be utilized. The passivation layer 219 may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 25 μm, such as about 7 μm, although any suitable method and thickness may be used. Once in place, the passivation layer 219 may be planarized with the external die contacts 217 using, e.g., a chemical mechanical polishing process.
Additionally, while a process has been described whereby the external die contacts 217 are formed and then surrounded by the passivation layer 219, this order is intended to be illustrative and is not intended to be limiting. Rather, any suitable order of process steps, such as depositing the passivation layer 219 first, patterning the passivation layer 219 to form openings for the external die contacts 217, and then forming the external die contacts 217 within the openings, may be also be utilized. Any suitable process for forming the external die contacts 217 and the passivation layer 219 may be utilized, and all such processes are fully intended to be included within the scope of the embodiments.
In some embodiments, the first IPD die 50A and second IPD die 50B may be formed in processes of a same technology node, or may be formed in processes of different technology nodes. For example, the first IPD die 50A may be of a more advanced process node than the second IPD die 50B. The first IPD dies 50A and 50B may have different sizes (e.g., different heights and/or surface areas), or may have the same size (e.g., same heights and/or surface areas).
Returning to
In
Once formed, the first bottom layer 301 may have dimensions which help to lower the overall footprint of the first IPD stack 500 while still obtaining an increase in a desired parameter such as capacitance. For example, a first one of the first IPD dies 50A may have a first height H1 of between about 40 μm and about 500 μm, such as about 90 μm, while a second one of the IPD dies 50B may have a second height H2 that may be equal to or different from the first height H1, such as the second height H2 being between about 40 μm and about 500 μm, such as about 90 μm. Similarly, the first one of the IPD dies 50A may have a first width W1 of between about 0.1 mm and about 20 mm, such as about 5 mm, while the second one of the IPD dies 50B may have a second width W2 that may be equal to or different from the first width W1, such as the second width W2 being between about 0.1 mm and about 20 mm, such as about 5 mm. However, any suitable dimensions may be utilized.
Similarly, the encapsulant 120 may have a third height H3 that is larger than the first height H1 and the second height H2, such as by being between about 50 μm and about 700 μm, such as about 100 μm. The back-side redistribution structure 106 may have a fourth height H4 that is less than the third height H3, such as the fourth height H4 being between about 10 μm and about 150 μm, such as about 40 μm. However, any suitable heights may be utilized for the encapsulant 120 and the back-side redistribution structure 106.
Finally, the first one of the first IPD dies 50A may be spaced apart from an edge of the encapsulant 120. In an embodiment the first one of the first IPD dies 50A may be spaced apart a third width W3 that is less than the first width W1, such as the third width W3 being between about 50 μm and about 2000 μm, such as about 500 μm. However, any suitable dimensions may be utilized.
In
In an embodiment the dielectric layer 124 is deposited on the encapsulant 120, the first through vias 116, and the external die contacts 217. In some embodiments, the dielectric layer 124 is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer 124 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 124 is then patterned. The patterning forms openings exposing portions of the first through vias 116 and the external die contacts 217. The patterning may be by an acceptable process, such as by exposing the dielectric layer 124 to light when the dielectric layer 124 is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer 124 is a photo-sensitive material, the dielectric layer 124 can be developed after the exposure.
The metallization pattern 126 is then formed. The metallization pattern 126 includes line portions (also referred to as conductive lines) on and extending along the major surface of the dielectric layer 124. The metallization pattern 126 further includes via portions (also referred to as conductive vias) extending through the dielectric layer 124 to physically and electrically couple the first through vias 116 and the IPD dies 50. As an example to form the metallization pattern 126, a seed layer is formed over the dielectric layer 124 and in the openings extending through the dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern 126. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.
The dielectric layer 128 is deposited on the metallization pattern 126 and dielectric layer 124. The dielectric layer 128 may be formed in a manner similar to the dielectric layer 124, and may be formed of a similar material as the dielectric layer 124. Once formed, the dielectric layer 128 may be patterned in order to expose underlying portions of the metallization pattern 126 using, e.g., a photolithographic masking and etching process. However, any suitable methods and materials may be utilized.
The metallization pattern 130 is then formed. The metallization pattern 130 includes line portions on and extending along the major surface of the dielectric layer 128. The metallization pattern 130 further includes via portions extending through the dielectric layer 128 to physically and electrically couple the metallization pattern 126. The metallization pattern 130 may be formed in a similar manner and of a similar material as the metallization pattern 126. In some embodiments, the metallization pattern 130 has a different size than the metallization pattern 126. For example, the conductive lines and/or vias of the metallization pattern 130 may be wider or thicker than the conductive lines and/or vias of the metallization pattern 126. Further, the metallization pattern 130 may be formed to a greater pitch than the metallization pattern 126.
The dielectric layer 132 is deposited on the metallization pattern 130 and dielectric layer 128. The dielectric layer 132 may be formed in a manner similar to the dielectric layer 124, and may be formed of a similar material as the dielectric layer 124. Once formed, the dielectric layer 132 may be patterned in order to expose underlying portions of the metallization pattern 130 using, e.g., a photolithographic masking and etching process. However, any suitable methods and materials may be utilized.
The metallization pattern 134 is then formed. In the embodiment illustrated the metallization pattern 134 includes only via portions extending through the dielectric layer 132 to physically and electrically couple the metallization pattern 130, although other embodiments may also utilize line portions in addition to the via portions. The metallization pattern 134 may be formed in a similar manner and of a similar material as the metallization pattern 126. However, any suitable methods, such as damascene processes or dual damascene processes, and any suitable materials may be utilized.
The metallization pattern 134 is the topmost metallization pattern of the front-side redistribution structure 122. As such, all of the intermediate metallization patterns of the front-side redistribution structure 122 (e.g., the metallization patterns 126 and 130) are disposed between the metallization pattern 134 and the first IPD dies 50A and 50B. In some embodiments, the metallization pattern 134 has a different size than the metallization patterns 126 and 130. For example, the conductive lines and/or vias of the metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of the metallization patterns 126 and 130. Further, the metallization pattern 134 may be formed to a greater pitch than the metallization pattern 130.
In an embodiment the second IPD dies 50C and 50D may be similar to the first IPD dies 50A and 50B, such as by having a third substrate 503 (similar to the second substrate 203) with deep trench capacitors formed therein and thereon, second external die contacts 505 (similar to the external die contacts 217), and a second passivation layer 511 (similar to the passivation layer 219). However, any suitable structures may be utilized.
In an embodiment the second IPD dies 50C and 50D may be placed into contact with the metallization pattern 134 using, for example, a pick and place process to place the second external die contacts 505 into physical contact with the metallization pattern 134. Once in physical contact, the second IPD dies 50C and 50D may be connected to the metallization pattern 134 using any suitable bonding process, such as fusion bonding, hybrid bonding, metal-to-metal bonding, combinations of these, or the like. However, any suitable bonding process may be utilized.
In an embodiment the second IPD die 50C may have a fifth height H5 of between about 40 μm and about 500 μm, such as about 90 μm. The second IPD die 50D may have a sixth height H6 that may be the same as, larger than, or less than the fifth height H5, such as the sixth height H6 being between about 40 μm and about 500μm, such as about 90 μm. However, any suitable heights may be utilized.
Additionally, the encapsulant 136 may be formed with a seventh height H7 that is greater than both of the fifth height H5 and the sixth height H6. For example, the encapsulant 136 may be formed to have the seventh height H7 to be between about 50 μm and about 700 μm, such as about 100 μm. However, any suitable height may be utilized.
Finally, the first one of the second IPD dies 50C may be spaced apart from an edge of the encapsulant 136. In an embodiment the first one of the second IPD dies 50C may be spaced apart a fourth width W4 that is larger than, smaller than, or equal to third width W3 (within the first bottom layer 301), such as the fourth width W4 being between about 50 μm and about 2000 μm, such as about 500 μm. In embodiments in which the fourth width W4 is larger than the third width W3, the structure may be better able to balance warpages throughout the structure. However, in embodiments in which the fourth width W, is greater than the third width W3, the second IPD dies 50C may be larger, leading to a higher total capacitance. However, any suitable dimensions may be utilized.
Conductive connectors 152 are formed extending through the dielectric layer 108 to contact the metallization pattern 110. In an embodiment the conductive connectors 152 can be placed by initially forming openings through dielectric layer 108 to expose portions of the metallization pattern 110. The openings may be formed, for example, using laser drilling, etching, or the like. The conductive connectors 152 may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the conductive connectors 152 are contact bumps, the conductive connectors 152 may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the conductive connectors 152 is a tin solder bump, the conductive connectors 152 may be formed by initially forming a layer of tin through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape.
In other embodiments the conductive connectors 152 may be conductive pillars, such as copper pillars, and may comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like with a seed layer and a placed and patterned photoresist. In an embodiment, an electroplating process is used wherein the seed layer and the photoresist are submerged or immersed in an electroplating solution such as a copper sulfate (CuSO4) containing solution. The seed layer surface is electrically connected to the negative side of an external DC power supply such that the seed layer functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the seed layer, acquires the dissolved atoms, thereby plating the exposed conductive areas of the seed layer within the opening of the photoresist. Once formed, the photoresist may be removed and the underlying exposed seed layer may be removed.
Additionally, the conductive connectors 152 can be arranged in an array of rows and columns along a bottom of the dielectric layer 108. Further, each row may comprise only ground connections while adjacent rows may comprise only power connections. As such, there are parallel lines of ground connections and power connections along the bottom of the dielectric layer 108. However, any suitable arrangement may be utilized.
Once the second IPD dies 50C and 50D have been encapsulated, a singulation process is performed by sawing along scribe line regions, e.g., between the first package region 100A and other package regions in order to form the first IPD stack 500. The resulting, singulated first IPD stack 500 is from the first package region 100A. However, any suitable singulation process may be utilized.
Once the third redistribution structure 138 has been formed, the first IPD stack 500 may be attached to the third redistribution structure 138. In an embodiment the first IPD stack 500 may be placed into contact with the third redistribution structure 138 using, for example, a pick and place process. Once in physical contact, the first IPD stack 500 may be bonded to the third redistribution structure 138 using any suitable bonding process, such as a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, combinations of these, or the like.
In an embodiment the first functional die 60A and the second functional die 60B may be placed into contact with the third redistribution structure 138 using, for example, a pick and place process, whereby external contacts (similar in some embodiments to conductive connectors 152) are placed in physical contact with conductive portions of the third redistribution structure 138. Once in physical contact, the first functional die 60A and the second functional die 60B may be bonded to the third redistribution structure 138 using any suitable bonding process, such as a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, combinations of these, or the like.
In some embodiments, an underfill 144 is formed between the third redistribution structure 138 and the first functional die 60A, between the third redistribution structure 138 and the second functional die 60B, and between the third redistribution structure 138 and the first IPD stack 500. The underfill 144 may reduce stress and protect the joints resulting from the reflowing of the conductive connectors 152. The underfill 144 may be formed by a capillary flow process after the first functional die 60A, the second functional die 60B, and the first IPD stack 500 are attached, or may be formed by a suitable deposition method before the first functional die 60A, the second functional die 60B, and the first IPD stack 500 are attached.
Once the encapsulant 146 has been placed, second conductive connectors 603 may be placed or formed on an opposite side of the third redistribution structure 138 from the first IPD stack 500. In an embodiment the second conductive connectors 603 may be similar to the conductive connectors 152, such as by being conductive balls such as solder balls or conductive pillars. However, any suitable materials and methods may be utilized.
The substrate 150 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design. The devices may be formed using any suitable methods.
The substrate 150 may also include metallization layers and conductive vias 208 on either side of the insulating core. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In other embodiments, the substrate 150 is substantially free of active and passive devices.
The substrate 150 may have bond pads 204 on a first side of the substrate 150, and bond pads 206 on a second side of the substrate 150, the second side being opposite the first side of the substrate 150, to couple to the second conductive connectors 603. In some embodiments, the bond pads 204 and 206 are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate 150. The recesses may be formed to allow the bond pads 204 and 206 to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads 204 and 206 may be formed on the dielectric layer. In some embodiments, the bond pads 204 and 206 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads 204 and 206 may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads 204 and 206 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.
In an embodiment, the bond pads 204 and bond pads 206 are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the bond pads 204 and 206. Any suitable materials or layers of material that may be used for the bond pads 204 and 206 are fully intended to be included within the scope of the current application.
In some embodiments, an underfill 154 is formed between the first packaged structure 601 and the substrate 150. The underfill 154 may reduce stress and protect the joints resulting from the reflowing of the second conductive connectors 603. The underfill 154 may be formed by a capillary flow process after the structure is attached, or may be formed by a suitable deposition method before the structure is attached.
In some embodiments, the second conductive connectors 603 are reflowed to attach the first packaged structure 601 to the bond pads 206. The second conductive connectors 603 electrically and/or physically couple the structures, including metallization layers 208 in the substrate 150, to the first packaged structure 601. In some embodiments, a solder resist is formed on the substrate core 302. The first packaged structure 601 may be disposed in openings in the solder resist to be electrically and mechanically coupled to the bond pads 206. The solder resist may be used to protect areas of the substrate 150 from external damage.
By utilizing the first IPD stack 500, an increased capacitance can be attached to the overall structure to work with the first functional die 60A and the second functional die 60B. Additionally, this achievement can be obtained without the need for a larger footprint which would negatively impact the overall size of the device. Finally, by choosing the number and size of the individual IPD dies, a precise capacitance can be obtained without requiring a full redesign of the overall structure.
In a particular embodiment the first IPD dies 50A and 50B are bonded to the back-side redistribution structure 106 using the external die contacts 217 and a process similar to the process for bonding the second IPD dies 50C and 50D to the front-side redistribution structure 122 as described above with respect to
Once the first IPD dies 50A and 50B are bonded, the process can be continued as described above with respect to
Once the back-side redistribution structure 106 has been formed, the first through vias 116 may be formed in electrical connection with the back-side redistribution structure 106. In an embodiment the back-side redistribution structure 106 may be formed as described above with respect to
In this embodiment, however, the first through vias 116 are not intended to be the sole connection between the back-side redistribution structure 106 and the front-side redistribution structure 122. As such, the first through vias 116 do not need to be as tall as the first IPD dies 50A and 50B, and are formed to have a smaller height than the first IPD dies 50A and 50B. For example, in this embodiment the first through vias 116 may be formed to have a first thickness T1 of between about 10 μm and about 650 μm, such as about 50 μm. However, any suitable thickness may be utilized.
Further, once the second IPD dies 50C and 50D are bonded to the front-side redistribution structure 122, the second IPD dies 50C and 50D are encapsulated with the encapsulant 136. In an embodiment the encapsulant 136 may be applied as described above with respect to
Finally,
Once the dielectric layer 124 has been exposed, the dielectric layer 124 may be patterned in order to expose portions of the one or more metallization pattern 126. In an embodiment the dielectric layer 124 may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated in
Once the dielectric layer 124 has been patterned, the second external connectors 156 are placed through the dielectric layer 124 and in electrical connection with the front-side redistribution structure 122. The second external connectors 156 may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the second external connectors 156 are tin solder bumps, the second external connectors 156 may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape
In another embodiment, the encapsulant 120 may be an underfill material. In this embodiment the encapsulant 120 may be formed by a capillary flow process after the second external connectors 156 have been bonded to the first through vias 116. However, any suitable method and material may be utilized.
Once the first IPD stack 500 has been formed in this embodiment, the process can be continued as described above with respect to
Once the first bottom layer 301 is formed, a first middle layer 303 is formed over the first bottom layer 301 prior to formation of the first top layer 501. In an embodiment the first middle layer 303 comprises a fourth redistribution layer 305, second through vias 307, third IPD dies 50E and 50F, and a third encapsulant 309. In an embodiment the fourth redistribution layer 305 is formed using similar methods and materials as the front-side redistribution structure 122, described above with respect to
Once the fourth redistribution layer 305 is formed, the second through vias 307 are formed in electrical connection with the fourth redistribution layer 305. In an embodiment the second through vias 307 may be formed using similar methods and materials as the first through vias 116 as described above with respect to
Additionally, once the second through vias 307 have been formed, the third IPD dies 50E and 50F may be placed adjacent to the second through vias 307. In an embodiment the third IPD dies 50E and 50F may be similar to the first IPD dies 50A and 50B (e.g., may be capacitor dies) and may be placed in physical and electrical contact with the fourth redistribution layer 305 using, e.g., a pick and place process. Once in physical contact, the third IPD dies 50E and 50F may be bonded using, e.g., a hybrid bonding process, a metal-to-metal bonding process, a dielectric bonding process, combinations of these, or the like. However, any suitable processes may be utilized.
Once the first middle layer 303 has been formed, the first top layer 501 may be formed over the first middle layer 303 and the conductive connectors 152 are placed in connection with the first bottom layer 301. In an embodiment the first top layer 501 may be formed as described above with respect to
In this embodiment, the overall first IPD stack 500 with five layers may have an overall height H0 of 670 μm (e.g., 100 μm per IPD die plus 30 μm per redistribution layer and molding compound on either side of four of the IPD dies, and plus 50 μm for the redistribution layer and molding compound on either side of the first top layer 501). Additionally, in embodiments in which the individual IPD dies may each have a capacitance of 1.1 μF/mm2 and the IPD dies have an active area of 32.27 mm2, then each of the individual layers may have a single layer capacitance of 35.5 μF. As such, the overall capacitance of the first IPD stack 500 in this particular embodiment is about 178 μF. However, any suitable parameters may be utilized.
In an embodiment the first functional die 60A may have a first dimension D1 of between about 10 mm and about 100 mm, such as about 33 mm, and a second dimension D2 of between about 8 mm and about 95 mm, such as about 25 mm. Similarly, each of the second functional dies 60B may have a third dimension D3 of between about 3 mm and about 20 mm, such as about 12 mm, and a fourth dimension D4 of between about 2 mm and about 20 mm, such as about 8 mm. However, any suitable dimensions may be utilized.
With respect to the first IPD stack 500, the first IPD stack 500 may be formed to have dimensions that fit within the small footprint left by the first functional die 60A and the second functional dies 60B. As such, the first IPD stack 500 may have a fifth dimension D5 of between about 2 mm and about 20 mm, such as about 8 mm, while having a sixth dimension D6 of between about 2 mm and about 20 mm, such as about 8 mm. However, any suitable dimensions may be utilized.
By packaging multiple IPD dies within a package utilizing the first IPD stack 500, a larger parameter (e.g., a larger capacitance) can be obtained without also requiring a larger footprint. Further, the desire capacitance can be precisely tuned using both a desired number of layers as well as a desired number and/or size of IPD dies. As such, any desired capacitance can be achieved without sacrificing size.
In accordance with an embodiment, a semiconductor device includes: a first integrated passive device (IPD); a first molding compound encapsulating the first IPD; a redistribution structure over and electrically connected to the first IPD; a second IPD on an opposing side of the redistribution structure as the first IPD, wherein the second IPD is electrically connected to the first IPD by the redistribution structure; and a second molding compound encapsulating the second IPD. In an embodiment a face of the first IPD faces a face of the second IPD. In an embodiment a face of the first IPD faces a back of the second IPD. In an embodiment the semiconductor device further includes a conductive via extending through the first molding compound. In an embodiment the semiconductor device further includes a conductive feature extending through the first molding compound, the conductive feature includes: a conductive via; and a solder region on the conductive via. In an embodiment the first IPD is electrically connected to the redistribution structure by a copper pillar. In an embodiment the first IPD is electrically connected to the redistribution structure by a solder region.
In accordance with another embodiment, a semiconductor device includes: a first redistribution structure; a first functional die bonded to the first redistribution structure; and a first integrated passive device stack bonded to the first redistribution structure, the first integrated passive device stack includes: a second redistribution structure; a first integrated passive device over the second redistribution structure; a third redistribution structure over the first integrated passive device, the third redistribution structure being connected to the second redistribution structure by first through vias; and a second integrated passive device over the third redistribution structure. In an embodiment the semiconductor device further includes: a third integrated passive device between the second redistribution structure and the third redistribution structure; and a first encapsulant surrounding the third integrated passive device and the first integrated passive device. In an embodiment the first through vias comprise copper pillars. In an embodiment the first through vias includes: copper pillars; and solder balls in physical contact with the copper pillars. In an embodiment the first integrated passive device and the second integrated passive device are configured in a face-to-face configuration. In an embodiment the first integrated passive device and the second integrated passive device are configured in a back-to-face configuration. In an embodiment the first integrated passive device stack further includes: a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second through vias; and a third integrated passive device over the fourth redistribution structure.
In accordance with yet another embodiment, a method of manufacturing a semiconductor device, the method includes: forming a first redistribution structure over a carrier wafer; forming through vias over the first redistribution structure; placing a first integrated passive device on the first redistribution structure adjacent to the through vias; encapsulating the first integrated passive device and the through vias with an encapsulant; forming a second redistribution structure over the encapsulant and in electrical connection with the through vias; and placing a second integrated passive device on the second redistribution structure and in electrical connection with the through vias. In an embodiment the placing the first integrated passive device on the first redistribution structure places the first integrated passive device in electrical connection with the first redistribution structure. In an embodiment the placing the first integrated passive device on the first redistribution structure utilizes an adhesive. In an embodiment the placing the first integrated passive device places a integrated passive capacitor. In an embodiment the method further includes bonding the first redistribution structure to a third redistribution layer. In an embodiment the method further includes: bonding a first functional die to the third redistribution layer; and encapsulating the first functional die in an encapsulant.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a continuation of U.S. patent application Ser. No. 17/873,387, filed on Jul. 26, 2022, entitled “Semiconductor Devices with Integrated Passive Devices and Methods of Manufacture,” which is a divisional of U.S. patent application Ser. No. 16/900,174, filed on Jun. 12, 2020, entitled “Semiconductor Devices with Integrated Passive Devices,” which claims the benefit of U.S. Provisional Application No. 62/939,147, filed on Nov. 22, 2019, which applications are hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62939147 | Nov 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16900174 | Jun 2020 | US |
| Child | 17873387 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17873387 | Jul 2022 | US |
| Child | 18787615 | US |
