Patent Application
20200373225
The present invention is related to a semiconductor integrated circuit, especially a semiconductor integrated circuit with a substrate via hole having a small aspect ratio.
Please refer to
When the uniformity of the thickness of the seed metal layer 91 formed on the inner surface 94 of the substrate via hole 93 is poor, it is possible that the thickness of the seed metal layer 91 in some area is too thin. It will cause the peeling phenomenon between the seed metal layer 91 and the semiconductor substrate 90 under high humidity and high temperature reliability test and cause damage to the reliability of the semiconductor integrated circuit 9. Furthermore, when the uniformity of the thickness of the seed metal layer 91 and the uniformity of the thickness of the backside metal layer 92 are poor, it will raise the resistance value of the seed metal layer 91 and the backside metal layer 92, especially, the resistance value of the seed metal layer 91 and the backside metal layer 92 formed in the substrate via hole 93 is particularly raised. Thereby, the heat dissipation of the semiconductor integrated circuit 9 of conventional technology is significantly raised such that the power consumption of the semiconductor integrated circuit 9 of the conventional technology is significantly raised. Moreover, since the resistance value of the seed metal layer 91 and the backside metal layer 92 is significantly raised, the heat is accumulated, especially in the substrate via hole 93. It is more possible to cause the peeling phenomenon between the seed metal layer 91 and the semiconductor substrate 90, and to cause damage to the reliability of the semiconductor integrated circuit 9. Furthermore, the seed metal layer 91 and the backside metal layer 92 formed in the substrate via hole 93 have an inductance value. Since the thickness of the seed metal layer 91 and the thickness of the backside metal layer 92 formed in the substrate via hole 93 are particularly non-uniform, such that a variation of the inductance value of the seed metal layer 91 and the backside metal layer 92 (in the substrate via hole 93) is significantly great. It affects the performance and the characteristics of the semiconductor integrated circuit 9 of conventional technology. Especially, when the semiconductor integrated circuit 9 of conventional technology is a high frequency circuit and the substrate via hole 93 is a hot via, the variation of the inductance value of the seed metal layer 91 and the backside metal layer 92 (in the substrate via hole 93) affects the performance and the characteristics of high frequency circuits greatly.
Accordingly, the present invention has developed a new design which may avoid the above mentioned drawbacks, may significantly enhance the performance of the devices and may take into account economic considerations. Therefore, the present invention then has been invented.
The main technical problems that the present invention is seeking to solve are: 1. To improve the thickness uniformity of the seed metal layer and the back metal layer to avoid the peeling phenomenon between the seed metal layer and the semiconductor substrate, and avoid damaging to the reliability of the semiconductor integrated circuit; and to reduce the heat dissipation of the semiconductor integrated circuit to reduce the power consumption of the semiconductor integrated circuit; and 2. To reduce the variation of the inductance value of the seed metal layer and the back metal layer to avoid affecting the performance and the characteristics of the semiconductor integrated circuit.
In order to solve the problems mentioned the above and to achieve the expected effect, the present invention provides a semiconductor integrated circuit which comprises a semiconductor substrate, a first circuit layout and a second circuit layout. The semiconductor substrate has a first substrate via hole, a top surface and a bottom surface, the first substrate via hole has an inner surface, the inner surface of the first substrate via hole includes a bottom and a surrounding, the surrounding of the inner surface of the first substrate via hole is at least partially defined by the semiconductor substrate. The first circuit layout comprises a front-side metal layer. The front-side metal layer is formed on the top surface of the semiconductor substrate, wherein the bottom of the inner surface of the first substrate via hole is at least partially defined by the front-side metal layer. The second circuit layout comprises a seed metal layer and a backside metal layer. The seed metal layer is formed on the inner surface of the first substrate via hole and the bottom surface of the semiconductor substrate, wherein the seed metal layer has an outer surface. The backside metal layer is formed on the outer surface of the seed metal layer. The first substrate via hole has an aspect ratio, the aspect ratio of the first substrate via hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside metal layer is improved. Thereby, the peeling phenomenon between the seed metal layer and the semiconductor substrate can be avoided, and thereby avoiding damage to the reliability of the semiconductor integrated circuit can be avoided. Moreover, the heat dissipation of the semiconductor integrated circuit is significantly reduced such that the power consumption of the semiconductor integrated circuit is significantly reduced.
The present invention further provides a semiconductor integrated circuit which comprises a semiconductor substrate, a first circuit layout and a second circuit layout. The semiconductor substrate has a first substrate via hole, a top surface and a bottom surface, the first substrate via hole has an inner surface, the inner surface of the first substrate via hole includes a bottom and a surrounding, the surrounding of the inner surface of the first substrate via hole is at least partially defined by the semiconductor substrate. The first circuit layout comprises a front-side metal layer. The front-side metal layer is formed on the top surface of the semiconductor substrate, wherein the bottom of the inner surface of the first substrate via hole is at least partially defined by the front-side metal layer. The second circuit layout comprises a seed metal layer and a backside metal layer. The seed metal layer is formed on the inner surface of the first substrate via hole and the bottom surface of the semiconductor substrate, wherein the seed metal layer has an outer surface. The backside metal layer is formed on the outer surface of the seed metal layer. The first substrate via hole has a depth and a width, the depth of the first substrate via hole is greater than or equal to 10 μm and less than or equal to 40 μm, the width of the first substrate via hole is greater than or equal to 5 μm and less than or equal to 50 μm, thereby a thickness uniformity of the backside metal layer is improved. Thereby, the peeling phenomenon between the seed metal layer and the semiconductor substrate can be avoided, and thereby avoiding damage to the reliability of the semiconductor integrated circuit can be avoided. Moreover, the heat dissipation of the semiconductor integrated circuit is significantly reduced such that the power consumption of the semiconductor integrated circuit is significantly reduced.
In an embodiment, the seed metal layer includes a first-substrate-via-hole-bottom seed metal layer formed on the bottom of the inner surface of the first substrate via hole, a first-substrate-via-hole-surrounding seed metal layer formed on the surrounding of the inner surface of the first substrate via hole, and a first-substrate-bottom-surface seed metal layer formed on the bottom surface of the semiconductor substrate; wherein the outer surface of the seed metal layer includes an outer surface of the first-substrate-via-hole-bottom seed metal layer, an outer surface of the first-substrate-via-hole-surrounding seed metal layer, and an outer surface of the first-substrate-bottom-surface seed metal layer; wherein the backside metal layer includes a first-substrate-via-hole-bottom backside metal layer formed on the outer surface of the first-substrate-via-hole-bottom seed metal layer, a first-substrate-via-hole-surrounding backside metal layer formed on the outer surface of the first-substrate-via-hole-surrounding seed metal layer, and a first-substrate-bottom-surface backside metal layer formed on the outer surface of the first-substrate-bottom-surface seed metal layer; wherein the second circuit layout includes a first-substrate-via-hole-bottom connection part, a first substrate via hole inductor, and a first electrical connection part; the first-substrate-via-hole-bottom connection part includes the first-substrate-via-hole-bottom seed metal layer and the first-substrate-via-hole-bottom backside metal layer; the first substrate via hole inductor includes the first-substrate-via-hole-surrounding seed metal layer and the first-substrate-via-hole-surrounding backside metal layer; the first electrical connection part includes the first-substrate-bottom-surface seed metal layer and the first-substrate-bottom-surface backside metal layer; wherein the first substrate via hole inductor is a hot via inductor.
The present invention further provides a semiconductor integrated circuit which comprises a semiconductor substrate, a first circuit layout and a second circuit layout. The semiconductor substrate has a first substrate via hole, a top surface and a bottom surface, the first substrate via hole has an inner surface, the inner surface of the first substrate via hole includes a bottom and a surrounding, the surrounding of the inner surface of the first substrate via hole is at least partially defined by the semiconductor substrate. The first circuit layout comprises a front-side metal layer. The front-side metal layer is formed on the top surface of the semiconductor substrate, wherein the bottom of the inner surface of the first substrate via hole is at least partially defined by the front-side metal layer. The second circuit layout comprises a seed metal layer and a backside metal layer. The seed metal layer is formed on the inner surface of the first substrate via hole and the bottom surface of the semiconductor substrate, wherein the seed metal layer includes a first-substrate-via-hole-bottom seed metal layer formed on the bottom of the inner surface of the first substrate via hole, a first-substrate-via-hole-surrounding seed metal layer formed on the surrounding of the inner surface of the first substrate via hole, and a first-substrate-bottom-surface seed metal layer formed on the bottom surface of the semiconductor substrate; wherein the first-substrate-via-hole-bottom seed metal layer is electrically connected to the front-side metal layer; wherein the seed metal layer has an outer surface; wherein the outer surface of the seed metal layer includes an outer surface of the first-substrate-via-hole-bottom seed metal layer, an outer surface of the first-substrate-via-hole-surrounding seed metal layer, and an outer surface of the first-substrate-bottom-surface seed metal layer. The backside metal layer is formed on the outer surface of the seed metal layer; wherein the backside metal layer includes a first-substrate-via-hole-bottom backside metal layer formed on the outer surface of the first-substrate-via-hole-bottom seed metal layer, a first-substrate-via-hole-surrounding backside metal layer formed on the outer surface of the first-substrate-via-hole-surrounding seed metal layer, and a first-substrate-bottom-surface backside metal layer formed on the outer surface of the first-substrate-bottom-surface seed metal layer. The second circuit layout includes a first-substrate-via-hole-bottom connection part, a first substrate via hole inductor, and a first electrical connection part; the first-substrate-via-hole-bottom connection part includes the first-substrate-via-hole-bottom seed metal layer and the first-substrate-via-hole-bottom backside metal layer; the first substrate via hole inductor includes the first-substrate-via-hole-surrounding seed metal layer and the first-substrate-via-hole-surrounding backside metal layer; the first electrical connection part includes the first-substrate-bottom-surface seed metal layer and the first-substrate-bottom-surface backside metal layer; wherein the first substrate via hole inductor is a hot via inductor.
In an embodiment, the first substrate via hole has a width, the width of the first substrate via hole is greater than or equal to 5 μm and less than or equal to 50 μm.
In an embodiment, the first substrate via hole has a depth, the depth of the first substrate via hole is greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the semiconductor integrated circuit is electrically connected to an RF signal output terminal or an RF signal input terminal through the first electrical connection part.
In an embodiment, the first substrate via hole inductor has a first inductance value, wherein the first inductance value of the first substrate via hole inductor is greater than or equal to 0.1 pH (picohenry) and less than or equal to 17.0 pH.
In an embodiment, the front-side metal layer comprises a first part and a second part, the bottom of the inner surface of the first substrate via hole is at least partially defined by the first part of the front-side metal layer; the first-substrate-via-hole-bottom seed metal layer is electrically connected to the first part of the front-side metal layer; wherein the semiconductor substrate further includes a second substrate via hole, the second substrate via hole has an inner surface, the inner surface of the second substrate via hole includes a bottom and a surrounding, the surrounding of the inner surface of the second substrate via hole is at least partially defined by the semiconductor substrate, the bottom of the inner surface of the second substrate via hole is at least partially defined by the second part of the front-side metal layer; the bottom surface of the semiconductor substrate comprises a first area, a second area, and a separation area, the separation area separates the first area of the bottom surface of the semiconductor substrate from the second area of the bottom surface of the semiconductor substrate; wherein the seed metal layer is formed on the inner surface of the first substrate via hole, the inner surface of the second substrate via hole, the first area of the bottom surface of the semiconductor substrate, and the second area of the bottom surface of the semiconductor substrate; the first-substrate-bottom-surface seed metal layer is formed on the first area of the bottom surface of the semiconductor substrate; the seed metal layer further includes a second-substrate-via-hole-bottom seed metal layer formed on the bottom of the inner surface of the second substrate via hole, a second-substrate-via-hole-surrounding seed metal layer formed on the surrounding of the inner surface of the second substrate via hole, and a second-substrate-bottom-surface seed metal layer formed on the second area of the bottom surface of the semiconductor substrate; the second-substrate-via-hole-bottom seed metal layer is electrically connected to the second part of the front-side metal layer; wherein the outer surface of the seed metal layer further includes an outer surface of the second-substrate-via-hole-bottom seed metal layer, an outer surface of the second-substrate-via-hole-surrounding seed metal layer, and an outer surface of the second-substrate-bottom-surface seed metal layer; wherein the backside metal layer further includes a second-substrate-via-hole-bottom backside metal layer formed on the outer surface of the second-substrate-via-hole-bottom seed metal layer, a second-substrate-via-hole-surrounding backside metal layer formed on the outer surface of the second-substrate-via-hole-surrounding seed metal layer, and a second-substrate-bottom-surface backside metal layer formed on the outer surface of the second-substrate-bottom-surface seed metal layer; wherein the second circuit layout further includes a second-substrate-via-hole-bottom connection part, a second substrate via hole inductor, and a second electrical connection part; the second-substrate-via-hole-bottom connection part includes the second-substrate-via-hole-bottom seed metal layer and the second-substrate-via-hole-bottom backside metal layer; the second substrate via hole inductor includes the second-substrate-via-hole-surrounding seed metal layer and the second-substrate-via-hole-surrounding backside metal layer; the second electrical connection part includes the second-substrate-bottom-surface seed metal layer and the second-substrate-bottom-surface backside metal layer.
In an embodiment, the second substrate via hole inductor is a hot via inductor.
In an embodiment, the semiconductor integrated circuit is electrically connected to one of an RF signal output terminal and an RF signal input terminal through the first electrical connection part, and the semiconductor integrated circuit is electrically connected to the other of the RF signal output terminal and the RF signal input terminal through the second electrical connection part.
In an embodiment, the second substrate via hole inductor is a non-hot via inductor, the semiconductor integrated circuit is grounded through the second electrical connection part.
In an embodiment, the second substrate via hole has an aspect ratio, the aspect ratio of the second substrate via hole is greater than or equal to 0.2 and less than or equal to 3.
In an embodiment, the second substrate via hole has a width, the width of the second substrate via hole is greater than or equal to 5 μm and less than or equal to 50 μm.
In an embodiment, the second substrate via hole has a depth, the depth of the second substrate via hole is greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the second substrate via hole inductor has a second inductance value, wherein the second inductance value of the second substrate via hole inductor is greater than or equal to 0.1 pH and less than or equal to 17.0 pH.
In an embodiment, the semiconductor integrated circuit is an RF circuit.
In an embodiment, the semiconductor substrate has a thickness, the thickness of the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the seed metal layer has a thickness, the thickness of the seed metal layer is greater than or equal to 0.1 μm and less than or equal to 1 μm.
In an embodiment, the backside metal layer has a thickness, the thickness of the backside metal layer is greater than or equal to 1 μm and less than or equal to 10 μm.
In an embodiment, the seed metal layer is made by at least one material selected from the group consisting of: Pd, Pd alloy, Au, Au alloy, Ni, Ni alloy, Co, Co alloy, Cr, Cr alloy, Cu, Cu alloy, Pt, Pt alloy, Sn, Sn alloy, Rh and Rh alloy.
In an embodiment, the backside metal layer is made by at least one material selected from the group consisting of: Au and Cu.
In an embodiment, the semiconductor substrate is made by one material selected from the group consisting of: GaAs, InP, GaN, sapphire and SiC.
The present invention further provides a circuit layout method for semiconductor integrated circuit, which comprises following steps of: Step A0: designing a first-substrate-via-hole shape, a first-substrate-via-hole depth and a first-substrate-via-hole width of a first substrate via hole, a seed-metal-layer thickness of a seed metal layer, and a backside-metal-layer thickness of a backside metal layer, such that a first substrate via hole inductor has a first inductance value; Step A1: forming a first circuit layout on a top surface of a semiconductor substrate, wherein the first circuit layout comprises a front-side metal layer; Step B1: etching the semiconductor substrate to form the first substrate via hole such that the first substrate via hole has the first-substrate-via-hole shape, the first-substrate-via-hole depth, and the first-substrate-via-hole width, wherein the first substrate via hole has an inner surface, the inner surface of the first substrate via hole includes a bottom and a surrounding, wherein the bottom of the inner surface of the first substrate via hole is at least partially defined by the front-side metal layer, the surrounding of the inner surface of the first substrate via hole is at least partially defined by the semiconductor substrate; and Step C1: forming a second circuit layout, which comprises following steps of: Step C10: forming the seed metal layer on the inner surface of the first substrate via hole and a bottom surface of the semiconductor substrate such that the seed metal layer has the seed-metal-layer thickness, wherein the seed metal layer includes a first-substrate-via-hole-bottom seed metal layer formed on the bottom of the inner surface of the first substrate via hole, a first-substrate-via-hole-surrounding seed metal layer formed on the surrounding of the inner surface of the first substrate via hole, and a first-substrate-bottom-surface seed metal layer formed on the bottom surface of the semiconductor substrate; wherein the first-substrate-via-hole-bottom seed metal layer is electrically connected to the front-side metal layer; wherein the seed metal layer has an outer surface; wherein the outer surface of the seed metal layer includes an outer surface of the first-substrate-via-hole-bottom seed metal layer, an outer surface of the first-substrate-via-hole-surrounding seed metal layer, and an outer surface of the first-substrate-bottom-surface seed metal layer; and Step C11: forming the backside metal layer on the outer surface of the seed metal layer such that the backside metal layer has the backside-metal-layer thickness, wherein the backside metal layer includes a first-substrate-via-hole-bottom backside metal layer formed on the outer surface of the first-substrate-via-hole-bottom seed metal layer, a first-substrate-via-hole-surrounding backside metal layer formed on the outer surface of the first-substrate-via-hole-surrounding seed metal layer, and a first-substrate-bottom-surface backside metal layer formed on the outer surface of the first-substrate-bottom-surface seed metal layer; wherein the second circuit layout includes a first-substrate-via-hole-bottom connection part, a first substrate via hole inductor, and a first electrical connection part; the first-substrate-via-hole-bottom connection part includes the first-substrate-via-hole-bottom seed metal layer and the first-substrate-via-hole-bottom backside metal layer; the first substrate via hole inductor includes the first-substrate-via-hole-surrounding seed metal layer and the first-substrate-via-hole-surrounding backside metal layer; the first electrical connection part includes the first-substrate-bottom-surface seed metal layer and the first-substrate-bottom-surface backside metal layer.
In an embodiment, the first substrate via hole has an aspect ratio, the aspect ratio of the first substrate via hole is greater than or equal to 0.2 and less than or equal to 3.
In an embodiment, the first-substrate-via-hole width is greater than or equal to 5 μm and less than or equal to 50 μm.
In an embodiment, the first-substrate-via-hole depth is greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the first inductance value of the first substrate via hole inductor is greater than or equal to 0.1 pH and less than or equal to 17.0 pH.
In an embodiment, the first substrate via hole inductor is a hot via inductor.
In an embodiment, the semiconductor integrated circuit is electrically connected to an RF signal output terminal or an RF signal input terminal through the first electrical connection part.
In an embodiment, the first substrate via hole inductor is a non-hot via inductor, the semiconductor integrated circuit is grounded through the first electrical connection part.
In an embodiment, the front-side metal layer comprises a first part and a second part, the bottom of the inner surface of the first substrate via hole is at least partially defined by the first part of the front-side metal layer; the first-substrate-via-hole-bottom seed metal layer is electrically connected to the first part of the front-side metal layer; wherein the Step A10 further comprises a following step of: designing a second-substrate-via-hole shape, a second-substrate-via-hole depth and a second-substrate-via-hole width of a second substrate via hole such that a second substrate via hole inductor has a second inductance value; wherein the Step B1 further comprises a following step of: etching the semiconductor substrate to form the second substrate via hole such that the second substrate via hole has the second-substrate-via-hole shape, the second-substrate-via-hole depth, and the second-substrate-via-hole width, wherein the second substrate via hole has an inner surface, the inner surface of the second substrate via hole includes a bottom and a surrounding, wherein the bottom of the inner surface of the second substrate via hole is at least partially defined by the second part of the front-side metal layer, the surrounding of the inner surface of the second substrate via hole is at least partially defined by the semiconductor substrate; wherein the bottom surface of the semiconductor substrate comprises a first area, a second area, and a separation area, the separation area separates the first area of the bottom surface of the semiconductor substrate from the second area of the bottom surface of the semiconductor substrate; wherein the seed metal layer is formed on the inner surface of the first substrate via hole, the inner surface of the second substrate via hole, the first area of the bottom surface of the semiconductor substrate, and the second area of the bottom surface of the semiconductor substrate; the first-substrate-bottom-surface seed metal layer is formed on the first area of the bottom surface of the semiconductor substrate; the seed metal layer further includes a second-substrate-via-hole-bottom seed metal layer formed on the bottom of the inner surface of the second substrate via hole, a second-substrate-via-hole-surrounding seed metal layer formed on the surrounding of the inner surface of the second substrate via hole, and a second-substrate-bottom-surface seed metal layer formed on the second area of the bottom surface of the semiconductor substrate; the second-substrate-via-hole-bottom seed metal layer is electrically connected to the second part of the front-side metal layer; wherein the outer surface of the seed metal layer further includes an outer surface of the second-substrate-via-hole-bottom seed metal layer, an outer surface of the second-substrate-via-hole-surrounding seed metal layer, and an outer surface of the second-substrate-bottom-surface seed metal layer; wherein the backside metal layer is formed on the outer surface of the first-substrate-via-hole-bottom seed metal layer, the outer surface of the first-substrate-via-hole-surrounding seed metal layer, the outer surface of the first-substrate-bottom-surface seed metal layer, the outer surface of the second-substrate-via-hole-bottom seed metal layer, the outer surface of the second-substrate-via-hole-surrounding seed metal layer, and the outer surface of the second-substrate-bottom-surface seed metal layer; wherein the backside metal layer further includes a second-substrate-via-hole-bottom backside metal layer formed on the outer surface of the second-substrate-via-hole-bottom seed metal layer, a second-substrate-via-hole-surrounding backside metal layer formed on the outer surface of the second-substrate-via-hole-surrounding seed metal layer, and a second-substrate-bottom-surface backside metal layer formed on the outer surface of the second-substrate-bottom-surface seed metal layer; wherein the second circuit layout further includes a second-substrate-via-hole-bottom connection part, a second substrate via hole inductor, and a second electrical connection part; the second-substrate-via-hole-bottom connection part includes the second-substrate-via-hole-bottom seed metal layer and the second-substrate-via-hole-bottom backside metal layer; the second substrate via hole inductor includes the second-substrate-via-hole-surrounding seed metal layer and the second-substrate-via-hole-surrounding backside metal layer; the second electrical connection part includes the second-substrate-bottom-surface seed metal layer and the second-substrate-bottom-surface backside metal layer.
In an embodiment, the second substrate via hole has an aspect ratio, the aspect ratio of the second substrate via hole is greater than or equal to 0.2 and less than or equal to 3.
In an embodiment, the second-substrate-via-hole width is greater than or equal to 5 μm and less than or equal to 50 μm.
In an embodiment, the second-substrate-via-hole depth is greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the second inductance value of the second substrate via hole inductor is greater than or equal to 0.1 pH and less than or equal to 17.0 pH.
In an embodiment, the second substrate via hole inductor is a hot via inductor.
In an embodiment, the semiconductor integrated circuit is electrically connected to one of an RF signal output terminal and an RF signal input terminal through the second electrical connection part.
In an embodiment, the first substrate via hole inductor and the second substrate via hole inductor are respectively a hot via inductor.
In an embodiment, the semiconductor integrated circuit is electrically connected to one of an RF signal output terminal and an RF signal input terminal through the first electrical connection part, and the semiconductor integrated circuit is electrically connected to the other of the RF signal output terminal and the RF signal input terminal through the second electrical connection part.
In an embodiment, the second substrate via hole inductor is a non-hot via inductor, the semiconductor integrated circuit is grounded through the second electrical connection part.
In an embodiment, the semiconductor integrated circuit is an RF circuit.
In an embodiment, after the Step A1 and before the Step B1, the circuit layout method further comprises a following step of: thinning the semiconductor substrate such that the semiconductor substrate has a thickness greater than or equal to 10 μm and less than or equal to 40 μm.
In an embodiment, the seed-metal-layer thickness of the seed metal layer is greater than or equal to 0.1 μm and less than or equal to 1 μm.
In an embodiment, the backside-metal-layer thickness of the backside metal layer is greater than or equal to 1 μm and less than or equal to 10 μm.
In an embodiment, the seed metal layer is made by at least one material selected from the group consisting of: Pd, Pd alloy, Au, Au alloy, Ni, Ni alloy, Co, Co alloy, Cr, Cr alloy, Cu, Cu alloy, Pt, Pt alloy, Sn, Sn alloy, Rh and Rh alloy.
In an embodiment, the backside metal layer is made by at least one material selected from the group consisting of: Au and Cu.
In an embodiment, the semiconductor substrate is made by one material selected from the group consisting of: GaAs, InP, GaN, sapphire and SiC.
For further understanding the characteristics and effects of the present invention, some preferred embodiments referred to drawings are in detail described as follows.
Please refer to
the aspect ratio=the depth D1/the width W2. When the cross-sectional view is taken along the section line, wherein the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 3 (i.e. 0.2≤the aspect ratio≤3), the aspect ratio of the substrate via hole 13 is small enough, so that when forming the seed metal layer 20 and the backside metal layer 30, the seed metal layer 20 can be uniformly deposited on the inner surface 14 of the substrate via hole 13 and the bottom surface 12 of the semiconductor substrate 10 and the backside metal layer 30 can be uniformly deposited on the outer surface 50 of the seed metal layer 20 (including the outer surface 51 of the substrate-via-hole-bottom seed metal layer 21, the outer surface 57 of the substrate-via-hole-surrounding seed metal layer 27, and the outer surface 52 of the substrate-bottom-surface seed metal layer 22), respectively. Thereby a thickness uniformity of the seed metal layer 20 (including the substrate-via-hole-bottom seed metal layer 21, the substrate-via-hole-surrounding seed metal layer 27, and the substrate-bottom-surface seed metal layer 22) can be significantly improved, and a thickness uniformity of the backside metal layer 30 (including the substrate-via-hole-bottom backside metal layer 31, the substrate-via-hole-surrounding backside metal layer 37, and the substrate-bottom-surface backside metal layer 32) can also be significantly improved too. Since the thickness uniformity of the seed metal layer 20 and the thickness uniformity of the backside metal layer 30 are both significantly improved such that a resistance of the second circuit layout 7 (including the seed metal layer 20 and the backside metal layer 30) is significantly reduced. Thereby, the heat dissipation of the semiconductor integrated circuit 1 of the present invention can be significantly reduced such that the power consumption of the semiconductor integrated circuit 1 of the present invention can be significantly reduced. Moreover, the peeling phenomenon between the seed metal layer 20 and the semiconductor substrate 10 can be prevented and thereby avoiding damage to the reliability of the semiconductor integrated circuit 1 of the present invention.
In some preferable embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 40 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 8 μm and less than or equal to 40 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 13 μm and less than or equal to 40 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 15 μm and less than or equal to 40 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 35 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 30 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 25 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 20 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 45 μm. In some embodiments, the depth D1 of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 50 μm.
In some preferable embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 45 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 35 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 30 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 25 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 8 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 10 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 13 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 15 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 20 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 25 μm and less than or equal to 50 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 55 μm. In some embodiments, the width of the substrate via hole 13 is greater than or equal to 5 μm and less than or equal to 60 μm.
In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.1 and less than or equal to 3. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.3 and less than or equal to 3. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.4 and less than or equal to 3. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.5 and less than or equal to 3. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 3.2. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 2.8. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 2.6. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 2.4. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 2.2. In some embodiments, the aspect ratio of the substrate via hole 13 is greater than or equal to 0.2 and less than or equal to 2.
In some embodiments, the structure is basically is basically the same as the structure of the embodiment of
In the embodiment of
In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.01 pH (picohenry) and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.05 pH and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.15 pH and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.2 pH and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.25 pH and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.3 pH and less than or equal to 17.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 25.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 20.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 15.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 13.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 11.0 pH. In some embodiments, the inductance value of the substrate via hole inductor 70 is greater than or equal to 0.1 pH and less than or equal to 9.0 pH.
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In some preferable embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 40 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 8 μm and less than or equal to 40 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 13 μm and less than or equal to 40 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 15 μm and less than or equal to 40 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 35 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 25 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 20 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 45 μm. In some embodiments, the depth D2 of the first substrate via hole 601 and the depth D3 of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 50 μm.
In some preferable embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 40 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 8 μm and less than or equal to 40 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 13 μm and less than or equal to 40 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 15 μm and less than or equal to 40 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 35 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 25 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 20 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 45 μm. In some embodiments, the depth D4 of the second substrate via hole 641 and the depth D5 of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 50 μm.
In some preferable embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 45 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 35 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 30 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 25 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 8 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 10 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 13 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 15 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 20 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 25 μm and less than or equal to 50 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 55 μm. In some embodiments, the width of the first substrate via hole 601 and the width of the first substrate via hole 602 are greater than or equal to 5 μm and less than or equal to 60 μm.
In some preferable embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 45 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 35 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 30 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 25 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 8 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 10 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 13 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 15 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 20 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 25 μm and less than or equal to 50 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 55 μm. In some embodiments, the width of the second substrate via hole 641 and the width of the second substrate via hole 642 are greater than or equal to 5 μm and less than or equal to 60 μm.
In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.1 and less than or equal to 3. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.3 and less than or equal to 3. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.4 and less than or equal to 3. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.5 and less than or equal to 3. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 3.2. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 2.8. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 2.6. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 2.4. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 2.2. In some embodiments, the aspect ratio of the first substrate via hole 601 and the aspect ratio of the first substrate via hole 602 are greater than or equal to 0.2 and less than or equal to 2.
In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.1 and less than or equal to 3. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.3 and less than or equal to 3. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.4 and less than or equal to 3. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.5 and less than or equal to 3. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 3.2. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 2.8. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 2.6. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 2.4. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 2.2. In some embodiments, the aspect ratio of the second substrate via hole 641 and the aspect ratio of the second substrate via hole 642 are greater than or equal to 0.2 and less than or equal to 2.
In some embodiments, the structure is basically the same as the structure of the embodiment of
In the embodiment of
In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.01 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.05 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.15 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.2 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.25 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.3 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 25.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 20.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 15.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 13.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 11.0 pH, respectively. In some embodiments, the inductance values of the first substrate via hole inductor 721 and the first substrate via hole inductor 722 are greater than or equal to 0.1 pH and less than or equal to 9.0 pH, respectively.
In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.01 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.05 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.15 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.2 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.25 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.3 pH and less than or equal to 17.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 25.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 20.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 15.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 13.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 11.0 pH, respectively. In some embodiments, the inductance values of the second substrate via hole inductor 741 and the second substrate via hole inductor 742 are greater than or equal to 0.1 pH and less than or equal to 9.0 pH, respectively.
In some preferable embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 40 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 5 μm and less than or equal to 40 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 8 μm and less than or equal to 40 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 13 μm and less than or equal to 40 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 15 μm and less than or equal to 40 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 35 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 30 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 25 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 20 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 45 μm. In some embodiments, the thickness T of the semiconductor substrate 10 is greater than or equal to 10 μm and less than or equal to 50 μm.
In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 1 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 0.9 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 0.8 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 0.7 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 0.6 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.1 μm and less than or equal to 0.5 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.2 μm and less than or equal to 1 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.3 μm and less than or equal to 1 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.4 μm and less than or equal to 1 μm. In some embodiments, the thickness of the seed metal layer 20 is greater than or equal to 0.5 μm and less than or equal to 1 μm.
In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 10 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 9 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 8 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 7 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 6 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 1 μm and less than or equal to 5 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 2 μm and less than or equal to 10 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 3 μm and less than or equal to 10 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 4 μm and less than or equal to 10 μm. In some embodiments, the thickness of the backside metal layer 30 is greater than or equal to 5 μm and less than or equal to 10 μm.
As disclosed in the above description and attached drawings, the present invention can provide a semiconductor integrated circuit and a circuit layout method for semiconductor integrated circuit. It is new and can be put into industrial use.
Although the embodiments of the present invention have been described in detail, many modifications and variations may be made by those skilled in the art from the teachings disclosed hereinabove. Therefore, it should be understood that any modification and variation equivalent to the spirit of the present invention be regarded to fall into the scope defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 108117734 | May 2019 | TW | national |
