Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device is provided in which a phase-change layer can be formed stably and electric current required to cause the phase change of the phase-change layer can be reduced. An edge portion of the phase-change layer is formed above a lower electrode. The edge portion is formed to assume a tapered shape in cross section such that the thickness of the phase-change layer varies above the contact area between the lower electrode and the phase-change layer. The tapered portion is filled with an oxide film. According to this configuration, the region in which the phase-change occurs can be restricted, and hence the phase-change layer can be heated efficiently, resulting in reduction of electric current required for heating.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinal sectional view showing an example of a conventional PRAM cell structure;

FIG. 2A is a longitudinal sectional view of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2B is a plan view of the semiconductor memory of FIG. 2A;

FIGS. 3A to 3I are diagrams for explaining respective steps of manufacturing the semiconductor memory device of FIGS. 2A and 2B; and

FIGS. 4A to 4C are diagrams for explaining respective steps of manufacturing a semiconductor memory device according to another embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2A is a sectional view and FIG. 2B is a plan view of a semiconductor memory device according to an embodiment of the present invention.

As shown FIG. 2A, the semiconductor memory device according to this embodiment has a phase-change layer 21 formed of a film of a chalcogenide (GST) as a phase change material, and upper electrodes 22 and lower electrodes 23 for heating the phase-change layer 21 by supplying electric current through the phase-change layer 21.

The semiconductor memory device further has transistors (not shown) formed in a substrate 24 in a diffused manner for controlling the supply of current to the lower electrodes 23, gate electrodes 25 connected to gates of the transistors, series of contacts 26a and 26b for connecting drains of the transistors to the lower electrodes 23, a ground wiring 27, and a series of contacts 28a and 28b for connecting a common source of the transistors to the ground wiring 27.

Each of the lower electrodes 23 is formed into a cup shape, and the upper edge of the lower electrode 23 has a ring shape as shown in FIG. 2B.

The lower electrode 23 is used as a heater plug. This means that the lower electrode 23 serves as a part of a heating element during writing of data. Therefore, the lower electrode 23 is preferably formed of a material having relatively high electric resistance such as a metal silicide, a meta nitride, or a nitride of a metal silicide. Specifically, a high melting point metal or a nitride thereof such as W, TiN, TaN, WN or TiAlN, or a nitride of a high melting point metal silicide such as TiSiN, WSiN or TiCN may preferably be used as the material of the lower electrode 23.

As described above, the bottom surface of the lower electrode 23 is connected to a diffused region (the drain of the transistor) formed in an active region of the substrate 24 through the contacts 26a and 26b. Two gate electrodes 25 are provided on the substrate 24. This means that, according to this embodiment, two transistors are formed in one active region. These two transistors have the common source, which is connected to the ground wiring 27 through the contacts 28a and 28b provided in an interlayer insulation film 29.

The phase-change layer 21 has an edge portion 21-1 located above the lower electrode 23. This edge portion 21-1 forms a tapered portion having a slant face extending from the outer periphery of the upper electrode 22 located outside of a ring defined by the upper edge of the lower electrode 23 to the inside of the ring defined by the upper edge of the lower electrode 23. In other words, the phase-change layer 21 has a tapered portion formed above the region where the phase-change layer 21 is in contact with the lower electrode 23. This tapered portion is filled with an oxide film 30. The oxide film 30 is formed to fill the whole area shown in FIG. 2 except the phase-change layer 21.

The chalcogenide material used for the phase-change layer 21 is an alloy containing at least one or more elements among germanium (Ge), antimony (Sb), tellurium (Te), indium (In), selenium (Se), and the like. For example, the material may be an alloy of binary elements such as GaSb, InSb, InSe, Sb₂Te₃, and GeTe, an alloy of ternary elements such as Ge₂Sb₂Te₅, InSbTe, GaSeTe, SnSb₂Te₄, and InSbGe, and an alloy of quaternary elements such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te₈₁Ge₁₅Sb₂S₂. The phase change material used for the phase-change layer 21 is not limited particularly but may be any material as long as the material is able to assume two or more phase states and has different electric resistance values depending on the phase states.

Referring to FIGS. 3A to 3I, a description will be made of a method of manufacturing the semiconductor memory device shown in FIGS. 2A and 2B. Formation of the transistors, the gate electrodes 25, the ground wiring 27, and the contacts 26a, 26b, 28a and 28b can be performed by a well-known method (standard process). Therefore, the description thereof will be omitted. The following description will be made on the assumption that a lower electrode is formed on a silicon substrate.

FIGS. 3A to 3I are sectional views for explaining primary steps for manufacturing the semiconductor memory device according to this embodiment.

As shown in FIG. 3A, a silicon oxide film is deposited on a silicon substrate 31 to form an interlayer insulation film 32.

The interlayer insulation film 32 is then patterned to form a contact hole 33 as shown in FIG. 3B.

As shown in FIG. 3C, a TiN film 34 is deposited so that a lower electrode 23 is defined by a part of the TiN film 34. Subsequently, as shown in FIG. 3D, an interlayer insulation film 35 formed of a silicon oxide film is deposited on the TiN film 34. The TiN film 34 deposited within the contact hole 33 assumes a cup shape.

The interlayer insulation film 35 and the TiN film 34 are then polished by a CMP (Chemical Mechanical Polishing) method from the top surface. This polishing is performed, as shown in FIG. 3E, such that only the cup-shaped portion of the TiN film 34 is left. The cup-shaped portion of the TiN film 34 is later utilized as the lower electrode 23.

Subsequently, a chalcogenide (e.g., GeSbTe) film 36 for later providing a phase-change layer 21 is deposited with a sputtering method. The surface on which the chalcogenide film 36 is formed is an even surface since it has been polished with the CMP method as described above. Therefore, the chalcogenide film 36 can be formed stably in a uniform thickness.

As shown in FIG. 3G, a tungsten film 37 is then formed so that a part of the tungsten film 37 later forms an upper electrode 22.

Subsequently, the tungsten film 37 and the chalcogenide film 36 are partially removed by a well-known selective etching method using a photoresist film or an etching mask. By this selective etching, the chalcogenide film 36 is formed with an edge with a tapered shape, or a tapered portion 36-1 as shown in FIG. 3H. To form the tapered shape of the chalcogenide film 36, reactive ion etching using mixes gas of O₂, Ar and HBr may be used, for instance. Because an edge of the etching mask can be gradually retreated by controlling etching conditions, the tapered shape can be made. The tapered portion 36-1 is formed such that the upper electrode 22 is located outside of a ring defined by the upper edge of the lower electrode 23 as shown by a right arrow and that the bottom surface of the chalcogenide film 36 is located inside of the ring as shown by a left arrow. In other words, the tapered portion 36-1 is formed to be located above a region where the lower electrode 23 is in contact with the chalcogenide film 36 (such that the slant face thereof is located above the contact region).

Finally, as shown in FIG. 3I, an oxide film 38 is formed in a region where the tungsten film 37 and the chalcogenide film 36 have been removed by the selective etching to fill the tapered portion 36-1 of the chalcogenide film 36.

In the semiconductor memory device according to this embodiment as described above, the base on which the chalcogenide film 36 is formed has an even surface, and hence the chalcogenide film 36 which is uniformly thin can be applied thereto in a stable manner. This stabilizes the characteristics of the semiconductor memory device as a phase-change memory.

By tapering the edge portion 36-1 (21-1) of the chalcogenide film 36 (21) above the cup-shaped portion of the TiN film 34 (or the lower electrode 23), the current path can be restricted and the region where phase-change occurs (the region hatched in a different manner in FIG. 3I (2A)) can also be restricted. Further, not only the volume of the part of the chalcogenide film 36 where the phase-change occurs can be reduced, but also heat dissipation in the upward direction can be suppressed. Therefore, the chalcogenide film 36 (21) can be heated efficiently and the electric current requiring for heating the same can be reduced.

A semiconductor memory device according to another embodiment will be described with reference to FIGS. 4A to 4C.

FIGS. 4A to 4C are sectional views for explaining respective steps for manufacturing the semiconductor memory device according to the second embodiment.

FIG. 4A shows the same state as FIG. 3G. This means that the same steps are performed as those shown in FIGS. 3A to 3G until the formation of the tungsten film 37.

Subsequently, as shown in FIG. 4B, the tungsten film 37 and the chalcogenide film 36 are partially removed by a well-known selective etching method to form a tapered portion 36-1 in the chalcogenide film 36. Further, the cup-shaped portion of the TiN film 34 (or the lower electrode 23) and the interlayer insulation film 35 (and 32) are then selectively partially removed so as to be substantially flush with the slant face of the tapered portion 36-1 of the chalcogenide film 36. This removes the part of the lower electrode which has become unnecessary by the tapering of the edge portion of the chalcogenide film 36. To etch the TiN film 34 and the interlayer insulation film 35, etching gas of CF₄, CHF₃ or Ar—HBr may be used in the reactive ion etching. An edge of an etching mask for etching the TiN film 34 and the interlayer insulation film 35 can be gradually retreated by controlling etching conditions and thereby a tapered shape can be made.

Finally, as shown in FIG. 4C, an oxide film 41 is formed in the region where the tungsten film 37, the chalcogenide film 36, the TiN film 34 (or the lower electrode 23), and the interlayer insulation film 35 have been removed by the selective etching, so that the tapered portion 36-1 is filled with the oxide film 41.

According to the second embodiment as described above, further advantageous effects can be obtained in addition to the above-mentioned effects by removing the unnecessary part of the lower electrode. Specifically, the heat dissipation from the lower electrode can be suppressed and the efficiency of heating the chalcogenide film 36 can be improved further more.

Claims

1. A semiconductor memory device comprising a phase-change layer provided between a lower electrode and an upper electrode, wherein the phase-change layer has a tapered portion located above the lower electrode, and the area of the uppermost flat surface of the phase-change layer is smaller than the area of the lower most flat surface of the phase-change layer.

2. The semiconductor memory device according to claim 1, wherein the tapered portion is located above a region where the lower electrode is in contact with the phase-change layer.

3. The semiconductor memory device according to claim 1, wherein the tapered portion is filled with an oxide film.

4. The semiconductor memory device according to claim 3, wherein the lower electrode has a shape defined by cutting off a part of a cup-shaped electrode in correspondence with the shape of the tapered portion of the phase-change layer.

5. The semiconductor memory device according to claim 1, wherein the lower electrode has a shape defined by cutting off a part of a cup-shaped electrode in correspondence with the shape of the tapered portion of the phase-change layer.

6. The semiconductor memory device according to claim 5, wherein the phase-change layer is formed of a chalcogenide.

7. The semiconductor memory device according to claim 1, wherein the phase-change layer is formed of a chalcogenide.

8. The semiconductor memory device according to claim 3, wherein the phase-change layer is formed of a chalcogenide.

9. The semiconductor memory device according to claim 4, wherein the phase-change layer is formed of a chalcogenide.

10. A method of manufacturing a semiconductor memory device having a phase-change layer provided between a lower electrode and an upper electrode, comprising: forming a flat surface of an insulation film from which a part of the lower electrode is exposed;forming a phase-change layer on the flat surface of the insulation film; andremoving a part of the phase-change layer to form a tapered portion in the phase-change layer such that the tapered portion is located above the lower electrode.

11. The method of manufacturing a semiconductor memory device according to claim 10, further comprising forming the upper electrode on the phase-change layer after the forming of the phase-change layer, wherein the upper electrode is also partially removed in the forming of the tapered portion.

12. The method of manufacturing a semiconductor memory device according to claim 10, further comprising filling the tapered portion with an oxide film.

13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the forming of the tapered portion also removes a part of the lower electrode in correspondence with the shape of the tapered portion of the phase-change layer.

14. The method of manufacturing a semiconductor memory device according to claim 10, wherein the forming of the tapered portion also removes a part of the lower electrode in correspondence with the shape of the tapered portion of the phase-change layer.

15. The semiconductor memory device according to claim 2, wherein the tapered portion is filled with an oxide film.

16. The semiconductor memory device according to claim 2, wherein the lower electrode has a shape defined by cutting off a part of a cup-shaped electrode in correspondence with the shape of the tapered portion of the phase-change layer.

17. The semiconductor memory device according to claim 2, wherein the phase-change layer is formed of a chalcogenide.

18. The method of manufacturing a semiconductor memory device according to claim 11, further comprising filling the tapered portion with an oxide film.

19. The method of manufacturing a semiconductor memory device according to claim 11, wherein the forming of the tapered portion also removes a part of the lower electrode in correspondence with the shape of the tapered portion of the phase-change layer.