Patent Application
20210296275
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application 2020-049933, filed on Mar. 19, 2020, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor memory device and a manufacturing method for a semiconductor memory device.
A NAND flash memory is known as one type of semiconductor memory device. The NAND flash memory includes a memory cell array and its control circuit. As a method of manufacturing the semiconductor memory device, a memory cell array chip and a control circuit chip formed on the individual semiconductor substrates can be bonded later. It is known that this method can suppress the effect of the temperature of the manufacturing process when forming the memory cell array on the control circuit chip, thereby improving the manufacturing yield of the semiconductor memory device.
A semiconductor memory device according to the present embodiment includes a substrate including a silicon single crystal, a control circuit including a transistor having a channel direction different from [010] direction and [100] direction of the substrate, a circuit wiring layer electrically connected to the control circuit, a first connecting terminal connected to the circuit wiring layer, a plurality of memory cells arranged three-dimensionally, a memory wiring layer electrically connected to the memory cells; and a second connecting terminal connected to the memory wiring layer and the first connecting terminal.
Hereinafter, a semiconductor memory device according to the present embodiment will be described in detail by referring to the drawings. In the following description, constituent elements having substantially the same functions and configurations are denoted by the same reference numerals, and duplicate description will be given only when necessary. Each of the embodiments described below exemplifies a device and a method for embodying the technical idea of this embodiment, and the technical idea of the embodiment does not specify the material, shape, structure, arrangement, and the like of the component parts as follows. Various modifications can be made to the technical idea of the embodiment in the claims.
In order to make the description clearer, the drawings may be schematically represented with respect to widths, thicknesses, shapes, and the like of the respective portions in comparison with actual embodiments, but the drawings are only examples and are not intended to limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described with reference to the preceding drawings are denoted by the same reference numerals, and a repetitive description thereof may be omitted.
When the crystal orientation is described in this specification, all crystallographically equivalent directions are included. For example, the (001) plane is equivalent to the (100), (010), (−100), (0-10), and (00-1) planes. The negative Miller index is represented as “−1”.
A semiconductor memory device 1 according to the embodiment will be described with reference to
As shown in
On the substrate 10, a lead-out region 12 (upper right portion in
The substrate 10 may include a single crystal silicon. In this case, the surface of the substrate 10 on which the plurality of memory cells is arranged may be a (001) plane. Note that in this specification, the (001) plane also includes a plane that is shifted by ±10° from the (001) plane. The plurality of electrode layers 16 may be stacked in the [001] direction and the semiconductor pillar 15 may extend in the [001] direction. Thus, the semiconductor pillar 15 may form a plurality of transistors including memory cells connected in series in the [001] direction. The plurality of electrode layers 16 extend in the [010] or [100] direction, and the semiconductor pillars 15 may be arranged in a matrix in the [010] and [100] directions. Accordingly, the pluralities of memory cells may be arranged three-dimensionally in the [001], [010], and [100] directions. The lead-out region 12 may be arranged in the [100] direction and/or the [−100] direction of the memory cell array region 11. With such configuration, deformation of the memory cell array chip 100 can be suppressed when an external force is applied. However, the material of the substrate 10 is not particularly limited and may include glass or resin or the like. The substrate 10 used in the manufacturing process may ultimately be removed from the semiconductor memory device 1.
As shown in
The substrate 20 may include the single crystal silicon. In this case, the surface of the substrate 20 on which the plurality of transistors 26 is arranged may be the (001) plane. The channel direction of the plurality of transistors 26 is arranged in a direction different from the [010] direction and the [100] direction of the substrate 20. The channel of the plurality of transistors 26 may be oriented in the [110] and/or [−110] directions of the substrate 20. Here, the direction of the channel indicates the direction of the current flow in the channel. Or, the surface of the substrate 20 on which the plurality of transistors 26 is arranged may be a (111) plane. The substrate 20 may include silicon-germanium, silicon carbide or gallium-arsenide. The substrate 20 may be doped with an impurity. With such configuration, the electron mobility of the channel and driving current of the transistor 26 of the control circuit chip 200 can be increased, thereby transistor performance can be improved.
The method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to
The substrate 10 of the memory cell array wafer may include the single crystal silicon. In this case, the surface of the substrate 10 on which the plurality of memory cell array chips 100 are formed may be a (001) plane. The plurality of memory cell array chips 100 may be formed in a matrix with a notch 19 of the substrate 10 facing forward. Here, the notch 19 is arranged at the end of the substrate 10 in the [0-10] direction (this is 0°). Therefore, the plurality of memory cell array chips 100 may be formed side by side in the [010] direction and the [100] direction. Since the plurality of memory cell array chips 100 are formed side by side in the [100] direction and the [010] direction, the memory cells of the plurality of memory cell array chips 100 are formed three-dimensionally in the [001], [010], and [100] directions. The memory cell array wafer is formed by aligning a plurality of memory cell array chips 100 in the [100] direction and the [010] direction, so that bending of the memory cell array wafer can be suppressed as compared with the case where the memory cell array wafers are formed by aligning a plurality of memory cell array chips 100 side by side in the [110] direction and the [−101] direction. However, the material of the substrate 10 is not particularly limited, and may include glass or resin or the like.
For example, in the case where the direction of the substrate 10 of the memory cell array wafer is 0° and the case where the direction of the substrate 10 of the memory cell array wafer is 45°, the amount of deformation during the manufacturing process of the memory cell array wafer is shown in Table 1. Here, the memory cell array wafer was formed using the (001) planar silicon substrate having a diameter of 300 mm as the substrate 10. The amount of deformation of the end portion of the memory cell array wafer in the [001] direction is shown in Table 1, where the center of the substrate 10 is set to 0.
As shown in Table 1, by forming a plurality of memory cell array chips 100 in the substrate 10 of 0°, deformation of the memory cell array wafer can be suppressed.
The substrate 20 of the control circuit wafer may include the single crystal silicon. In this case, the surface of the substrate 20 on which the plurality of control circuit chips 200 are formed may be the (001) plane. The plurality of control circuit tips 200 may be formed in a matrix with a notch 29 of the substrate 20 facing forward. Here, the notch 29 is arranged at the end of the substrate 20 in the [1-10] direction (this is 45°). Therefore, the plurality of control circuit tips 200 may be formed side by side in the [110] direction and [−110] direction. The plurality of control circuit chips 200 are formed side by side in the [110] direction and the [−110] direction, so that the transistors 26 of the plurality of control circuit chips 200 are formed in the [110] direction and/or the [−110] direction. However, the surface of the substrate 20 on which the plurality of control circuit chips 200 are formed may be a (111) plane.
The substrate 20 may include silicon-germanium, silicon carbide, or gallium-arsenide. The substrate 20 may be doped with impurities. By forming the control circuit wafer in this manner, the electron mobility of the channel and driving current of the transistor 26 of the control circuit chip 200 of the control circuit wafer can be increased, thereby transistor performance can be improved.
After bonding the memory cell array wafer and the control circuit wafer, it may be divided into the individual semiconductor memory device 1. The substrate 10 may be removed before the semiconductor memory device 1 is divided.
The manufacturing method of the semiconductor memory device 1 according to this embodiment can improve the productivity and performance of the semiconductor memory device 1 by the fact that the substrate 10 of the memory cell array wafer and the substrate 20 of the control circuit wafer have different crystal orientations or compositions.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-049933 | Mar 2020 | JP | national |
