Semiconductor memory device and methods thereof

Abstract

A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type. A second example method may include storing at least one fixed data pattern within a storage unit, the at least one fixed data pattern only accessible during read operations of a first type, storing normal data within at least one memory cell, the normal data only accessible during read operations of a second type and blocking access to the at least one memory cell during an execution of read operations of the second type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention.

FIG. 1 is a block diagram illustrating a semiconductor memory device according to an example embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a mode register according to another example embodiment of the present invention.

FIG. 3 illustrates operating modes for the semiconductor memory device of FIG. 1 based on a mode register set according to another example embodiment of the present invention.

FIG. 4 is a block diagram illustrating a semiconductor memory device according to another example embodiment of the present invention.

Claims

1. A semiconductor memory device, comprising: a memory cell configured to store data;a storage unit configured to store at least one data pattern;a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation; andan output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type.

2. The semiconductor memory device of claim 1, wherein the at least one data pattern is fixed in memory.

3. The semiconductor memory device of claim 1, wherein the output control circuit controls the data output circuit such that during read operations of the second type the output at least one data pattern is synchronized with the same clock signal to which the output of the stored data is synchronized with during read operations of the first type.

4. The semiconductor memory device of claim 1, wherein the memory cell is a dynamic random access memory (DRAM).

5. The semiconductor memory device of claim 4, wherein the storage unit is a multi-purpose register that is selectively activated by a mode register.

6. The semiconductor memory device of claim 5, wherein the multi-purpose register stores the at least one data pattern for a read leveling operation.

7. The semiconductor memory device of claim 1, wherein the output control circuit decodes an mode register set (MRS) command to generate a read leveling signal for outputting the at least one data pattern during read operations of the second type.

8. The semiconductor memory device of claim 7, wherein the output control circuit disables a column selection line in response to the read leveling signal.

9. The semiconductor memory device of claim 1, wherein the output control circuit allows access to the memory cell during read operations of the first type.

10. The semiconductor memory device of claim 1, wherein the storage unit is a signature fuse circuit.

11. The semiconductor memory device of claim 10, wherein the output control circuit decodes an MRS command to generate a signature signal for outputting the at least one data pattern during read operations of the second type.

12. The semiconductor memory device of claim 11, wherein the output control circuit disables a column selection line in response to the signature signal.

13. The semiconductor memory device of claim 1, wherein the output control circuit includes: a first logic gate for generating an enable signal in response to an active signal and a read leveling signal;a column command decoder for operating responsive to the enable signal and generating a read signal in response to a read command;a second logic gate for disabling a column selection line in response to the read leveling signal;a delay locked loop circuit for generating a clock signal in response to the enable signal; anda latency circuit for controlling data synchronization with the clock signal so such the output of the data output circuit is synchronized with the clock signal.

14. The semiconductor memory device of claim 1, further comprising: a selection circuit for selectively outputting one of the stored data and the at least one data pattern,wherein the data output circuit outputs the selected output received from the selection circuit.

15. The semiconductor memory device of claim 14, wherein the selection circuit outputs the at least one data pattern in response to the read leveling signal.

16. The semiconductor memory device of claim 14, wherein the second logic gate is an AND gate performing an AND operation on the read signal and an inverted version of the read leveling signal and provides the result of the AND operation to the column selection line.

17. A method of reading data from a semiconductor memory device, comprising: storing data in a memory cell;storing at least one data pattern in a storage unit;outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation; andblocking access to the memory cell during read operations of the second type.

18. The method of claim 17, further comprising: synchronizing an output of the stored data with a clock signal during read operations of the first type; andsynchronizing an output of the at least one data pattern with the clock signal during read operations of the second type.

19. A method of reading data from a semiconductor memory device, comprising: storing at least one fixed data pattern within a storage unit, the at least one fixed data pattern only accessible during read operations of a first type;storing normal data within at least one memory cell, the normal data only accessible during read operations of a second type; andblocking access to the at least one memory cell during an execution of read operations of the second type.

20. The method of claim 19, wherein the at least one fixed data pattern is read-only and includes identifying information associated with the semiconductor memory device.