This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-174622, filed Sep. 4, 2015, the entire contents of which are incorporated herein by reference.
Exemplary embodiments described herein relate to a semiconductor package and a method of manufacturing the semiconductor package.
There is a semiconductor package in which a semiconductor chip is provided between two metal plates via a connection portion. In order to enhance heat dissipation performance of the semiconductor package, an exposed area of each of the metal plates should be increased. Meanwhile, the thickness of the connection portion affects reliability of the semiconductor package, and thus, the thickness of the connection portion of the assembled semiconductor package needs to be measured. However, when the area of the metal plate is increased, the measurement of the thickness of the connection portion between each of the metal plates and the semiconductor chip cannot be easily performed.
Embodiments provide a semiconductor package which enables easy measurement of the thickness of a connection portion and a method of manufacturing the semiconductor package.
In general, according to one embodiment, there is provided a semiconductor package including a first metal plate having a first surface, a semiconductor chip including a first electrode and a second electrode, on the first surface, and a second metal plate. The first electrode of the semiconductor chip is connected to the first metal plate. The second metal plate has a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface, and is connected to the second electrode. The first side surface has a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface has a second recessed portion extending in the second direction that crosses the first and second surfaces.
Hereinafter, the respective embodiments will be described with reference to the drawings.
In addition, the drawings are schematic or conceptual, and thus the relationship between the thickness and the width of each portion, and the size ratio between portions are not necessarily the same as the actual ones. Moreover, the same components, dimensions and ratios may be illustrated differently depending on the drawings in some cases.
In the disclosure, the same components which have already been described are given the same reference numerals, and the specific description of the same components will be repeated as needed.
An XYZ orthogonal coordinate system is used in the description of the respective embodiments. Two directions which are parallel to a first surface S1 of a first metal plate 1 and are orthogonal to each other are referred to as an X-direction and a Y-direction. In addition, a direction which is perpendicular to the X-direction and Y-direction is referred to as a Z-direction.
A semiconductor package according to an embodiment will be described with reference to
Note that, a portion of a sealing portion 5 is omitted in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
The first lead terminal 21 is connected to the first metal plate 1. A plurality of the first lead terminals 21 are provided and are spaced apart in a Y-direction, and each of the first lead terminals 21 extend from the metal plate 1 in the X-direction. In the example illustrated in
The second lead terminal 22 is connected to the second metal plate 2 by a fourth connection portion 34. A plurality of second lead terminals 22 are arranged spaced apart in the Y-direction, and each of the second lead terminals 22 extends from the fourth connection portion 34 in the X-direction.
The third lead terminal 23 is connected to the metallic member 3 by a fifth connection portion 35, and extends from the fifth connection portion 35 in the X-direction.
The second metal plate 2 and the second lead terminal 22 may be integrally formed with each other without being limited to the examples illustrated in
The number of the first lead terminals 21, the number of the second lead terminals 22, and the number of the third lead terminals 23 are optionally determined without being limited to the example illustrated in
In addition, each of the first lead terminal 21, the second lead terminal 22, and the third lead terminal 23 may include a portion which is bent in the middle thereof.
The sealing portion 5 is provided on the first metal plate 1 and in the vicinity of the first metal plate 1, and covers the semiconductor chip 10, a portion of each of the first lead terminals 21 to the third lead terminal 23, and a portion of the second metal plate 2.
Next, a second metal plate 2 will be described in detail.
As illustrated in
A first cutout or recessed portion 41 is formed on the second surface S2, and a second cutout portion 42 and a third cutout portion 43 are formed on the third surface S3. The first cutout portion 41 and the second cutout portion 42 are aligned in the Y-direction, and the second cutout portion 42 and the third cutout portion 43 are aligned in the X-direction.
The first to third cutout portions 41 to 43 extend through the second metal plate 2 in the Z-direction. More specifically, the first cutout portion 41 is formed from one side to the other side of the second surface S2 in the Z-direction. The second cutout portion 42 and the third cutout portion 43 are formed from one side to the other side of the third surface S3 in the Z-direction. That is, the first cutout portion 41 is formed from an upper side to a lower side of the second surface S2, and the second cutout portion 42 and the third cutout portion 43 are formed from an upper side to a lower side of the third surface S3.
The first to third cutout portions 4143 are filled with the sealing portion 5.
A portion of each of the first to third cutout portions 41 to 43 and a side surface of the semiconductor chip 10 are arranged to be on a same line in parallel with the Z-direction respectively. In other words, a portion of the surface forming each of the first cutout portions 41 to 43 and a side surface of the semiconductor chip 10 are arranged to be on a same line in parallel with the Z-direction respectively.
That is, when the semiconductor package 100 is viewed from the Z-direction through the sealing portion 5, the second metal plate 2 is formed such that the top surface of the semiconductor chip 10 is exposed through the first to third cutout portions 41 to 43.
In addition, the second metal plate 2 and the metallic member 3 are spaced from each other on the semiconductor chip 10 in the X-direction and the Y-direction. For this reason, when the semiconductor package 100 is viewed from the Z-direction through the sealing portion 5, it is possible to view the top surface of the semiconductor chip 10 through a gap between the second metal plate 2 and the metallic member 3.
Here, examples of materials of the respective configuring components will be described.
The first metal plate 1, the second metal plate 2, the metallic member 3, and the first lead terminal 21 to the third lead terminal 23 includes metal such as copper.
The semiconductor chip 10 includes a semiconductor element which mainly contains silicon, silicon carbide, gallium nitride, or gallium arsenide.
The first electrode 11 to the third electrode 13 contains a metallic material such as aluminum.
The first connection portion 31 to the fifth connection portion 35 contains a solder material.
The sealing portion 5 contains an insulating resin such as an epoxy resin.
Next, an example of a method of manufacturing the semiconductor package according to the embodiment will be described.
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
Further, the first to third cutout portions 41 to 43 are formed on the second metal plate 2, as described above. The second metal plate 2 is positioned such that a portion of each of the first to third cutout portions 41 to 43 and the side end surface of the semiconductor chip 10 are on a same line in parallel with the Z-direction respectively. At this time, the second metal plate 2 is desirably positioned such that the first to third cutout portions 41 to 43 are respectively adjacent to the corners of the semiconductor chip 10 in the Z-direction.
After positioning the second metal plate 2, the position of the semiconductor chip 10 is measured in plural places through the first cutout portion 41 to the third cutout portion 43.
Next, as illustrated in
Subsequently, the top surface of the sealing portion 5 is ground until the top surface of the second metal plate 2 is exposed. Thereafter, the semiconductor package 100 illustrated in
Meanwhile, operations and effects in the embodiment will be described.
In a case where the semiconductor package 100 is repeatedly heated and cooled in the, it is likely that cracks occur in a portion thereof having a relatively small thickness. This phenomenon is most commonly occurs in the first connection portion 31 and the second connection portion 32 which have a large contact area between each metal plate and the semiconductor chip 10. When the cracks occur in these connection portions, the conductivity is deteriorated, and thus it is likely that an operation failure of the semiconductor package occurs.
For this reason, it is desired to measure the thickness of the connection portion, and to scan for confirming whether or not a portion having small thickness is locally present in the connection portion. On the other hand, in order to enhance heat dissipation performance, when an area of the first metal plate 1 and an area of the second metal plate 2 are increased, the connection portion is hidden between the metal plates, and thus the measurement of the thickness of the connection portion cannot be easily performed.
In contrast, in the semiconductor package of the embodiment, the first cutout portion 41 and the second cutout portion 42 are formed on the second metal plate 2. When forming the first cutout portion 41 and the second cutout portion 42 on the second metal plate 2, the measurement of the position of the top surface of the semiconductor chip 10 is easily performed through the cutout portions thereof.
It is possible to calculate inclination of the semiconductor chip 10 by measuring at least two positions of the top surface of the semiconductor chip 10 through the first cutout portion 41 and the second cutout portion 42. When calculating the inclination of the semiconductor chip 10, it is possible to estimate the thickness of each point of the thickness of the first connection portion 31 and the thickness of the second connection portion 32.
That is, according to the embodiment, the measurement of the thickness of the connection portion can be easily performed by forming the first cutout portion 41 and the second cutout portion 42 on the second metal plate 2.
In addition, when forming the third cutout portion 43 in addition to the second cutout portion 42 on the third surface S3, through the first cutout portion 41 to the third cutout portion 43, it is possible to detect three positions of the top surface of the semiconductor chip 10. For this reason, it is possible to detect the inclination of the semiconductor chip 10 in X-Z plane and the inclination of the semiconductor chip 10 in Y-Z plane. As a result, it is possible to more accurately measure the thickness of the first connection portion 31 and the thickness of the second connection portion 32.
In addition, in order to more accurately calculate the inclination of the semiconductor chip 10, it is desirable that the position of each corner portion of the semiconductor chip 10 can be measured through the first to third cutout portions 41 to 43. That is, it is desirable that the first to third cutout portions 41 to 43 are adjacent to each corner portion of the semiconductor chip 10 in the Z-direction as illustrated in
Note that, as illustrated in
Accordingly, when the semiconductor package includes the metallic member 3, it is possible to measure the thickness of the first connection portion 31 and the thickness of the second connection portion 32 as long as at least one of the first cutout portion 41 and the second cutout portion 42 is formed. In addition, if both the first cutout portion 41 and the second cutout portion 42 are formed, it is possible to calculate the inclination of the semiconductor chip 10 in X-Z plane and the inclination of the semiconductor chip 10 in Y-Z plane.
On occasion, the semiconductor chip 10 may be bent or warped. In this case, the inclination of the semiconductor chip 10 is not uniform. Accordingly, it is desirable that the position of the top surface of the semiconductor chip 10 is measured though the gap between the second metal plate 2 and the metallic member 3 in addition to the first cutout portion 41 to the third cutout portion 43, and the thickness of the first connection portion 31 and the thickness of the second connection portion 32 in the respective points are optically measured.
In addition, in order to more accurately measure the position of the top surface of the semiconductor chip 10, it is desirable that a portion of each of the first to third cutout portions 41 to 43 and the side end surface of the semiconductor chip 10 are on a same line in parallel with the Z-direction, and are not adjacent to the second connection portion 32 in the Z-direction.
Meanwhile,
The embodiment is not limited to the aforementioned examples; the semiconductor chip 10 is applicable to a case of a diode including two electrodes. In this case, the semiconductor chip 10 may not include the third electrode, and the semiconductor package 100 may not include the metallic member 3 and the third lead terminal 23.
In addition, in the examples illustrated in
In addition, in addition to the first to third cutout portions 41 to 43, other cutout portions may be formed on the second metal plate 2.
As illustrated in
The first cutout portion 41, which is formed in the first portion 2a, in the X-direction is longer than the first cutout portion 41, which is formed in the second portion 2b, in the X-direction.
For this reason, a volume of the sealing portion 5 which is provided in the first cutout portion 41 in the first portion 2a is greater than a volume of the sealing portion 5 which is provided in the first cutout portion 41 in the second portion 2b. Further, a portion of the second portion 2b is positioned between a portion of the sealing portion 5 and a portion of another portion in the Z-direction.
With such a configuration, it is possible to increase the contact area between the sealing portion 5 and the second metal plate 2, and to increase the area of the sealing portion 5 which covers the second metal plate 2. For this reason, it is possible to more firmly fix the second metal plate 2 by the sealing portion 5.
As described above, the embodiment is described by exemplifying the first cutout portion 41; however, it is also possible that the structure of the above-described first cutout portion 41 is applied to the second cutout portion 42 and the third cutout portion 43.
Note that, the position of the top surface of the semiconductor chip 10 can be measured by using, for example, a measurement microscope.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein maybe made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
For example, the specific configurations of the respective components of the first metal plate 1, the metallic member, the sealing portion 5, the semiconductor chip 10, the first electrode 11, the second electrode 12, the third electrode 13, the first lead terminal 21, the second lead terminal 22, the third lead terminal 23, the first connection portion 31, the second connection portion 32, the third connection portion 33, the fourth connection portion 34, and the fifth connection portion 35 which are included in the embodiment can be properly selected by those skilled in the art based on a well-known technique. In addition, the above-described embodiments may be combined with each other so as to be executed.
Number | Date | Country | Kind |
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2015-174622 | Sep 2015 | JP | national |