Patent Application
20250079382
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0113970, filed on Aug. 29, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concept relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a panel-level semiconductor package and a method of manufacturing the semiconductor package.
In the electronic product market, the demand for portable devices has rapidly increased. Miniaturization and lightening of electronic components mounted on these electronic products continues to be desirable. For miniaturization and lightening of electronic components, a semiconductor package mounted on the electronic components is required to process high capacity data while the volume of the semiconductor package is gradually reduced. Recently, a panel-level package (PLP) technology of performing a semiconductor package process at a panel level and dividing a panel-level semiconductor structure on which the semiconductor package process is performed into separate packages has been proposed.
The inventive concept provides a semiconductor package in which a line width of a fine pattern included in a redistribution pattern of an upper package substrate is further refined.
It will be appreciated by persons skilled in the art that the objects that could be achieved with the inventive concept are not limited to what has been particularly described hereinabove and the above and other objects that the inventive concept could achieve will be more clearly understood from the following detailed description.
According to an aspect of the inventive concept, there is provided a semiconductor package comprising: a lower package substrate including lower insulating layers; a first semiconductor device mounted on the lower package substrate; a core layer on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device and including: a core substrate, core vias passing through the core substrate, and core patterns connecting the core vias to each other; an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer; and an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer, wherein the first upper redistribution layer includes a first upper insulating layer and a first upper redistribution pattern on the first upper insulating layer, the second upper redistribution layer includes a second upper insulating layer on the first upper insulating layer and a second upper redistribution pattern on the second upper insulating layer, a first line width of a first fine pattern of the first upper redistribution pattern is greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, and a first line spacing of the first fine pattern is greater than or equal to a corresponding second line spacing of the second fine pattern.
According to another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor package, the method including forming a first process structure including: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, and the core layer being laterally spaced apart from the first semiconductor device, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, the encapsulation material being on the core layer; forming a first upper redistribution layer, the first upper redistribution layer including: a first upper insulating layer on the encapsulation material of the first process structure and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer including: a second upper insulating layer on the first upper redistribution layer and a second upper redistribution pattern on the second upper insulating layer, wherein the forming of the first upper redistribution layer includes: forming the first upper insulating layer on the encapsulation material; forming, by recessing a portion of the encapsulation material, a plurality of first upper via holes which pass through the first upper insulating layer and through which a portion of the core layer is exposed; forming a first seed layer on the first upper insulating layer having the plurality of first upper via holes; and forming first upper via patterns in the plurality of first upper via holes, the first upper via patterns being electrically connected to the core layer, and forming first upper line patterns on the first upper via patterns, wherein the forming of the second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper via holes through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes; forming a resist layer on the second upper insulating layer on which the second seed layer is formed; and forming second upper via patterns on the plurality of second upper via holes and forming second upper line patterns on the second upper via patterns, wherein a material of the first upper insulating layer and a material of the second upper insulating layer are different from each other, the first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line width of a first fine pattern of the first upper redistribution pattern is greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, the first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line spacing of the first fine pattern is greater than or equal to a corresponding second line spacing of the second fine pattern, and the first seed layer is formed via electroless plating and the second seed layer is formed using a sputter process.
According to another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor package, the method including forming a first process structure including: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, the encapsulation material being on the core layer; forming a first upper redistribution layer, the first upper redistribution layer including: a first upper insulating layer on the encapsulation material of the first process structure and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer including: a second upper insulating layer on the first upper redistribution layer and a second upper redistribution pattern on the second upper insulating layer, wherein the forming of the first upper redistribution layer includes: forming the first upper insulating layer on the encapsulation material; forming, by recessing a portion of the encapsulation material, a plurality of first upper via holes which pass through the first upper insulating layer and through which a portion of the core layer is exposed; forming a first seed layer on the first upper insulating layer having the plurality of first upper via holes; and forming first upper via patterns in the plurality of first upper via holes, the first upper via patterns being electrically connected to the core layer, and forming first upper line patterns on the first upper via patterns, the forming of the second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper via holes through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes; forming a resist layer on the second upper insulating layer on which the second seed layer is formed; and forming second upper via patterns on the plurality of second upper via holes and forming second upper line patterns on the second upper via patterns, wherein a material of the first upper insulating layer and a material of the second upper insulating layer are identical to each other, and the first seed layer and the second seed layer are each formed using a sputter process.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, embodiments will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and repetitions thereof are omitted.
Referring to
The core layer 100 may include the through hole CA passing through upper and lower surfaces thereof to mount the semiconductor chip 200 therein. As shown in
The core layer 100 may include a core insulating layer 110, core wiring layers 121, and core vias 122. The core wiring layers 121 and the core vias 122 may be arranged to electrically connect the upper and lower surfaces of the core layer 100 to each other. The core wiring layer 121 may be disposed inside the core insulating layer 110 but is not limited thereto. The core wiring layers 121 exposed through the lower surface of the core layer 100 among all the core wiring layers 121 may be embedded and disposed into the core insulating layer 110, which may be a structure based on a manufacturing process. The core insulating layer 110 may be referred to as a base substrate.
The core insulating layer 110 may be formed of or include an insulating material, for example, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide, and may further include an inorganic filler. Alternatively, the core insulating layer 110 may include a resin impregnated into a core material such as glass fiber, glass cloth, and glass fabric, for example, a prepreg, Ajinomoto build-up film (ABF), FR-4, or bismaleimide triazine (BT) in addition to an inorganic filler. The core insulating layer 110 may be a multilayer substrate including a plurality of layers.
The semiconductor chip 200 may be mounted in the through hole CA of the core layer 100 and may be spaced apart from an inner wall of the through hole CA. The first semiconductor chip 200 may be configured in a single or plural number. The semiconductor chip 200 may include a semiconductor substrate 210 having an active surface and an inactive surface opposite to each other, and connection pads 220 disposed on the active surface of the semiconductor chip 200. For example, the semiconductor chip 200 may have a vertical direction thickness of about 150 μm or more.
The semiconductor chip 200 may have a face down arrangement in which the active surface of the semiconductor substrate 210 faces the lower package substrate 300 and may be mounted on an upper surface of the lower package substrate 300. In this case, the inactive surface of the semiconductor chip 200 may be referred to as an upper surface of the semiconductor chip 200, and a surface of the semiconductor substate 210, which is an opposite surface to the inactive surface of the semiconductor chip 200, may be referred to as a lower surface of the semiconductor chip 200.
The semiconductor substrate 210 may be formed of or include, for example, semiconductor materials such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 210 may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 210 may include a well doped with impurities as a conductive area. The semiconductor substrate 210 may have a variety of device separation structures, such as a shallow trench isolation (STI) structure.
A semiconductor device including a plurality of individual devices of various types may be formed on the active surface of the semiconductor substrate 210. The plurality of individual devices may be electrically connected to the conductive area of the semiconductor substrate 210. The semiconductor device may further include conductive wiring or conductive plugs that electrically connect the plurality of individual devices to the conductive area of the semiconductor substrate 210. The plurality of individual devices may be electrically separated from other individual devices that neighbor each other by an insulating film.
In some embodiments, the semiconductor chip 200 may include a logic device. For example, the semiconductor chip 200 may be a central processing device chip, a graphics processing device chip, or an application processor (AP). In other embodiments, when the semiconductor package 1 includes the plurality of semiconductor chips 200, one of the plurality of semiconductor chips 200 may be a central processing device chip, a graphics processing device chip, or an AP chip, and another one may be a memory semiconductor chip including a memory device.
For example, the memory device may be a non-volatile memory device such as flash memory, a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM) or a resistive random access memory (RRAM). In some embodiments, the memory device may be a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).
The semiconductor chip 200 may include the connection pads 220 disposed on the lower surface of the semiconductor chip 200. The connection pads 220 may be disposed to electrically connect the semiconductor chip 200 to other components. In some embodiments, a redistribution layer, a bump, or the like, which is connected to the connection pads 220, may be further disposed on the lower surface of the semiconductor chip 200. The connection pads 220 may be formed of or include a conductive material such as aluminum (Al). The semiconductor chip 200 may be electrically connected to a lower redistribution pattern 320 of the lower package substrate 300 through the connection pads 220.
On the lower package substrate 300, the connection pads 220 may be redistributed in a region outside the semiconductor chip 200 below the semiconductor chip 200. The lower package substrate 300 may include a plurality of lower insulating layers 310 and a lower redistribution pattern 320 including lower via patterns 321 and lower line patterns 322. The number and arrangement of the lower insulating layer 310, the lower via patterns 321, and the lower line patterns 322, which constitute the lower package substrate 300, are not limited to the diagrams, and may be changed in various ways in some embodiments.
The lower insulating layer 310 may be formed of or include an insulating material, such as a photo imageable dielectric (PID) resin. In this case, the lower insulating layers 310 may further include an inorganic filler. The lower insulating layers 310 may include the same materials or different materials. The lower redistribution pattern 320 including the lower via patterns 321 and the lower line patterns 322 may perform a function of redistribution the connection pads 220.
The lower line patterns 322 may be disposed on at least one of the upper and lower surfaces of the lower insulating layers 310. The lower via patterns 321 may be connected to portions of the lower line patterns 322 through the lower insulating layer 310.
The lower via patterns 321 may be completely filled with a conductive material, or may have a shape in which the conductive material is formed along a wall of the via. The lower redistribution pattern 320 may be formed of or include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.
The lower surface of the semiconductor chip 200 may be in contact with the uppermost lower insulating layer 310 among all the lower insulating layers 310. It will be understood that when an element is referred to as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact. In a semiconductor package manufacturing method S1, which is a manufacturing process of the semiconductor package 1 according to an embodiment described below (see, e.g.,
A lower passivation layer 350 may be disposed on the lower surface of the lower package substrate 300 and may protect the lower package substrate 300. The lower passivation layer 350 may be formed of or include an insulating material, for example, a resin, but is not limited thereto.
At least portions of the lower line patterns 322 may be exposed through openings of the lower passivation layer 350, and lower pads 330 may be disposed on the exposed lower line patterns 322. External connection terminals 340 may be electrically connected to the lower pads 330, respectively.
The external connection terminals 340 may connect the semiconductor package 1 to a main board of a separate electronic device on which the semiconductor package 1 is mounted. The external connection terminals 340 may be formed of or include at least one of conductive materials such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). A shape of the external connection terminal 340 may be changed in various forms such as a land, a bump, a pillar, or a pin in addition to a ball shape.
The encapsulation material 130 may prevent the semiconductor chip 200 from physical and/or chemical damage from the outside by sealing the semiconductor chip 200. The encapsulation material 130 may fill a space in the through hole CA of the core layer 100 and extend on the upper surface of the core layer 100. In other words, the encapsulation material 130 may fill a space between the inner wall of the through hole CA and the semiconductor chip 200 and cover a portion of the upper surface of the semiconductor chip 200 and an upper surface of the core layer 100. In some embodiments, the encapsulation material 130 may fill at least a partial space between the semiconductor chip 200 and the upper package substrate 400. The encapsulation material 130 may be formed of or include an insulating material such as an epoxy resin or a polyimide. However, the material of the encapsulation material 130 is not limited to the above-described materials.
The upper package substrate 400 may include a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2. The upper package substrate 400 may be disposed on an upper surface of the encapsulation material 130 and may be electrically connected to the semiconductor chip 200 and the lower package substrate 300 through the core wiring layers 121 and the core vias 122 of the core layer 100.
The first upper redistribution layer RDL1 may include a first upper insulating layer 411A disposed on the encapsulation material 130, and a first redistribution pattern 420. The first redistribution pattern 420 may include first upper via patterns 421 (e.g., first upper vias), first upper line patterns 422 (e.g., first upper lines), and a first fine pattern FP1. A first seed layer SD1A used as a base of formation of the first redistribution pattern 420 may be provided on a lower surface of the first redistribution pattern 420. Unless otherwise specified, the term “pattern” may refer to a via and/or a line that forms a part of a redistribution layer or other layer. The term “pattern” may also refer to a group of patterns. For example, the term “pattern” may refer collectively to one or more via patterns and one or more line patterns.
The first upper via patterns 421 may each pass through the first upper insulating layer 411A. The first upper via patterns 421 may each be electrically connected to the uppermost core wiring layer 121 of the core layer 100 through a portion of the encapsulation material 130. The first upper line patterns 422 may be disposed on the first upper insulating layer 411A and the first upper via patterns 421. Redistribution of electrical input and output in the first upper redistribution layer RDL1 may be achieved through the first fine pattern FP1.
Among all side surfaces of the first upper via patterns 421, portions of side surfaces of the first upper via patterns 421 may be in contact with the first upper insulating layer 411A, and at least other portions of the side surfaces of the first upper via patterns 421, which are not in contact with the first upper insulating layer 411A, may be in contact with the encapsulation material 130.
The first seed layer SD1A may be disposed between the first upper via patterns 421 and the first upper insulating layer 411A, and between the first upper line patterns 422 and the first upper insulating layer 411A. In the specification, the first upper via patterns 421 and the first upper line patterns 422 are considered as including up to the first seed layer SD1A of the contact lower surface. That is, portions of the side surfaces of the first upper via patterns 421 are shown to be in contact with the first seed layer SD1A and a portion of a side surface of the first seed layer SD1A is shown to be in contact with the first upper insulating layer 411A, but the first seed layer SD1A in contact with the first upper via patterns 421 is included in (e.g., is a part of) the first upper via patterns 421, and thus portions of the side surfaces of the first upper via patterns 421 may be described as being in contact with the first upper insulating layer 411A. At the same time, among all the side surfaces of the first upper via patterns 421, at least other portions of the surfaces of the first upper via patterns 421, which are not in contact with the first upper insulating layer 411A, may be described as being in contact with the encapsulation material 130.
The first upper via patterns 421 may have a tapered shape, a horizontal width of which increases away from the lower package substrate 300.
The first upper insulating layer 411A may be processed and a first via hole 420R (refer to
The first upper insulating layer 411A may be formed of or include a build up material. According to an embodiment, a build up film as a build up material may be a three-layer structure obtained by combining a resin structure to which a filling material of SiO2 using an epoxy resin as a main component and a flame retardant are added, with a PET film as a base of the bottom. The build up material may include an Ajinomoto build-up film (ABF) or other laminates. For example, an ABF may be used as the build up material included in the first upper insulating layer 411A. Therefore, according to an embodiment, the encapsulation material 130 and the first upper insulating layer 411A may include the same build up material.
To form the first seed layer SD1A as a base of the first redistribution pattern 420 through electroless plating after the encapsulation material 130 is formed to include an ABF, the first upper insulating layer 411A including an ABF may be newly formed on the upper surface of the encapsulation material 130 including an already hardened ABF. When the first upper insulating layer 411A that is not hardened, which includes an ABF, is formed on the encapsulation material 130 including a hardened ABF, a non-hardened ABF may have greater adhesion with a plating layer in electroless plating than a hardened ABF. Accordingly, to easily form electroless plating for forming the first seed layer SD1A, the first upper insulating layer 411A may be formed by applying the ABF to form the first upper insulating layer 411A on the encapsulation material 130. As such, the reliability of wiring of the semiconductor package 1 according to an embodiment may be improved.
The first seed layer SD1A formed through the electroless plating may be formed of or include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).
The second upper redistribution layer RDL2 may include a second upper insulating layer 412 disposed on the first upper insulating layer 411A, and a second redistribution pattern 430. The second redistribution pattern 430 may include second upper via patterns 431, second upper line patterns 432, and a second fine pattern FP2. A second seed layer SD2 used as a base of formation of the second redistribution pattern 430 may be provided on a lower surface of the second redistribution pattern 430. Redistribution of electrical input and output in the second upper redistribution layer RDL2 may be achieved through the second fine pattern FP2. Unlike the diagrams, the semiconductor package 1 according to an embodiment may include three or more redistribution layers by stacking a plurality of second upper redistribution layers RDL2. In this case, the second upper via patterns 431 may be stack vias or staggered vias and may be provided on the preceding second upper redistribution layer RDL2. The stack via refers to a structure in which via patterns are stacked to overlap up and down, and the staggered via refers to a structure in which via patterns are stacked up and down and are laterally arranged at a certain distance offset from each other.
The second upper insulating layer 412 may be provided on the first upper insulating layer 411A and the first redistribution pattern 420. The second upper insulating layer 412 may be formed of or include an insulating material, such as a PID resin. In this case, the second upper insulating layer 412 may further include an inorganic filler.
The second redistribution pattern 430 including the second upper via patterns 431 and the second upper line patterns 432 may be formed on the second upper insulating layer 412. The second upper via patterns 431 may be electrically connected to at least portions of the first upper line patterns 422 of the first upper redistribution layer RDL1 through the second upper insulating layer 412. The second upper line patterns 432 may be disposed on the second upper insulating layer 412 and may be provided on the second upper via patterns 431. A metal plating layer 433 may be provided on at least portions of the second upper line patterns 432. The metal plating layer 433 may be formed of or include a metal including gold (Au) for example.
An upper passivation layer 440 may be disposed on the upper surface of the second upper insulating layer 412 and may protect the upper package substrate 400. The upper passivation layer 440 may include an insulating material, for example, a build up material, but is not limited thereto. The upper passivation layer 440 may include a third hole 440R obtained by recessing a portion of the upper passivation layer 440, through which at least portions of the second upper via patterns 431 and the metal plating layer 433 are exposed. In a package-on-package type package in which an upper semiconductor device 500 described below is stacked on or attached onto another package, upper connection terminals 540 may be located in the third hole 440R.
According to an embodiment, the second upper insulating layer 412 may include a photo imageable dielectric (PID) resin, and the second seed layer SD2, which is a base of the second redistribution pattern 430, may be formed by a sputter process. The second seed layer SD2 may be formed with a smaller line width than in the case in which the second seed layer SD2 is formed through electroless plating. When the second upper insulating layer 412 includes a PID resin, the second seed layer SD2 is accordingly formed by the sputter process, and therefore, a line width of the second seed layer SD2 may be less than a line width of the first seed layer SD1A that is a base of the first redistribution pattern 420 formed through electroless plating. Thus, the line width of the second fine pattern FP2 of the second redistribution pattern 430 may be equal to or less than the line width of the first fine pattern FP1 of the first redistribution pattern 420. In other words, the line width of the first fine pattern FP1 of the first redistribution pattern 420 may be equal to or greater than the line width of the second fine pattern FP2 of the second redistribution pattern 430.
For example, a first line width LW1A and a first line spacing LS1A of the first fine pattern FP1 are equal to or greater than a second line width LW2 and a second line spacing LS2 of the second fine pattern FP2, respectively. The first line width LW1A of the first fine pattern FP1 may be equal to or less than 10 μm, the first line spacing LS1A may be equal to or less than 13 μm, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μ. Alternatively, the first line width LW1A may be about 5 μm to about 10 μ, the first line spacing LS1 may be about 5 μm to about 13 μm, the second line width LW2 may be about 3 μm to about 9 μm, and the second line spacing LS2 may be about 3 μm to about 12 μm. Alternatively, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 5 μm, and the second line spacing LS2 may be equal to or less than 5 μm.
The entire first redistribution pattern 420 of the first redistribution layer RDL1 may be included in the first fine pattern FP1, or only a part of the first redistribution pattern 420 may be included in the first fine pattern FP1. Similarly, the entire second redistribution pattern 430 of the second redistribution layer RDL2 may be included in the second fine pattern FP2, or only a part of the second redistribution pattern 430 may be included in the second fine pattern FP2.
The line width of some portions of the first redistribution pattern 420 that are not included in the first fine pattern FP1 may exceed 10 μm, and the line spacing may exceed 13 μm. Similarly, the line width of some portions of the second redistribution pattern 430 that are not included in the second fine pattern FP2 may exceed 10 um, and the line spacing may exceed 13 um. The portions of the first redistribution pattern 420 that are not included in the first fine pattern FP1 and the portions of the second redistribution pattern 430 that are not included in the second fine pattern FP2 may collectively be referred to as coarse patterns. For example, the line width and line spacing of the coarse patterns may each range from 13 μm to 100 μm. The coarse patterns may include power lines and ground lines. The first fine pattern FP1 and the second fine pattern FP2 may include signal lines, power lines, and ground lines.
In the semiconductor package 1, a line width of the second fine pattern FP2 may be less than a line width of the first fine pattern FP1. Therefore, in the semiconductor package 1 according to an embodiment, fine patterns of a second package substrate 400 corresponding to a rear redistribution layer may be further refined, thereby improving the performance of the semiconductor package 1.
Referring to
The upper package substrate 400 may include a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2.
The first upper redistribution layer RDL1 may include a first upper insulating layer 411B disposed on the encapsulation material 130, and a first redistribution pattern 420. The first redistribution pattern 420 may include first upper via patterns 421, first upper line patterns 422, and a first fine pattern FP1. The first upper via patterns 421 may each pass through the first upper insulating layer 411B. The first upper via patterns 421 may each be electrically connected to the uppermost core wiring layer 121 of the core layer 100 through a portion of the encapsulation material 130. The first upper line patterns 422 may be disposed on the first upper insulating layer 411B and the first upper via patterns 421.
Unlike the semiconductor package 1 according to an embodiment of
According to an embodiment, the first upper insulating layer 411B may include a photo imageable dielectric (PID) resin, and a first seed layer SD1B, which is a base of the first redistribution pattern 420, may be formed by a sputter process. The first seed layer SD1B may be formed with a smaller line width than in the case in which the first seed layer SD1B is formed through electroless plating. When the first upper insulating layer 411B includes a PID resin, the first seed layer SD1B is accordingly formed by the sputter process, and therefore, a line width of the first seed layer SD1B formed by the sputter process may be less than a line width of the first seed layer SD1B formed through electroless plating. Thus, a line width of the first micro pattern FP1 of the first redistribution pattern 420 may be further refined.
The range of the first line width LW1B of the first fine pattern FP1 and the range of the second line width LW2 of the second fine pattern FP2 may be the same. The range of the first line spacing LS1B of the first fine pattern FP1 and the range of the second line spacing LS2 of the second fine pattern FP2 may be the same.
For example, the first line width LW1B of the first fine pattern FP1 may be equal to or less than 9 μm, and the first line spacing LS1B may be equal to or less than 12 μm, and similarly, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the first line width LW1B and the second line width LW2 may each be about 3 μm to about 9 μm, and the first line spacing LS1B and the second line spacing LS2 may each be about 3 μm to about 12 μm. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 may be equal to or less than 5 μm, and the first line spacing LS1B and the second line spacing LS2 of the second fine pattern FP2 may each be equal to or less than 5 μm.
Therefore, in the semiconductor package 1A according to an embodiment, fine patterns of a second package substrate 400 corresponding to a rear redistribution layer may be further refined, thereby improving the performance of the semiconductor package 1A.
Referring to
The upper semiconductor device 500 may be electrically connected to the upper package substrate 400 through the upper connection terminals 540. The upper connection terminals 540 may be formed of or include at least one of conductive materials such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). A shape of the upper connection terminals 540 may be changed in various forms such as a land, a bump, a pillar, or a pin in addition to a ball shape.
The upper semiconductor device 500 may be a semiconductor package including at least one semiconductor chip. At least one of the semiconductor chips included in the upper semiconductor device 500 may include a memory chip, a logic chip, a system on chip (SoC), a power management integrated circuit (PMIC) chip, and a radio frequency integrated circuit (RFIC) chip. The memory chip may include a DRAM chips, a SRAM chip, an MRAM chip, a NAND flash memory chip, and/or a high bandwidth memory (HBM) chip. The logic chip may include an application processor (AP), a micro-processor, a central processing unit (CPU), a controller, and/or an application specific integrated circuit (ASIC). For example, the SoC may include at least two of a logic circuit, a memory circuit, a digital integrated circuit (IC), an RFIC, and an input/output circuit.
Referring to
Referring to
Referring to
Operation S300 of forming the second upper redistribution layer may include forming the second upper insulating layer including PID on the first upper redistribution layer (S310), forming a plurality of second upper via holes through the second upper insulating layer (S320), forming a second seed layer using a sputter process (S330), forming a liquid photoresist layer on the second upper insulating layer (S340), and forming the plurality of second upper via patterns, and the plurality of second upper line patterns in the plurality of second upper via holes (S350).
The semiconductor package manufacturing method S1 according to an embodiment will be described with reference to
Referring to
Referring to
Referring to
Referring to
Referring to
The process of forming the lower package substrate 300 may be achieved by a redistribution process. That is, the lower package substrate 300 may be formed by alternately forming the lower via patterns 321 and the lower line patterns 322 included in the lower insulating layer 310 and the lower redistribution pattern 320. The process result located on the first adhesive layer CF1 on which processes up to the process of
Referring to
Referring to
A certain time elapses after the encapsulation material 130 is formed, and thus the build up material included in the encapsulation material 130 may be hardened. On the other hand, a certain time does not elapse after the first upper insulating layer 411A is formed, and thus the first upper insulating layer 411A may not be completely hardened.
As described below with reference to
Referring to
Due to the characteristics of the process of forming the upper via holes, the first upper via patterns 421 may have a tapered shape, a horizontal width of which increases away from the lower package substrate 300.
Referring to
The first redistribution pattern 420 of
According to an embodiment, the first redistribution pattern 420 may be formed through a plating process such as an additive process (AP), a semi additive process (SAP), or a modified semi additive process (MSAP). The AP, the SAP, and the MSAP are each an additive process for forming fine patterns, and the three aforementioned additive processes are different from each other in terms of a method of forming a seed layer and a method of removing the seed layer. In the SAP, patterns may be plated using an electroless copper plating layer as a seed layer, and the seed layer may be removed via flash etching after the patterns are plated. The MSAP means to remove a seed layer via quick etching using a copper foil and an electroless copper plating layer as the seed layer. In particular, the first redistribution pattern 420 may be formed by the SAP.
Then, the resist pattern may be removed, for example, by a strip process. Compared to the first redistribution pattern 420, the first seed layer SD1A may be removed by an etching process having etching selectivity for the first seed layer SD1A.
Referring to
The sputter process may be performed to form the second seed layer SD2. The second seed layer SD2 may be formed in the second via holes 430R and on an upper surface of the second upper insulating layer 412. The second seed layer SD2 may conformally cover a bottom surface and a sidewall of the second via holes 430R and the upper surface of the second upper insulating layer 412. The second seed layer SD2 may be formed of or include a conductive material. For example, the second seed layer SD2 may include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).
Referring to
Referring to
As described above, a line width of the second seed layer SD2 may be less than a line width of the first seed layer SD1A.
Thus, the line width of the second fine pattern FP2 of the second redistribution pattern 430 may be equal to or less than the line width of the first fine pattern FP1 of the first redistribution pattern 420. For example, a first line width LW1A and a first line spacing LS1A of the first fine pattern FP1 are equal to or greater than a second line width LW2 and a second line spacing LS2 of the second fine pattern FP2, respectively. The first line width LW1A of the first fine pattern FP1 may be equal to or less than 10 μm, the first line spacing LS1A may be equal to or less than 13 μm, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 5 μm, and the second line spacing LS2 may be equal to or less than 5 μm.
Accordingly, in the semiconductor package manufacturing method S1 according to an embodiment, the fine patterns of the second package substrate 400 corresponding to a rear redistribution layer may be refined through materials and processes, thereby improving the semiconductor package manufactured through the semiconductor package manufacturing method S1.
Referring to
Referring to
Referring to
Operation S300 of forming the second upper redistribution layer may include forming the second upper insulating layer including PID on the first upper redistribution layer (S310), forming a plurality of second upper via holes through the second upper insulating layer (S320), forming a second seed layer using a sputter process (S330), forming a liquid photoresist layer on the second upper insulating layer (S340), and forming the plurality of second upper via patterns, and the plurality of second upper line patterns in the plurality of second upper via holes (S350).
The semiconductor package manufacturing method S1 according to an embodiment will be described with reference to
In particular,
Referring to
Referring to
Referring to
Due to the characteristics of the process of forming the upper via holes, the first upper via patterns 421 may have a tapered shape, a horizontal width of which increases away from the lower package substrate 300.
Referring to
The first redistribution pattern 420 may be formed on the first seed layer SD1B. According to an embodiment, the first redistribution pattern 420 may be formed through a plating process such as an additive process (AP), a semi additive process (SAP), or a modified semi additive process (MSAP). In particular, the first redistribution pattern 420 may be formed by the SAP.
A line width of the first seed layer SD1B formed by a sputtering process may be less than a line width of the first seed layer formed through electroless plating. Thus, a line width of the first micro pattern FP1 of the first redistribution pattern 420 may be further refined.
For example, the first line width LW1B of the first fine pattern FP1 may be equal to or less than 9 μm, and the first line spacing LS1B may be equal to or less than 12 μm, and similarly, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 may be equal to or less than 5 μ, and the first line spacing LS1B and the second line spacing LS2 may be equal to or less than 5 μm.
Accordingly, in the semiconductor package manufacturing method S1 according to an embodiment, a circuit of the second package substrate 400 corresponding to a rear redistribution layer may be refined, thereby improving the performance of the semiconductor package manufactured through the semiconductor package manufacturing method S1.
The semiconductor package 1A according to an embodiment may be manufactured through the semiconductor package manufacturing method S1 described above.
It will be appreciated by those skilled in the art to which the inventive concept belongs that the inventive concept described above may be practiced in other specific forms without altering its technical ideas or essential features. It should therefore be understood that the embodiments described above are examples and non-limiting in all respects.
Terms such as “same,” “equal,” “planar,” “coplanar,” “parallel,” and “perpendicular,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0113970 | Aug 2023 | KR | national |
