Patent Application
20240071845
This application claims priority to Korean Patent Application No. 10-2022-0110323, filed on Aug. 31, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a semiconductor package and a package-on-package including the semiconductor package, and more particularly, to a fan-out semiconductor package and a package-on-package including the fan-out semiconductor package.
As the electronics industry has rapidly developed, much smaller and lighter electronic apparatuses have been developed to satisfy users' demands, and thus, semiconductor devices, which are core components of electronic apparatuses, must be highly integrated. In addition, small and multifunctional semiconductor devices are needed along with the development of mobile products.
Therefore, semiconductor packages of a package-on-package type in which semiconductor packages having different functions are disposed on one another have been developed to provide multifunctional semiconductor packages.
Example embodiments provide a semiconductor package having high electrical reliability and a package-on-package including the semiconductor package.
Further, example embodiments provide a semiconductor package of which a lower redistribution layer, connection structures, and an upper redistribution layer are electrically tested together, and a package-on-package including the semiconductor package.
Further still, example embodiments relate to a semiconductor package and a package-on-package including the semiconductor package, and more particularly, to a fan-out semiconductor package and a package-on-package including the fan-out semiconductor package.
According to an aspect of an example embodiment, a semiconductor package includes: a redistribution layer including: a plurality of conductive lines; a plurality of conductive vias, each of the plurality of conductive vias being connected to at least one of the plurality of conductive lines; and a plurality of lower pads, each of the plurality of lower pads being connected to one of the plurality of conductive vias; a semiconductor chip provided on the redistribution layer; a plurality of external connection terminals attached to the plurality of lower pads; and a plurality of electrical paths configured for testing the plurality of conductive lines and the plurality of conductive vias, each of the plurality of electrical paths including at least one of the plurality of conductive lines and at least one of the plurality of conductive vias, wherein each of the plurality of electrical paths is connected to at least four external connection test terminals from among the plurality of external connection terminals.
According to an aspect of an example embodiment, a semiconductor package includes: a first redistribution layer including: a plurality of first conductive lines; a plurality of first conductive vias, each of the plurality of first conductive vias being connected to at least one of the plurality of first conductive lines; and a plurality of first lower pads, each of the plurality of first lower pads being connected to one of the plurality of first conductive vias; a semiconductor chip provided on the first redistribution layer; connection structures provided on the first redistribution layer and spaced apart from the semiconductor chip in a horizontal direction; a plurality of external connection terminals attached to the plurality of first lower pads; a second redistribution layer provided on the connection structures, the second redistribution layer including: a plurality of second conductive lines; a plurality of second conductive vias, each of the plurality of second conductive vias being connected to at least one of the plurality of second conductive lines; a plurality of second lower pads, each of the plurality of second lower pads being connected to one of the plurality of second conductive vias, a plurality of second upper pads; and a plurality of electrical paths configured for testing (i) the plurality of first lower pads, the plurality of first conductive lines, and the plurality of first conductive vias, or (ii) the plurality of second lower pads, the plurality of second conductive lines, and the plurality of second conductive vias, wherein each of the plurality of electrical paths includes at least one of the plurality of first conductive lines and at least one of the plurality of first conductive vias, wherein each of the plurality of electrical paths is connected to at least four external connection test terminals from among the plurality of external connection terminals, and wherein the at least four external connection test terminals include: at least two first test terminals configured to input a test input signal; and at least two second test terminals configured to output a test output signal.
According to an aspect of an example embodiment, a package-on-package includes: a first semiconductor package; and a second semiconductor package, wherein the first semiconductor package includes: a first redistribution layer including: a plurality of first conductive lines; a plurality of first conductive vias, each of the plurality of first conductive vias being connected to at least one of the plurality of first conductive lines; and a plurality of first lower pads, each of the plurality of first lower pads being connected to one of the plurality of first conductive vias; a first semiconductor chip provided on the first redistribution layer and including chip pads; connection structures provided on the first redistribution layer and spaced apart from the first semiconductor chip in a horizontal direction; a plurality of external connection terminals attached to the plurality of first lower pads; a second redistribution layer provided on the connection structures, the second redistribution layer including: a plurality of second conductive lines; a plurality of second conductive vias, each of the plurality of second conductive vias being connected to at least one of the plurality of second conductive lines; a plurality of second lower pads, each of the plurality of second lower pads being connected to one of the plurality of second conductive vias, and a plurality of second upper pads, wherein the second semiconductor package is provided on the first semiconductor package, wherein the second semiconductor package includes: a second semiconductor chip; and package connection terminals configured to electrically connect the second semiconductor chip to the second redistribution layer; wherein the package-on-package further includes a plurality of electrical paths configured for testing (i) the plurality of first lower pads, the plurality of first conductive lines, and the plurality of first conductive vias, or (ii) the plurality of second lower pads, the plurality of second conductive lines, and the plurality of second conductive vias, wherein each of the plurality of electrical paths includes at least one of the plurality of first conductive lines; and at least one of the plurality of first conductive vias, wherein each of the plurality of electrical paths is connected to at least four external connection test terminals from among the plurality of external connection terminals, wherein the external connection test terminals include: at least two first test terminals configured to input a test input signal; and at least two second test terminals configured to output a test output signal, wherein the external connection test terminals are provided in a plurality of first areas that are respectively adjacent to a plurality of vertices of the first redistribution layer, or are provided in a second area adjacent to a center of the first semiconductor chip, wherein the at least two first test terminals are electrically connected to each other through a lowermost conductive line of the plurality of first conductive lines, and wherein the at least two second test terminals are electrically connected to each other through a lowermost conductive line of the plurality of first conductive lines.
The above and/or other aspects will be more clearly understood from the following detailed description of example embodiments taken in conjunction with the accompanying drawings in which:
Hereinafter, example embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and repeated descriptions thereof are omitted.
Referring to
The semiconductor package 1 may be a fan-out semiconductor package in which the horizontal width and the horizontal area of the lower redistribution layer 100 are respectively greater than the horizontal width and the horizontal area of the footprint of the semiconductor chip 10, and the horizontal width and the horizontal area of the upper redistribution layer 200 are respectively greater than the horizontal width and the horizontal area of the footprint of the semiconductor chip 10. For example, when the semiconductor package 1 includes one semiconductor chip 10, the horizontal width and the horizontal area of the lower redistribution layer 100 may be respectively greater than the horizontal width and the horizontal area of the semiconductor chip 10, and the horizontal width and the horizontal area of the upper redistribution layer 200 may be respectively greater than the horizontal width and the horizontal area of the semiconductor chip 10. In one or more example embodiments, the horizontal width and the horizontal area of the lower redistribution layer 100 may be respectively equal to the horizontal width and the horizontal area of the upper redistribution layer 200. In one or more example embodiments, corresponding lateral surfaces of the lower redistribution layer 100, the extended layer 160, and the upper redistribution layer 200 may be coplanar with one another.
The semiconductor chip 10 may include: a semiconductor substrate 12 having a semiconductor device 14 formed on an active surface of the semiconductor substrate 12; and a plurality of chip pads 16 provided on the active surface of the semiconductor substrate 12. In one or more example embodiments, when the semiconductor package 1 is a lower package of a package-on-package (PoP), the semiconductor package 1 may be referred to as a first semiconductor package and/or a lower semiconductor package, the semiconductor chip 10 may be referred to as a first semiconductor chip and/or a lower semiconductor chip, the semiconductor substrate 12 may be referred to as a first semiconductor substrate and/or a lower semiconductor substrate, the semiconductor device 14 may be referred to as a first semiconductor device and/or a lower semiconductor device, and the chip pads 16 may be referred to as first chip pads and/or lower chip pads.
The semiconductor substrate 12 may include, but is not limited to, for example, a semiconductor material such as silicon (Si). Alternatively, the semiconductor substrate 12 may include, but is not limited to, a semiconductor element such as germanium (Ge), or may include, but is not limited to, a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The semiconductor substrate 12 may include a conductive region such as a well that is doped with a dopant. The semiconductor substrate 12 may have various device isolation structures such as a shallow trench isolation (STI) structure.
The semiconductor device 14 including a plurality of individual devices of various types may be formed on the active surface of the semiconductor substrate 12. The individual devices may include, but is not limited to, various microelectronic devices: for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor; a system large-scale-integration (LSI) device; an image sensor such as a CMOS imaging sensor (CIS); a micro-electro-mechanical system (MEMS); an active device; a passive device; or the like. The individual devices may be electrically connected to the conductive region of the semiconductor substrate 12. The semiconductor device 14 may include at least two of the individual devices, or may further include conductive wires or conductive plugs that electrically connect the individual devices to the conductive region of the semiconductor substrate 12. In addition, each of the individual devices may be electrically isolated from adjacent individual devices by an insulating layer.
The semiconductor chip 10 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In one or more example embodiments, when the semiconductor package 1 includes a plurality of semiconductor chips 10, some of the semiconductor chips 10 may be, but are not limited to, for example, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, flash memory chips, electrically erasable and programmable read-only memory (EEPROM) chips, phase-change random access memory (PRAM) chips, magnetic random access memory (MRAM) chips, or resistive random access memory (RRAM) chips.
The semiconductor chip 10 may be mounted on the lower redistribution layer 100 by a flip-chip method. That is, the semiconductor chip 10 may be mounted on the lower redistribution layer 100 such that the active surface of the semiconductor substrate 12 may face the lower redistribution layer 100.
The chip pads 16 of the semiconductor chip 10 electrically connected to the semiconductor device 14 may be electrically connected to the lower redistribution layer 100. A plurality of chip connection terminals 18 may be provided between the chip pads 16 and some of a plurality of first upper pads 124 to electrically connect the semiconductor chip 10 to a plurality of first redistribution patterns 120. For example, the chip connection terminals 18 may be, but are not limited to, solder balls or bumps.
The lower redistribution layer 100 may also be referred to as a lower wiring structure, a first wiring structure, and/or a first redistribution layer. The upper redistribution layer 200 may be referred to as an upper wiring structure, a second wiring structure, and/or a second redistribution layer.
The lower redistribution layer 100 may be disposed under the semiconductor chip 10, the extended layer 160, and the connection structures 162, and the lower redistribution layer 100 may redistribute the chip pads 16 of the semiconductor chip 10 to an external region. For example, the lower redistribution layer 100 may include a first redistribution insulating layer 110 and the first redistribution patterns 120.
The first redistribution insulating layer 110 may include an insulating material such as a photo-imageable dielectric (PID) resin and may further include photosensitive polyimide and/or an inorganic filler. The first redistribution insulating layer 110 may have a multilayer structure according to a multilayer structure of the first redistribution patterns 120. However, for ease of illustration,
The first redistribution patterns 120 may transmit electrical signals and/or transfer heat in the semiconductor package 1. The first redistribution patterns 120 may include a plurality of first lower pads 122, the first upper pads 124, a plurality of first redistribution line patterns 126, and a plurality of first conductive vias 128. For example, the first redistribution patterns 120 may include, but are not limited to, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof. However, the first redistribution patterns 120 are not limited to the one or more example embodiments described above.
The first lower pads 122 may be provided in a lower portion of the lower redistribution layer 100 and may electrically connect the lower redistribution layer 100 to the external connection terminals 150. Lower surfaces of the first lower pads 122 may be in direct contact with the external connection terminals 150, and upper surfaces of the first lower pads 122 may be in direct contact with lower surfaces of the first conductive vias 128.
According to one or more example embodiments, a lower surface of an element may refer to a surface of the element closest to one of the external connection terminals 150 in a vertical direction (Z direction), and an upper surface of the element may refer to a surface of the element that is opposite the lower surface of the element.
The first upper pads 124 may be provided in an upper portion of the lower redistribution layer 100 and may electrically connect the lower redistribution layer 100 to the semiconductor chip 10 and/or the connection structures 162. Lower surfaces of the first upper pads 124 may be in direct contact with upper surfaces of some of the first conductive vias 128, and upper surfaces of the first upper pads 124 may respectively be in direct contact with lower surfaces of the chip pads 16 and/or lower surfaces of the connection structures 162.
A photosensitive insulating material may be subjected to an exposure process and a developing process to form the first redistribution line patterns 126 and the first conductive vias 128. In one or more example embodiments, the first redistribution patterns 120 may be formed by depositing a metal or a metal alloy on a seed layer including titanium, titanium nitride, and/or titanium tungsten.
The first redistribution line patterns 126 may be provided on at least one of an upper surface and a lower surface of the first redistribution insulating layer 110. The first conductive vias 128 may penetrate at least one first redistribution insulating layer 110 and may respectively be in contact with some of the first redistribution line patterns 126. In one or more example embodiments, at least some of the first redistribution line patterns 126 may respectively be formed in one piece with some of the first conductive vias 128. For example, a first redistribution line pattern 126 may be formed in one piece with a first conductive vias 128, which is in contact with an upper surface of the first redistribution line pattern 126.
The first redistribution patterns 120, which include the first redistribution line patterns 126 and the first conductive vias 128, may be formed by a plating method. For example, the first redistribution patterns 120 may be formed by a plating method such as immersion plating, electroless plating, or electroplating.
The first conductive vias 128 may transmit electrical signals and/or transfer heat in the semiconductor package 1. The first conductive vias 128 may include, but are not limited to, a metal such as molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof. However, the first conductive vias 128 are not limited the one or more example embodiments described above. A photosensitive insulating material may be subjected to an exposure process and a developing process to form the first conductive vias 128.
In one or more example embodiments, the first conductive vias 128 may have a tapered shape extending with a horizontal width which decreases in a downward direction. That is, the horizontal width of each the first conductive vias 128 may decrease in a vertical direction (negative Z direction) away from the semiconductor chip 10.
External connection pads may be formed on the lower surfaces of the first lower pads 122, and the external connection terminals 150 may be provided on the external connection pads. The external connection terminals 150 may be electrically connected to the semiconductor chip 10 through the first redistribution patterns 120 of the lower redistribution layer 100. The external connection terminals 150 may connect the semiconductor package 1 to a main board of an electronic device on which the semiconductor package 1 is mounted. The external connection terminals 150 may be solder balls, which include a conductive material such as a metallic material including, but is not limited to, at least one selected from tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).
The external connection terminals 150 may include: first external connection terminals 152 through which a test input signal may be applied, and second external connection terminals 154 through which a test output signal may be output. The first external connection terminals 152 and the second external connection terminals 154 may be collectively referred to as test terminals. When the semiconductor package 1 is later connected to a system board, for example, a ground signal may be applied to the test terminals or may not be electrically connected to any external connection terminals 150 other than the test terminals. That is, the test terminals may be dummy external connection terminals. The first external connection terminals 152 may be first test terminals, and the second external connection terminals 154 may be second test terminals.
One electrical path may include two or more first external connection terminals 152 and two or more second external connection terminals 154. A plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, may be provided adjacent to each other.
Each of the plurality of first external connection terminals 152 may be connected to only one of an amperemeter and a voltmeter. In addition, each of the plurality of second external connection terminals 154 may be connected to only one of the amperemeter and the voltmeter. The plurality of first external connection terminals 152 to which the test input signals are applied may be electrically connected to each other at lowermost first redistribution line patterns 126. In addition, test output signals output through the plurality of second external connection terminals 154 may be electrically diverged from each other at the lowermost first redistribution line patterns 126.
As shown in
The lower redistribution layer 100 may further include a first upper solder resist layer 132 disposed on an upper surface of the lower redistribution layer 100. The first upper solder resist layer 132 may cover an upper surface of the at least one first redistribution insulating layer 110 and may expose the first upper pads 124. In one or more example embodiments, the first upper solder resist layer 132 may be formed by applying a solder mask insulation ink to upper and lower surfaces of the at least one first redistribution insulation layer 110 by a screen printing method or an inkjet printing method, and then curing the solder mask insulating ink with heat, ultraviolet (UV) light, or infrared (IR) light. In one or more other example embodiments, the first upper solder resist layer 132 is formed by operations comprising: completely applying a photosensitive solder resist to the upper surface of the at least one first redistribution insulating layer 110 by a screen printing method or a spray coating method, or bonding a film-type solder resist material by a laminating method; removing unnecessary portions through exposure and developing processes; and then curing the photosensitive solder resist or the film-type solder resist material with heat, UV or IR.
The extended layer 160 may include: the connection structures 162; and a filler member 164 surrounding the connection structures 162 and the semiconductor chip 10. The connection structures 162 may be apart from the semiconductor chip 10 in any horizontal direction (e.g., X direction and/or Y direction) and may be provided around the semiconductor chip 10. The connection structures 162 may penetrate the filler member 164 to electrically connect the lower redistribution layer 100 to the upper redistribution layer 200. Upper and lower ends of each of the connection structures 162 may respectively be connected to, and in contact with, one of a plurality of second conductive vias 228 of the upper redistribution layer 200 and one of the first upper pads 124 of the lower redistribution layer 100.
Each of the connection structures 162 may include a through-mold via (TMV), a conductive solder, a conductive pillar, or at least one conductive bump. In one or more example embodiments, each of the connection structures 162 may be formed by soldering, to each other, a lower portion attached to one of the first upper pads 124 of the lower redistribution layer 100 and an upper portion attached to one of the second conductive vias 228 of the upper redistribution layer 200 such that the lower portion and the upper portion may reflow by heat and form one body. The filler member 164 may include, but is not limited to, for example, an epoxy mold compound (EMC).
The upper redistribution layer 200 may include a second redistribution insulating layer 210 and second redistribution patterns 220. In addition, each of the second redistribution patterns 220 may include one of the second upper pads 222, one of the second redistribution line patterns 226, and one of the second conductive vias 228. The second redistribution insulating layer 210, the second redistribution line patterns 226, and the second conductive vias 228 are respectively similar to the first redistribution insulating layer 110, the first redistribution line patterns 126, and the first conductive vias 128, and thus repetitive descriptions thereof are omitted.
The second upper pads 222 may include a first connection pad 222-1 connected to the connection structures 162. The first connection pad 222-1 may be formed by connecting a plurality of second upper pads 222 to each other. Although
The upper redistribution layer 200 may further include a second upper solder resist layer 232 disposed on an upper surface of the upper redistribution layer 200. The second upper solder resist layer 232 may be substantially similar to the first upper solder resist layer 132.
A test unit 190 may test electrical characteristics of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200. The test unit 190 may include a first tip 192, a second tip 194 and a test probe head 196. The first tip 192 may be electrically connected to the first external connection terminals 152 to apply a test input signal of the test unit 190 to the first external connection terminals 152. The second tip 194 may be electrically connected to the second external connection terminals 154 to transmit a test output signal to the test unit 190. The test probe head 196 may apply the test input signal to the first tip 192. The test probe head 196 may receive the test output signal from the second tip 194.
The test unit 190 may perform a test process to measure electrical parameters of an electrical path. For example, the test unit 190 may include an ampere meter and/or a voltmeter. The electrical path may include, but is not limited to, the first external connection terminals 152, the first redistribution patterns 120, the connection structures 162, and the second redistribution patterns 220. The electrical path may include, but is not limited to, the first external connection terminals 152, the first redistribution line patterns 126, the first conductive vias 128, the connection structures 162, the second upper pads 222, the second redistribution line patterns 226, the second conductive vias 228, and the second external connection terminals 154. The test unit 190 may measure electrical parameters of each of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200.
One first external connection terminal and one second external connection terminal may be provided in one electrical path, and thus electrical parameter test sensitivity is relatively low. In addition, semiconductor packages may not provide an electrical path for testing a lower redistribution layer, connection structures, and an upper redistribution layer all together.
However, in the semiconductor package 1 of one or more example embodiments, a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154 are provided in one electrical path, and thus electrical parameter test sensitivity may be higher. In addition, the semiconductor package 1 of one or more example embodiments may include the first connection pad 222-1, and thus an electrical path for testing all of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200 may be provided.
The semiconductor package 1a in
Referring to one or more example embodiments shown in
A plurality of first external connection terminals 152 and a plurality of second external connection terminals 154 may be provided far from each other in an extending direction of the first connection pad 222-1a. That is, in a plan view, test terminals may be provided apart from each other in any of the horizontal directions (e.g., X direction and/or Y direction) on opposite sides of the semiconductor package 1a.
The semiconductor package 1b according to one or more example embodiments as shown in
Referring to one or more example embodiments as shown in
The second connection pad 124-1 may not be electrically connected to a semiconductor chip 10. That is, the second connection pad 124-1 may not be electrically connected to chip pads 16 of the semiconductor chip 10.
A test unit 190 may perform a test process to measure electrical parameters of an electrical path. The electrical path may include the first external connection terminals 152, the first lower pads 122, the first redistribution line patterns 126, the first conductive vias 128, and the second connection pad 124-1. The test unit 190 may measure electrical parameters of the lower redistribution layer 100a.
The first external connection terminals 152 and the second external connection terminals 154 may be provided adjacent to each other. In addition, second upper pads 222b of the upper redistribution layer 200b may not include a first connection pad (refer to the first connection pad 122-1 according to one or more example embodiments shown in
Referring to
According to one or more example embodiments as shown in
A plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, may be provided in any one of the first areas A1. When a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154 are provided in the first areas A1, electrical parameters of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200 may be measured. When a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, are provided in the same first area A1, electrical parameters of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200 of the semiconductor package 1 according to one or more example embodiments as shown in
In one or more example embodiments, a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, may be provided in different first areas A1. When a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, are provided in different first areas A1, electrical parameters of the lower redistribution layer 100, the connection structures 162, and the upper redistribution layer 200a of the semiconductor package 1a according to one or more example embodiments as shown in
In one or more example embodiments, a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154, which are included in one electrical path, may be provided in the second area A2. When a plurality of first external connection terminals 152 and a plurality of second external connection terminals 154 are provided in the second area A2, electrical parameters of the lower redistribution layer 100a shown according to one or more example embodiments as in
Referring to
The semiconductor package 2 may include a first upper solder resist layer 132 and a first lower solder resist layer 134, which are respectively provided on an upper surface and a lower surface of the lower redistribution layer 100b. In addition, the semiconductor package 2 may include a second upper solder resist layer 232 and a second lower solder resist layer 234, which are respectively provided on an upper surface and a lower surface of the upper redistribution layer 200c.
The first upper solder resist layer 132 may surround and protect first upper pads 124, and the first lower solder resist layer 134 may surround and protect first lower pads 122. The first upper solder resist layer 132 and the first lower solder resist layer 134 may form first solder resist layers 130.
The second upper solder resist layer 232 may surround and protect second upper pads 222, and the second lower solder resist layer 234 may surround and protect second lower pads 224. The second upper solder resist layer 232 and the second lower solder resist layer 234 may form second solder resist layers 230.
In addition, an underfill layer 50 may be disposed between a semiconductor chip 10 and the lower redistribution layer 100 to surround chip connection terminals 18. The underfill layer 50 may include, but is not limited to, for example, an epoxy resin and may be formed by a capillary underfill method. In one or more example embodiments, the underfill layer 50 may cover at least a portion of a lateral surface of the semiconductor chip 10.
For example, each of the connection structures 162 may include conductive solder. In addition, the upper redistribution layer 200c may include the second upper pads 222, the second lower pads 224, the second redistribution line patterns 226, and the second conductive vias 228.
Upper surfaces of the second lower pads 224 may be in contact with lower surfaces of some of the second conductive vias 228, and lower surfaces of the second lower pads 224 may be in contact with upper surfaces of some of the connection structures 162.
Referring to
The lower redistribution layer 100c may include a plurality of first lower pads 122, a plurality of first redistribution line patterns 126, and a plurality of first conductive vias 128.
For example, each of the connection structures 162 may be copper foil of an embedded trace substrate (ETS). Although
When copper foil of an ETS is selected as the connection structures 162, the semiconductor package 3 may additionally include a molding layer 170. The upper redistribution layer 200d may be formed on an upper surface of the molding layer 170. The upper redistribution layer 200d may include multi-layered copper wires for electrical connection with the copper foil of the ETS. The upper redistribution layer 200d may include second upper pads 222 and second conductive vias 228.
Chip pads 16 of a semiconductor chip 10 and the connection structures 162 may be connected to portions of the lower redistribution layer 100c while making direct contact with the portions of the lower redistribution layer 100c. For example, the chip pads 16 of the semiconductor chip 10 and the connection structures 162 may be connected to some of the first conductive vias 128 by direct contact therebetween.
Referring to
The lower redistribution layer 100c may include a plurality of first lower pads 122, a plurality of first redistribution line patterns 126, and a plurality of first conductive vias 128.
Chip pads 16 of a semiconductor chip 10 and the connection structures 162 may be connected to portions of the lower redistribution layer 100c while making direct contact with the portions of the lower redistribution layer 100c. For example, the chip pads 16 of the semiconductor chip 10 and the connection structures 162 may be connected to some of the first conductive vias 128 by direct contact therebetween.
Referring to
The second semiconductor package 400 may include at least one second semiconductor chip 40. The second semiconductor package 400 may be electrically connected to the first semiconductor package 1 through a plurality of package connection terminals 550 attached to a plurality of second upper pads 222 of the first semiconductor package 1 that are exposed without being covered with a second upper solder resist layer 232. In addition, the package connection terminals 550 may be electrically connected to a first connection pad 222-1 by direct contact with the first connection pad 222-1.
The at least one second semiconductor chip 40 may include: a second semiconductor substrate 42 having a second semiconductor device 44 formed on an active surface of the second semiconductor substrate 42; and a plurality of second chip pads 46 provided on the active surface of the second semiconductor substrate 42. The second semiconductor substrate 42, the second semiconductor device 44, and the second chip pads 46 according to the one or more example embodiments shown in
The at least one second semiconductor chip 40 may be a memory semiconductor chip. The at least one second semiconductor chip 40 may be, but is not limited to, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip.
Although
The package base substrate 500 may include a base board layer 510 and a plurality of board pads 520 provided on upper and lower surfaces of the base board layer 510. The board pads 520 may include a plurality of upper board pads 522 provided on the upper surface of the base board layer 510 and a plurality of lower board pads 524 provided on the lower surface of the base board layer 510. In one or more example embodiments, the package base substrate 500 may be a printed circuit board. For example, the package base substrate 500 may be a multi-layer printed circuit board. The base board layer 510 may include, but is not limited to, at least one material selected from a phenol resin, an epoxy resin, and polyimide.
A board solder resist layer 530 comprising the board pads 520 may be formed on the upper and lower surfaces of the base board layer 510. The board solder resist layer 530 may include: an upper board solder resist layer 532 covering the upper surface of the base board layer 510 and comprising the upper board pads 522; and a lower board solder resist layer 534 covering the lower surface of the base board layer 510 and comprising the lower board pads 524.
The package base substrate 500 may include board wiring 540, which electrically connects the upper board pads 522 and the lower board pads 524 to each other. The board wiring 540 may include board wiring lines and board wiring vias. The board wiring 540 may include, but is not limited to, nickel, stainless steel, or beryllium copper. In one or more example embodiments, the board wiring 540 may be disposed between the upper surface of the base board layer 510 and the upper board solder resist layer 532, and/or between the lower surface of the base board layer 510 and the lower board solder resist layer 534.
The upper board pads 522 may be electrically connected to the second semiconductor chip 40. For example, a plurality of second chip connection terminals 48 may be provided between the second chip pads 46 of the second semiconductor chip 40 and the upper board pads 522 of the package base substrate 500 to electrically connect the second semiconductor chip 40 and the package base substrate 500 to each other. In one or more example embodiments, a second underfill layer 450 surrounding the second chip connection terminals 48 may be disposed between the second semiconductor chip 40 and the package base substrate 500. For example, the second underfill layer 450 may include, but is not limited to, an epoxy resin and may be formed by a capillary underfill method. In one or more example embodiments, the second underfill layer 450 may be a non-conductive film.
An upper molding layer 490, which surrounds the second semiconductor chip 40, may be disposed on the package base substrate 500. The upper molding layer 490 may include, but is not limited to, for example, an epoxy mold compound (EMC). In one or more example embodiments, the upper molding layer 490 may cover an inactive surface of the second semiconductor chip 40. In one or more other example embodiments, the upper molding layer 490 may cover a lateral surface of the second semiconductor chip 40 but may not cover the non-active surface of the second semiconductor chip 40, and a heat dissipation member may be attached to the non-active surface of the second semiconductor chip 40.
Referring to one or more example embodiments shown in
Referring to one or more example embodiments shown in
Referring to one or more example embodiments shown in
Referring to one or more example embodiments shown in
While one or more example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0110323 | Aug 2022 | KR | national |
