Embodiments of the disclosure pertain to semiconductor packages that use thermal interface materials and, in particular, to a semiconductor package with a sealed thermal interface cavity with low thermal resistance liquid thermal interface material.
Thermal interface materials are used in packages to minimize thermal resistance between the die and the integrated heat spreader. Some conventional packages use polymer thermal interface material which suffers from low thermal conductivity and degradation after reliability testing. Solder thermal interface material offers better performance but requires die backside metallization which adds cost and complexity to the die fabrication process. In addition, solder thermal interface material is not compatible with ball-grid-array (BGA) products.
The low thermal conductivity of polymer thermal interface material becomes a significant drawback when a thick layer of thermal interface material is needed, e.g., to counter integrated heat spreader tilt or to make up for different die heights in a multichip package (MCP). The thermal degradation of polymer thermal interface material after reliability testing can be especially apparent near die edges after thermal cycling. Solder thermal interface material offers better performance but at the expense of requiring die back side metallization, which adds cost and complexity to the wafer fabrication process. Moreover, current solder thermal interface material is not compatible with BGA products. Conventional approaches do not provide a high volume manufacturing compatible process for using liquid metal thermal interface materials.
A semiconductor package with a sealed thermal interface cavity with low thermal resistance liquid thermal interface material is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Liquid metal thermal interface material has been shown experimentally to match and even exceed the thermal performance of solder thermal interface material both before and after reliability testing. In addition, liquid metal thermal interface material is very compliant. Compliance is an important characteristics for preventing large die stresses due to die/substrate warpage (especially during thermal cycling). Because liquid metal thermal interface material can be strongly reactive with metals such as aluminum, it is important to constrain it to the die-integrated heat spreader interface and eliminate the possibility of it leaking outside the package and reacting with other equipment (e.g., during assembly or at the OEM). Consequently, applying liquid metal thermal interface material in a high-volume manufacturing compatible manner and ensuring it is constrained to the desired locations (e.g., only between die and integrated heat spreader) presents significant challenges. Moreover, there is no process known or used today to enable the application of liquid metal thermal interface material to processor packages in high volume production.
Other thermal interface materials such as polymers suffer from low thermal conductivity and degradation after testing. In addition, thermal interface materials such as those based on solder are not compatible with ball grid array (BGA) technology. An approach that addresses and overcomes the shortcomings of previous approaches is disclosed herein. As part of the approach, an architecture and methodology for creating a sealed thermal interface cavity, that is filled with low thermal resistance, liquid metal thermal interface material, is disclosed. In an embodiment, the top and the bottom perimeter of the cavity are defined by parts of the top surface of the substrate and the upper inside surface of the integrated heat spreader. In other embodiments, the top and the bottom perimeter of the cavity are defined by the top surface of the semiconductor die and the upper inside surface of the integrated heat spreader. In an embodiment, a polymer is used to seal the integrated heat spreader and the substrate. In other embodiments, a polymer is used to define the lateral walls of the cavity and to seal the perimeter of the cavity. In an embodiment, the cavity is completely filled with liquid metal thermal interface material by means of a weak-vacuum-assisted, high-volume-manufacturing compatible process. The liquid metal thermal interface material is constrained to the cavity with no risk of the material leaking or reacting with external parts or equipment. The liquid metal is liquid at operating temperatures, characterized by low thermal resistance, and is non-toxic.
The disclosed approach provides a high volume manufacturing (HVM) compatible process and a package architecture in which a low thermal resistance, compliant thermal interface material is deployed that has a performance that is on-par with solder thermal interface material (STIM) but without requiring backside metallization (BSM) or having the other STIM associated challenges such as multichip package (MCP) and BGA incompatibility.
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In an embodiment, the substrate 101 can be formed from organic, ceramic, or glass materials and may contain metallic traces or vias. In other embodiments, the substrate 101 can be formed from other types of materials. In an embodiment, the air permeable adhesive 103 can be formed from polydimethylsiloxane (PDMS) or other silicones. In other embodiments, the air permeable adhesive 103 can be formed from other materials. In an embodiment, the integrated heat spreader 105 can be formed from materials such as copper, aluminum, nickel-plated copper or nickel-plated aluminum. In other embodiments, the integrated heat spreader 105 can be formed from other materials. In an embodiment, the liquid metal thermal interface material 109 can be formed from materials such as gallium, or an alloy of gallium with indium and/or tin. In other embodiments, the liquid metal thermal interface material 109 can be formed from other materials.
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In an embodiment, the substrate 201 can be formed from organic, ceramic, or glass materials and may contain metallic traces or vias. In other embodiments, the substrate 201 can be formed from other types of materials. In an embodiment, the air permeable adhesive 203a, 203b and 203c can be formed from PDMS or other silicones. In other embodiments, the air permeable adhesive 203a, 203b and 203c can be formed from other materials. In an embodiment, the integrated heat spreader 205 can be formed from materials such as copper, aluminum, nickel plated copper or nickel plated aluminum. In an embodiment, the integrated heat spreader 205 can be formed from other materials. In an embodiment, the thermal interface material 209a and 209b can be formed from materials such as gallium, an alloy of gallium with indium and/or tin, eutectic gallium indium, or gallinstan. In other embodiments, the thermal interface material 209a and 209b can be formed from other materials.
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In an embodiment, the electronic system 400 is a computer system that includes a system bus 420 to electrically couple the various components of the electronic system 400. The system bus 420 is a single bus or any combination of busses according to various embodiments. The electronic system 400 includes a voltage source 430 that provides power to the integrated circuit 410. In some embodiments, the voltage source 430 supplies current to the integrated circuit 410 through the system bus 420.
The integrated circuit 410 is electrically coupled to the system bus 420 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 410 includes a processor 412 that can be of any type. As used herein, the processor 412 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 412 includes, or is coupled with, semiconductor package 100 or semiconductor package 200, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 410 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 414 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 410 includes on-die memory 416 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 410 includes embedded on-die memory 416 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 410 is complemented with a subsequent integrated circuit 411. Useful embodiments include a dual processor 413 and a dual communications circuit 415 and dual on-die memory 417 such as SRAM. In an embodiment, the dual integrated circuit 410 includes embedded on-die memory 417 such as eDRAM.
In an embodiment, the electronic system 400 also includes an external memory 440 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 442 in the form of RAM, one or more hard drives 444, and/or one or more drives that handle removable media 446, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 440 may also be embedded memory 448 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 400 also includes a display device 450, an audio output 460. In an embodiment, the electronic system 400 includes an input device such as a controller 470 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 400. In an embodiment, an input device 470 is a camera. In an embodiment, an input device 470 is a digital sound recorder. In an embodiment, an input device 470 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 410 can be implemented in a number of different embodiments, including a package substrate including semiconductor package 100 or semiconductor package 200, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate including semiconductor package 100 or semiconductor package 200, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates including semiconductor package 100 or semiconductor package 200 embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.
A package includes a substrate, a die on the substrate, an integrated heat spreader on the substrate that encloses the die, the integrated heat spreader including a hole that extends through the integrated heat spreader, an air permeable adhesive contacting the integrated heat spreader and forming a cavity underneath the integrated heat spreader, and a liquid metal thermal interface material filling the cavity. A sealant plugs the hole that extends through the integrated heat spreader.
The package of example embodiment 1, wherein the air permeable adhesive is formed on a perimeter of the substrate.
The package of example embodiment 1, wherein the air permeable adhesive is formed on a perimeter of the die.
The package of example embodiment 1, wherein the air permeable adhesive is formed outside of a perimeter of the die and inside of a perimeter of the integrated heat spreader.
The package of example embodiment 3, wherein a material having greater conductivity than the air permeable adhesive is formed above the air permeable adhesive.
The package of example embodiment 5, wherein the material having greater conductivity than the air permeable adhesive determines a gap height between the integrated heat spreader and the die.
The package of example embodiment 6, wherein the hole is offset from the center of the die.
A package includes a substrate, a first die on the substrate, a second die on the substrate, an integrated heat spreader on the substrate and enclosing the first die and the second die, the integrated heat spreader including a first hole and a second hole that extend through the integrated heat spreader, a first air permeable adhesive contacting the integrated heat spreader and forming a first cavity underneath the integrated heat spreader and above the first die, the second air permeable adhesive contacting the integrated heat spreader and forming a second cavity underneath the integrated heat spreader and above the second die, a first liquid metal thermal interface material filling the first cavity, a second liquid metal thermal interface material filling the second cavity, and a first sealant plugging the first hole that extends through the integrated heat spreader. A second sealant plugs the second hole that extends through the integrated heat spreader.
The package of example embodiment 8, wherein the first die and the second die have different heights.
The package of example embodiment 8, wherein a third air permeable adhesive is formed on a perimeter of the substrate.
The package of example embodiment 8, wherein the first air permeable adhesive is formed on a perimeter of the first die.
The package of example embodiment 8, wherein the second air permeable adhesive is formed on a perimeter of the second die.
The package of example embodiment 8, wherein the first hole is formed above the first cavity.
The package of example embodiments 8, 9, 10, 11, 12 or 13 wherein the second hole is formed above the second cavity.
A method includes forming a substrate, placing a die on the substrate, placing an integrated heat spreader on the substrate and enclosing the die, the integrated heat spreader including a hole that extends through the integrated heat spreader, forming an air permeable adhesive to contact the integrated heat spreader and forming a cavity underneath the integrated heat spreader, and filling the cavity with a liquid metal thermal interface material. The hole that extends through the integrated heat spreader is plugged with sealant.
The method of example embodiment 15, wherein the air permeable adhesive is formed on a perimeter of the substrate.
The method of example embodiment 15, wherein the air permeable adhesive is formed on a perimeter of the die.
The method of example embodiment 15, wherein the air permeable adhesive is formed outside of perimeter of the die and inside of a perimeter of the integrated heat spreader.
The method of example embodiment 17, wherein a material having greater conductivity than the air permeable adhesive is formed above the air permeable adhesive.
The method of example embodiment 19, wherein the material having greater conductivity than the air permeable adhesive determines the gap height between the integrated heat spreader and the die.