Patent Application
20250087634
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0119965 filed in the Korean Intellectual Property Office on Sep. 8, 2023, the entire contents of which are incorporated herein by reference.
The present disclosure relates to semiconductor packages and to methods for manufacturing the same.
The semiconductor industry is seeking to improve integration density so that more passive or active devices can be integrated within a given region.
Among others, the development of technology to miniaturize the circuit line width of the semiconductor front-end process has gradually faced limitations. Accordingly, the semiconductor industry is in a trend of developing semiconductor packaging technology that can have a high integration density to compensate for the limitations of semiconductor front-end processes.
Following this trend, a 2.5D package technology has been developed in which high-bandwidth memory (HBM) and logic dies are arranged side by side, with the bottom surface of the HBM and the bottom surface of the logic die connected through a silicon interposer, and a substrate placed under the silicon interposer.
However, in 2.5D package technology, as the HBM and logic die are arranged side by side, the I/O between them may be relatively wide, and this arrangement of the I/O may slow down the speed of transferring signals and power within the semiconductor package.
In addition, 2.5D package technology including high-performance circuits may require reducing power loss to implement high-performance. Since the HBM and logic die are connected with a silicon interposer, power loss may be significant due to the silicon interposer.
Additionally, the use of expensive silicon interposers increases the price of semiconductor packages.
Additionally, since a surface mount device (SMD) may be under the substrate, the number of connection members under the substrate may be reduced. As a result, the horizontal size of the 2.5D package increases.
Therefore, it is desirable to develop a new semiconductor package technology capable of solving these issues of the conventional semiconductor package technology.
A 3.5D semiconductor package and a method for manufacturing the 3.5D semiconductor package may be provided, including a semiconductor stacked structure having a high-bandwidth memory (HBM) stacked on a logic die, a semiconductor die arranged side by side with the semiconductor stacked structure, and a surface mount device on the semiconductor stacked structure, without the use of a silicon interposer.
A semiconductor package according to some embodiments may include a substrate, a semiconductor stacked structure on the substrate, with the semiconductor stacked structure including a logic die and a high-bandwidth memory on the logic die, one or more semiconductor dies on the substrate and arranged side by side with the semiconductor stacked structure, and one or more surface mount devices (SMD) on the semiconductor stacked structure.
A semiconductor package according to some embodiments may include a substrate, a semiconductor stacked structure on the substrate, with the semiconductor stacked structure including a logic die, a high-bandwidth memory on the logic die, and a first molding material substantially surrounding the high-bandwidth memory on the logic die, the semiconductor package further including one or more semiconductor dies on the substrate and arranged side by side with the semiconductor stacked structure, one or more surface mount devices (SMD) on the semiconductor stacked structure, and a second molding material substantially surrounding the semiconductor stacked structure, the one or more semiconductor dies, and the one or more surface mount devices on the substrate.
A method for manufacturing a semiconductor package according to some embodiments may include forming a semiconductor stacked structure, with the semiconductor stacked structure including a logic die and a high-bandwidth memory on the logic die, mounting the semiconductor stacked structure on a substrate, mounting a surface mount device (SMD) on the semiconductor stacked structure, and mounting one or more semiconductor dies on the substrate and horizontally spaced apart from the semiconductor stacked structure.
By stacking HBM on a logic die without using a silicon interposer, it may be possible to reduce power loss, implement high performance, and/or reduce the price of the semiconductor package.
By providing a SMD on the semiconductor stacked structure, it may be possible to reduce the length of the electrical path between the semiconductor stacked structure and the SMD, and reduce power loss.
It may be possible to improve the performance of a semiconductor package by providing a memory die or a power management integrated circuit (PMIC) side by side with the semiconductor stacked structure.
Hereinafter, the inventive concepts of present disclosure will be described in detail hereinafter with reference to the accompanying drawings, in which some examples of embodiments of the present disclosure are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.
The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals may designate like elements throughout the specification.
Size and thickness of each constituent element in the drawings are arbitrarily illustrated for better understanding and ease of description, the following embodiments are not limited thereto.
Throughout the specification, the term “connected” does not mean only that two or more constituent components are directly connected, but may also mean that two or more constituent components are indirectly connected through another constituent component. In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, when an element is referred to as being “above” or “on” a reference element, it can be positioned above or below the reference element, and it is not necessarily referred to as being positioned “above” or “on” in a direction opposite to gravity.
Further, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.
Hereinafter, a semiconductor package 100 and a method for manufacturing the semiconductor package 100 according to some embodiments will be described with reference to the drawings.
Referring to
The substrate 110 may include a substrate base 111 and external connection members 112. In some embodiments, the substrate 110 may be or may include a printed circuit board. The substrate 110 may include electrical routing that mediates signals between the semiconductor stacked structure 120 and the semiconductor die 180. In some embodiments, the substrate 110 may include interconnect lines that electrically connect the semiconductor stacked structure 120 and the semiconductor die 180.
The substrate base 111 may include an insulating layer, wires, and vias. In some embodiments, the insulating layer may include at least one of a thermosetting epoxy resin and a resin containing a filler. In some embodiments, the insulating layer may include ajinomoto build-up film (ABF). In some embodiments, the wires and vias may each include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, or titanium, and/or alloys thereof. The external connection member 112 may electrically connect the semiconductor package 100 to an external device (not shown). In some embodiments, the external connection member 112 may include at least one of tin, silver, lead, nickel, or copper, and/or an alloy thereof.
The semiconductor stacked structure 120 may include a logic die 130, a high-bandwidth memory 140, and a first molding material 149. The semiconductor stacked structure 120 may be a 3D package having a three-dimensional stacked structure in which the high-bandwidth memory 140 is stacked on the logic die 130. The semiconductor package 100 may be a 3.5D semiconductor package including a semiconductor stacked structure 120, which may be a 3D package, and semiconductor dies 180 which may be arranged side by side with the semiconductor stacked structure 120. The semiconductor package 100 may include the semiconductor stacked structure 120 and the semiconductor die 180 arranged in a vertical direction on the substrate 110, with the semiconductor stacked structure 120 and the semiconductor die 180 arranged horizontally in one or more horizontal directions that intersect the vertical direction. The semiconductor die 180 may be spaced apart horizontally from the semiconductor stacked structure 120.
The logic die 130 may be at the bottom in the semiconductor stacked structure 120. The logic die 130 may include a logic die base 131, first connection pads 132, first through silicon vias (TSVs) 133, and second connection pads 134. In some embodiments, the logic die 130 may include a system on chip (SoC). In some embodiments, the logic die 130 may include an application processor (AP). In some embodiments, the logic die base 131 may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), system memory, a communication chip, a controller, and a sensor.
The first connection pads 132 may be between the first through silicon vias 133 and connection members 121. The first connection pad 132 may electrically connect the first through silicon via 133 to the connection member 121. In some embodiments, the first connection pads 132 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, or titanium, and/or alloys thereof.
The first through silicon vias 133 may be between the first connection pads 132 and the second connection pads 134. The first through silicon via 133 may electrically connect the second connection pad 134 to the first connection pad 132.
The first through silicon vias 133 may be formed by drilling thousands of fine holes that vertically penetrate or extend through each die and filling the holes with conductive material. In some embodiments, the holes of the first through silicon vias 133 may be formed by deep etching. In some embodiments, the holes of the first through silicon vias 133 may be formed by a laser. In some embodiments, the holes of the first through silicon vias 133 may be filled with a conductive material by electrolytic plating. In some embodiments, the first through silicon vias 133 may include at least one of tungsten, aluminum, or copper, and/or alloys thereof. Additionally, a barrier layer (not shown) may be formed between the logic die base 131 and the first through silicon via 133. In some embodiments, the barrier layer (not shown) may include at least one of titanium, tantalum, titanium nitride, or tantalum nitride, and/or alloys thereof. As such, the first through silicon vias 133 may be within the logic die base 131, and the first through silicon vias 133 are connected to the high-bandwidth memory 140 by a first interconnect structure 150. Therefore, it may be possible to increase the speed of transmitting and receiving signals and power between the logic die 130 and the high-bandwidth memory 140.
The second connection pads 134 may be between the first through silicon vias 133 and first bonding pads 151 of the first interconnect structure 150. The second connection pad 134 may electrically connect the first bonding pad 151 of the first interconnect structure 150 to the first through silicon via 133. In some embodiments, the second connection pads 134 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, or titanium, and/or alloys thereof.
The high-bandwidth memory 140 may be on (e.g., stacked on) the logic die 130. The high-bandwidth memory 140 may include a buffer die 141 and a plurality of stacked memory dies 142, 143, and 144. The high-bandwidth memory 140 may be a high-performance 3D stacked dynamic random access memory RAM (DRAM). The high-bandwidth memory 140 may be manufactured by stacking memory dies vertically to form one memory stack. The high-bandwidth memory 140 may have an advantage of having multiple memory channels through a memory stack of vertically stacked memory dies, enabling simultaneous implementation of low latency and high-bandwidth compared to conventional DRAM products, and reducing the total area occupied by individual DRAMs on a printed circuit board (PCB), which may be advantageous for high-bandwidth to area ratio, and reducing power consumption.
The buffer die 141 may be at the bottom in the high-bandwidth memory 140, and may be between the logic die 130 and the plurality of stacked memory dies 142, 143, and 144. When data is exchanged between devices with different data processing speeds, processing units and/or usage times, data loss may occur due to the differences in data processing speeds, processing units and/or usage times between each device. To prevent such loss, the buffer die 141 may be between the logic die 130 and the plurality of stacked memory dies 142, 143, and 144, and the information when exchanging data between the logic die 130 and the plurality of stacked memory dies 142, 143, and 144 may be temporarily stored in the buffer die 141. When transmitting data to the plurality of stacked memory dies 142, 143, and 144, or receiving data from the plurality of stacked memory dies 142, 143, and 144, the buffer die 141 may pass the data in order after aligning the sequence of the data.
The plurality of stacked memory dies 142, 143, and 144 may be on the buffer die 141. Each of the plurality of stacked memory dies 142, 143, and 144 may include DRAM. In some embodiments, the lowermost memory die 142 may be coupled to the buffer die 141 by hybrid bonding. In some embodiments, plurality of stacked memory dies 142, 143, and 144 may be coupled to each other by hybrid bonding. Although three stacked memory dies 142, 143, and 144 are shown in
The buffer die 141 and the plurality of stacked memory dies 142, 143, and 144 may include third connection pads 145, second through silicon vias 146, and fourth connection pads 147. In particular, the memory die 144 on the top of the high-bandwidth memory 140 generally does not include through silicon vias, but according to the present disclosure, for electrical connection with a surface mount devices 170 on the semiconductor stacked structure 120, the topmost or uppermost memory die 144 at the top of the high-bandwidth memory 140 may include the third connection pads 145, the second through silicon vias 146, and the fourth connection pads 147.
The third connection pads 145 of the buffer die 141 may be between the second through silicon vias 146 and second bonding pads 152 of the first upper connection structure 150. The third connection pad 145 of the buffer die 141 may electrically connect the second through silicon via 146 to the second bonding pad 152 of the first upper connection structure 150. The third connection pads 145 of each of the stacked memory dies 142, 143, and 144 may be between the second through silicon vias 146 and fourth bonding pads 162 of the second upper connection structure 160. The third connection pad 145 of each of the stacked memory dies 142, 143, and 144 may electrically connect the second through silicon via 146 to the fourth bonding pad 162 of the second upper connection structure 160. In some embodiments, the third connection pads 145 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, or titanium, and/or alloys thereof.
The second through silicon vias 146 may be between the third connection pads 145 and the fourth connection pads 147. The second through silicon via 146 may electrically connect the fourth connection pad 147 to the third connection pad 145.
The second through silicon vias 146 may be formed by drilling thousands of fine holes that vertically penetrate each die and filling the holes with conductive material. In some embodiments, the holes of the second through silicon vias 146 may be formed by deep etching. In some embodiments, the holes of the second through silicon vias 146 may be formed by a laser. In some embodiments, the holes of the second through silicon vias 146 may be filled with a conductive material by electrolytic plating. In some embodiments, the second through silicon vias 146 may include at least one of tungsten, aluminum, or copper, and/or alloys thereof. Additionally, a barrier layer (not shown) may be formed around the second through silicon via 146. In some embodiments, the barrier layer (not shown) may include at least one of titanium, tantalum, titanium nitride, or tantalum nitride, and/or alloys thereof.
The fourth connection pads 147 of the buffer die 141 may be between the second through silicon vias 146 and third bonding pads 161 of the second upper connection structure 160. The fourth connection pads 147 of the buffer die 141 may electrically connect the third bonding pad 161 of the second upper connection structure 160 to the second through silicon vias 146. The fourth connection pads 147 of each of the stacked memory dies 142 and 143 may be between the second through silicon vias 146 and the third bonding pads 161 of the second upper connection structure 160. The fourth connection pad 147 of each of the stacked memory dies 142 and 143 may electrically connect the third bonding pad 161 of the second upper connection structure 160 to the second through silicon via 146. The fourth connection pads 147 of the memory die 144 may be between the second through silicon vias 146 and connection members 171 of the surface mount device 170. The fourth connection pad 147 of the memory die 144 may electrically connect the connection member 171 of the surface mount device 170 to the second through silicon vias 146. In some embodiments, the fourth connection pads 147 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, or titanium, and/or alloys thereof.
The first interconnect structure 150 may be between the logic die 130 and the high-bandwidth memory 140. The logic die 130 and the high-bandwidth memory 140 may be bonded by hybrid bonding using the first interconnect structure 150. Hybrid bonding may be or may refer to a method of bonding two devices by fusing the same materials of the two devices using the bonding properties of the same materials. Here, hybrid means bonding two devices by two different types of bonding, for example, a first type of metal-to-metal bonding and a second type of non-metal-to-non-metal bonding. According to hybrid bonding, I/O with a fine pitch may be formed.
The first interconnect structure 150 may include the first bonding pads 151, the second bonding pads 152, a first silicon insulating layer 153, and a second silicon insulating layer 154. The first bonding pads 151 and the first silicon insulating layer 153 may be on the top surface of the logic die 130. The second bonding pads 152 and the second silicon insulating layer 154 may be on the bottom surface of high-bandwidth memory 140. The first bonding pad 151 may be directly bonded to the second bonding pad 152 by metal-metal hybrid bonding. The first silicon insulating layer 153 may be directly bonded to the second silicon insulating layer 154 by non-metal-non-metal hybrid bonding.
As such, according to the present disclosure, it may be possible to stack the high-bandwidth memory 140 on the logic die 130 using the first interconnect structure 150 without using a silicon interposer. Accordingly, it may be possible to implement relatively high-performance by reducing power loss that may occur due to the silicon interposer, and potentially avoid using relatively expensive silicon interposers, thereby reducing the price of the semiconductor package.
The second interconnect structure 160 may be between the buffer die 141 and the memory die 142, and between each of the stacked memory dies 142, 143, and 144 within the high-bandwidth memory 140. Within the high-bandwidth memory 140, the buffer die 141, the memory die 142, and each of the memory dies 142, 143, and 144 may be bonded by hybrid bonding using the second interconnect structure 160.
The second interconnect structure 160 may include the third bonding pads 161, the fourth bonding pads 162, a third silicon insulating layer 163, and a fourth silicon insulating layer 164. The third bonding pads 161 and the third silicon insulating layer 163 may be on the top surface of the buffer die 141 and the top surfaces of the stacked memory dies 142 and 143. The fourth bonding pads 162 and the fourth silicon insulating layer 164 may be on the bottom surfaces of the stacked memory dies 142, 143, and 144. The third bonding pad 161 may be directly bonded to the fourth bonding pad 162 by metal-metal hybrid bonding. The third silicon insulating layer 163 may be directly bonded to the fourth silicon insulating layer 164 by non-metal-non-metal hybrid bonding.
The first molding material 149 may be on the logic die 130 and mold or substantially surround the high-bandwidth memory 140. The top surface of the high-bandwidth memory 140 may not be molded by the first molding material 149. Stated differently, the top surface of the high-bandwidth memory 140 may be free from coverage by the first molding material 149.
One or more SMDs 170 may be on the semiconductor stacked structure 120. Stated differently, the substrate 110 may be on a first side of the semiconductor stacked structure 120, and the one or more SMDs 170 may be on a second side of the semiconductor stacked structure 120 that is opposite from the first side in a vertical direction. The SMD 170 may provide additional functionality or programming to the semiconductor package 100. The SMD 170 may include at least one of a resistor, an inductor, a capacitor, and a jumper. The SMD 170 may be electrically connected to the semiconductor stacked structure 120 by the connection members 171.
According to the present disclosure, the SMD 170, which was conventionally under the substrate (e.g., under the substrate 110), may be disposed on the top surface of the semiconductor stacked structure 120. In addition, the SMD 170 may be electrically connected to the second through silicon vias 146 of the memory die 144. Accordingly, it is possible to reduce the length of the electrical path between the semiconductor stacked structure 120 and the SMD 170 and power loss associated with the electrical path may be reduced.
One or more semiconductor dies 180 may be on the substrate 110. One or more semiconductor dies 180 may be arranged side by side with the semiconductor stacked structure 120. In some embodiments, one or more semiconductor dies 180 may include a power management integrated circuit (PMIC). In some embodiments, one or more semiconductor dies 180 may include multi-bank DRAM (M-DRAM).
According to the present disclosure, it may be possible to improve the performance of the semiconductor package by forming a logic die and a high-bandwidth memory, which were conventionally disposed side by side in a 2.5D package, into a 3D stacked structure, and disposing at least one of a PMIC and a M-DRAM at the position where a high-bandwidth memory was conventionally arranged.
The second molding material 190 may be on the substrate 110, and may mold or substantially surround the semiconductor stacked structure 120, one or more SMDs 170, and one or more semiconductor dies 180. In some embodiments, the top surface of the SMD 170 may be exposed to the outside from the second molding material 190. The top surface of the semiconductor die 180 may be exposed to the outside from the second molding material 190. Stated differently, the top surface of the SMD 170 and/or the top surface of the semiconductor die 180 may be free from coverage from the second molding material 190.
In
Referring to
The first interconnect structure 150 may include first connection members 155 and first insulating members 156. The first connection member 155 may be between the logic die 130 and the high-bandwidth memory 140. The first connection member 155 may electrically connect the third connection pad 145 of the buffer die 141 to the second connection pad 134 of the logic die 130. In some embodiments, the first connection member 155 may include micro bumps or solder balls. In some embodiments, the first connection member 155 may include at least one of tin, silver, lead, nickel, or copper, and/or an alloy thereof. The first insulating member 156 may be between the logic die 130 and the high-bandwidth memory 140 and surround the first connection members 155. Stress between the logic die 130 and the high-bandwidth memory 140 may be relieved by the first insulating member 156. The first insulating member 156 may include a non-conductive film (NCF).
The second interconnect structure 160 may include second connection members 165 and second insulating members 166. The second connection member 165 may be between the buffer die 141 of the high-bandwidth memory 140 and each of the stacked memory dies 142, 143, and 144 respectively, and may electrically connect them to each other.
In some embodiments, the second connection member 165 may include micro bumps or solder balls. In some embodiments, the second connection member 165 may include at least one of tin, silver, lead, nickel, or copper, and/or an alloy thereof. The second insulating member 166 may be between the buffer die 141 of the high-bandwidth memory 140 and each of the stacked memory dies 142, 143, and 144 and surround the second connection members 165. Stress between the buffer die 141 of the high-bandwidth memory 140 and each of the stacked memory dies 142, 143, and 144 may be relieved by the second insulating member 166. The second insulating member 166 may include the NCF.
In
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Afterwards, heat treatment may be performed to bond the first bonding pad 151 positioned on the top surface of the logic die 130 and the second bonding pad 152 positioned on the bottom surface of the high-bandwidth memory 140 by hybrid bonding.
The first bonding pad 151 may be directly bonded to the second bonding pad 152 by metal-metal hybrid bonding. Metal bonding may be made at the interface between the first bonding pad 151 and the second bonding pad 152 by metal-metal hybrid bonding.
In some embodiments, the first bonding pad 151 and the second bonding pad 152 may each include copper. In some embodiments, the first bonding pad 151 and the second bonding pad 152 may each be made of a metallic material to which hybrid bonding may be applied. The first bonding pad 151 and the second bonding pad 152 may be made of the same material, such that after hybrid bonding, the interface between the first bonding pad 151 and the second bonding pad 152 may disappear. The logic die 130 and the high-bandwidth memory 140 may be electrically connected to each other through the first bonding pad 151 and the second bonding pad 152.
The first silicon insulating layer 153 may be directly bonded to the second silicon insulating layer 154 by non-metal-non-metal hybrid bonding. Covalent bonding may be made at the interface between the first silicon insulating layer 153 and the second silicon insulating layer 154 by non-metal-non-metal hybrid bonding. In some embodiments, the first silicon insulating layer 153 and the second silicon insulating layer 154 may each include silicon oxide or TEOS forming oxide. In some embodiments, the first silicon insulating layer 153 and the second silicon insulating layer 154 may each include SiO2. In some embodiments, the first silicon insulating layer 153 and the second silicon insulating layer 154 may each be silicon nitride, silicon oxynitride, or other suitable dielectric material. In some embodiments, the first silicon insulating layer 153 and the second silicon insulating layer 154 may each include SiN or SiCN. The first silicon insulating layer 153 and the second silicon insulating layer 154 may be made of the same material, such that after hybrid bonding, the interface between the first silicon insulating layer 153 and the second silicon insulating layer 154 may disappear.
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First, a non-conductive film (NCF) may be attached as the first insulating member 156 on the logic die 130. The NCF may have adhesive properties and may be attached to the logic die 130. The NCF has an uncured state that can be deformed by external force. Next, the high-bandwidth memory 140 may be stacked on the NCF. The first connection member 155 provided in the high-bandwidth memory 140 may penetrate the NCF and contact the second connection pad 134 of the logic die 130.
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While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0119965 | Sep 2023 | KR | national |
