This invention relates generally to a semiconductor power device. More particularly, the present invention relates to a semiconductor power device having single in-line lead module and the method of making the semiconductor power device.
An electronic equipment, for example a power tool, may contain several power devices. Conventionally, metal-oxide semiconductor field-effect transistor (MOSFET) chips of those several power devices are fabricated and assembled in several different packages. The MOSFET chips are placed side-by-side. A pre-determined gap width between adjacent MOSFET chips is required to increase heat dissipation. Each package requires a separate pick-and-place process. It is not space efficient nor time efficient in a board level mounting step. It generates excessive impedance from board level interconnection.
The present disclosure discloses a semiconductor power device having semiconductor chip stacks. Each chip stack contains a high-side MOSFET chip, a low-side MOSFET chip and a clip connecting a source pad of the high-side MOSFET chip to a drain pad of the low-side MOSFET chip. In one example, clip interconnection is applied to a main power path, for example a source path or a drain path of a MOSFET chip of an N-channel module. In another example, a top surface of a clip is exposed from an encapsulation and a bottom surface of a lead frame unit is exposed from the encapsulation. It reduces the number of the pick-and-place processes. It is more space efficient and time efficient in a board level mounting step.
This invention discloses a semiconductor power device comprising a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip.
This invention further discloses a method for fabricating semiconductor power devices. The method comprises the steps of providing a lead frame strip having a plurality of lead frame units; providing two or more pluralities of single in-line leads; attaching two or more high-side semiconductor chips to each lead frame unit; connecting each of the two or more high-side semiconductor chips to a respective lead by a respective clip of two or more first clips; attaching a respective low-side semiconductor chip of the two or more low-side semiconductor chips to each clip of the two or more first clips; molding an encapsulation; and singulating the lead frame strip and the encapsulation to form the semiconductor power devices.
In block 102, a lead frame strip 200 of
Two or more pluralities of single in-line leads 360A, 360B and 360C of
In block 104, two or more high-side semiconductor chips 312, 314 and 316 of
In block 106, each of the high-side semiconductor chips 312, 314 and 316 is connected to a source lead 362, 364 or 366 (a first lead) of a respective plurality of single in-line leads of the two or more pluralities of single in-line leads 360A, 360B and 360C by a respective clip of two or more first clips 442, 444 and 446. The clip 442 has a first end 452, a bridge 456 and a second end 454. The bridge 456 connects the first end 452 to the second end 454. A bottom surface of the first end 452 is attached to a top surface of the high-side semiconductor chip 312 through a second layer of conductive bonding material. In examples of the present disclosure, the source pad 322 of the high-side semiconductor chip 312 is electrically and mechanically connected to the clip 442. A bottom surface of the second end 454 is attached to a top surface of the source lead 362 through a third layer of conductive bonding material. A region 472 of the top surface of the high-side semiconductor chip 312 is not covered by the clip 442. Therefore, the gate pad 332 is accessible in the wire bonding step of block 112. Similarly, a region 474 of the top surface of the high-side semiconductor chip 314 is not covered by the clip 444 and a region 476 of the top surface of the high-side semiconductor chip 316 is not covered by the clip 446. Block 106 may be followed by block 108.
In block 108, a respective semiconductor chip of two or more low-side semiconductor chips 512, 514 and 516 of
In block 110, a source pad 522, 524 or 526 of each semiconductor chip of the two or more low-side semiconductor chips 512, 514 and 516 is connected to ground. In examples of the present disclosure, each of the source pad 522, 524 or 526 of the low-side semiconductor chips 512, 514 and 516 is connected to a ground lead 662, 664 or 666 (a second lead) of a respective plurality of single in-line leads of the two or more pluralities of single in-line leads 360A, 360B and 360C by a respective clip of two or more second clips 642, 644 and 646. The clip 642 has a first end 652, a bridge 656 and a second end 654. The bridge 656 connects the first end 652 to the second end 654. A bottom surface of the first end 652 is attached to a top surface of the low-side semiconductor chip 512 through a fifth layer of conductive bonding material. In examples of the present disclosure, the source pad 522 of the low-side semiconductor chip 512 is electrically and mechanically connected to the clip 642. A bottom surface of the second end 654 is attached to a top surface of the ground lead 662 through a sixth layer of conductive bonding material.
In examples of the present disclosure, a linked clip 842 of
In examples of the present disclosure, a respective wire 982, 984 or 986 of
In examples of the present disclosure, wire 1062 of
In block 112, wire bonding is applied. A first respective wire 692, 694 or 696 of
In block 114, an encapsulation 722 of
In examples of the present disclosure, at least a majority portion of the respective clip of the two or more second clips 642, 644 and 646 is embedded in the encapsulation 722 of
In one example, the linked clip 842 is entirely embedded in the encapsulation. In another example, as shown in
In block 116, the lead frame strip 200 and the encapsulation 722 are singulated to form the semiconductor power devices. In examples of the present disclosure, a semiconductor power device includes two or more semiconductor chip stacks. In one example, a first chip stack includes the lead frame unit 302, the high-side semiconductor chip 312, the clip 442 and the low-side semiconductor chip 512. The first chip stack may further includes the clip 642. In examples of the present disclosure, the two or more first clips 442, 444 and 446, the two or more second clips 642, 644 and 646, and the linked clip 842 are made of a conductive metal material. In one example, the conductive metal material is copper. In another example, the conductive metal material is nickel.
Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, the elevations of a first and second ends of a clip may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.
This Patent Application is a Divisional Application of a pending application Ser. No. 15/191,414 filed on Jun. 23, 2016. The Disclosure made in the patent application Ser. No. 15/191,414 is hereby incorporated by reference.
Number | Date | Country | |
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Parent | 15191414 | Jun 2016 | US |
Child | 15659587 | US |