Patent Application
20250022840
The embodiments relate to the field of power products and production methods thereof, including relating to a semiconductor power entity and a method for producing such entity by hybrid bonding, a hybrid bonding method, and a corresponding structure.
In order to increase power density and efficiency in next generation power packages, short, current-capable low-parasitic interconnection paths, a very good thermal management and electrical isolation are essential. Conductor traces with a current capability of several ten Amperes up to hundreds of Amperes, and power modules with an internal stray inductance below 10 nH are the current targets.
In today's chip embedding technology, only limited interconnect capabilities are available. For making connections between two vertically arranged power semiconductors on 2 different core layers, only micro-via interconnects are possible that are produced outside of both component's projected physical outline, i.e., outside of the die area. The through-via has to be placed in a minimum distance of about 400 to 500 μm from the embedded component edge in order to account for via process tolerances. This leads to a long routing distance and results in a high commutation loop inductance. Another severe disadvantage of this arrangement is the thermal decoupling by the usually low thermally conductive laminate layer between the two dies. Depending on the cooling situation on either side of the assembly, the dies could reach different operating temperature and develop a dispersive switching behavior.
The embodiments provide a solution for semiconductor power products and manufacturing such power products without the above-described disadvantages.
For example, the embodiments present a solution for a semiconductor power entity that has improved thermal characteristics and provides low parasitic interconnection paths.
The foregoing and other objects are achieved by the embodiments. Further implementation forms are apparent from the description and the figures.
A solution presented in the embodiments achieves these objects at a feasible cost by the combination of vertical system integration (3rd dimension), panel level packaging, and low temperature metal joining (e. g. diffusion soldering or sintering). By the combination of these technologies, at least the following advantages can be realized:
Vertical system integration (3D-integration) drastically shortens interconnect length and allows to significantly increase the power density. According to the embodiments, this technology can be used in an industrialized scale for chip embedding or other panel level packaging technologies and for power device packaging.
Hybrid bonding according to the embodiments is a process that allows simultaneously bonding of metallic contacts & dielectric areas in one bonding process. Hybrid bonding can be used for 3D-integration on wafer level. A direct surface activated bonding (SAB) process can be used, which may require specialized high vacuum equipment and tight control of surface quality with a roughness in the range of about 1 nm, for example. This makes hybrid bonding in its current form unsuitable for power electronics packaging. The embodiments present a mechanism to make this technology available for panel level hybrid bonding process for power electronics packaging.
Chip embedding according to the embodiments employs PCB (printed circuit board) materials interfacing directly with the semiconductor die. In addition to excellent electrical and thermal performance, chip embedding (CE) offers at least the benefits of panel scale mass production. Currently, CE, which is still new technology, is not yet used for 3D stacking. It could be used, but due to limitations, e.g., direct vertical connections, it is not yet used (only one core layer, i.e., laminate layer).
According to the embodiments, vertical connections can be implemented between pre-manufactured PCB layers, resulting in a connection layer that embeds large connection metal areas in isolation material, achieving sufficient current carrying capability and thermal conductivity for power electronics.
The embodiments are based on the concept where direct vertical connections can be made between two or more laminate core layers, also referred to as laminate layers or core layers, where the vertical connections have the following characteristics: they can be made within the projected physical outline of embedded components; they are not confined to a certain shape (e. g. round) or size (e. g. 100 μm diameter); they do not need an outer layer plating process to form the electrical connection; they are suitable for power electronics (have low inductance and high current capability); they are reliable and do not remelt at bond temperature; they can be formed either by diffusion soldering or sintering.
A method or process to form these vertical connections has at least the following characteristics: using a standard PCB lamination process (bond temperature, pressure, format); using hybrid bonding to bond metal to metal and dielectric to dielectric in one step; several premanufactured layers can be connected to each other in one lamination step or in several sequential lamination steps; the bonding materials can be attached or applied to the surface of the laminate layers or placed between the laminate layers prior to bonding.
In case of diffusion soldering, the vertical metal-to-metal connection can be based on the formation of intermetallic phases in a selected bi- or multi metal system. The structure can have a minimum of three layers that contain at least one metal or metal alloy layer that has a low melting point and which is located between two separate metal layers that have a high melting point.
Some low melting point metals that can be used are, e.g., tin (Sn) and indium (In) and the high melting point metal or top metal layers are, e.g., copper (Cu), gold (Au), and silver (Ag). In diffusion soldering, the two high melting point metal layers can be bonded together by aim of at least one low temperature melting metal layer. During the bonding the layer can be pressed against each other and the temperature can be increased above the eutectic point for the selected metal system. Because the temperature is above the eutectic point of the selected metal system a liquid phase can appear and the metals can start to inter-diffuse and create intermetallic compounds (IMCs). Because the formed inter-metallics have a higher melting point, those are gradually solidified. If the bonding time is long enough all low melting point metals react with the high melting point metals to form inter-metallics and the joint is completely solidified. The formed intermetallic compounds have a significantly higher melting point than the low melting point metals and the joint does not melt anymore at the bonding temperature.
The diffusion soldering process can be divided into five phases that are wetting, alloying, liquid diffusion, gradual solidification and solid diffusion. The suitable metal, metal alloy or paste on one or both laminate layers or between the laminate layers (with metal) can be applied by plating, printing, dispensing or other suitable methods. Diffusion soldering or sintering can be used, for example, to form the metallic interconnection.
The described semiconductor power entity can be described by at least the following features, including: two or more laminate layers that i) are laminated together with isolating polymer layer; ii) have Cu metal routing at least on top and bottom side; iii) are electrically connected together with a non-re-meltable metal joint embedded in the isolating polymer layer.
Other features include: all laminate layers are PCB core layer in panel level (up to normal PCB production sizes); at least one laminate layer has power components embedded inside; the first power die in the first laminate layer and the second power die in the second laminate layer can face in different directions, but are not limited to this, in some other applications they can also face in the same direction. In one example, the first power die in the first laminate layer and the second power die in the second laminate layer can be arranged in a half bridge configuration. It may be understood that many other configurations of the two power dies can be implemented as well.
In order to describe the embodiments in detail, the following terms, abbreviations and notations will be used:
The embodiments relate to a semiconductor power entity according to a first aspect, a method for producing such semiconductor power entity according to a second aspect, a computer program product according to a third aspect, and a non-transitory computer-readable medium according to a fourth aspect, as described in the following.
According to the first aspect, the embodiments relate to a semiconductor power entity, including: a first laminate layer having a first laminate upper main face and a first laminate lower main face opposing the first laminate upper main face; a second laminate layer having a second laminate upper main face and a second laminate lower main face opposing the second laminate upper main face; an isolation layer arranged between the first laminate layer and the second laminate layer; a first metal layer arranged at the first laminate upper main face of the first laminate layer and a second metal layer arranged at the first laminate lower main face of the first laminate layer; a third metal layer arranged at the second laminate upper main face of the second laminate layer and a fourth metal layer arranged at the second laminate lower main face of the second laminate layer; and a connection metal layer embedded in the isolation layer between the first laminate layer and the second laminate layer, the connection metal layer forming an electrical connection with the second metal layer and the third metal layer.
Such a semiconductor power entity provides at least the advantage of having direct vertical connections between two or more laminate core layers. These vertical connections can be made within the projected physical outline of embedded components if the laminate layer have such embedded components; they are not confined to a certain shape or size, i.e., they can be flexibly designed in shape and size; they do not need an outer layer plating process to form the electrical connection; they are suitable for power electronics, since they have low inductance and high current capability; they are reliable and do not remelt at bond temperature. These vertical connections can be formed, for example by solid-liquid interdiffusion (SLID), transient liquid phase (TLP) bonding or sintering.
Thus, the semiconductor power entity provides increased power density and efficiency, short, current-capable low-parasitic interconnection paths, a very good thermal management and improved electrical isolation. Conductor traces with a current capability of several ten Amperes up to hundreds of Amperes and even higher, and power modules with an internal stray inductance below about 10 nH and even lower can be achieved.
The first, second, third, and fourth metal layers can be redistribution or routing metal layers for redistributing or routing current paths. It can be understood that the semiconductor power entity is not restricted to these four metal layers and two laminate layers as examples shown in the Figures. The semiconductor power entity can also have more layers. The layers that are laminated may also be the layers of a multi-layer board, e.g., four layers or six layers, instead of the two-layer boards that are shown here in the Figures which are only examples for such a multi-layer board.
The semiconductor power entity can also be referred to as semiconductor power product. Such product can also be a module or a larger size product (PCB), for example, where the power components may be embedded inside the PCB and the rest of the components may be placed on top. Some or all of the passives may also be embedded in the PCB, depending on the passive components, e.g., depending on a type of the passive components.
In an exemplary implementation of the semiconductor power entity, the connection metal layer forms a non-remelting electrical and mechanical connection.
Such a “non-remelting” connection is different from a normal solder connection such as formed during a conventional TC/NCP process (thermo-compression bonding with solder and pre-applied non-conductive polymer). A non-remelting connection provides at least the advantage that it is a connection which will not remelt or decompose at temperatures much higher than the process temperature it was formed.
In an exemplary implementation of the semiconductor power entity, the connection metal layer forms one of a diffusion soldering connection or a sintering connection.
Diffusion soldering or diffusion bonding is a metal joining technique which can be advantageously applied to electronic packaging. It operates on the principle of interdiffusion of two dissimilar metals, where a liquid phase is completely transformed into solid state by metallic phase reactions and intermetallic compound formation. Similar terms for such technique are transient liquid phase bonding, solid-liquid interdiffusion, isothermal solidification. The technique provides at least the advantage that the resulting solid phase has a higher melting point than the temperature of the formation process.
Sintering is the process of compacting and forming a solid mass of material by heat or pressure without melting it to the point of liquefaction. Sintering happens as part of a manufacturing process used with metals, ceramics, plastics, and other materials. The atoms in the materials diffuse across the boundaries of the particles, fusing the particles together and creating one solid piece. An advantage of sintering is the following: because the sintering temperature does not have to reach the melting point of the material, sintering is often chosen as the shaping process for materials with extremely high melting points.
The connection metal can form a composed metal layer, for example. Such composed metal layer may include a compound from more than two metals, e.g., such as inter-metallic layer, or a connection of metal layers including one single metal, or a connection of a metal and a polymer or polymer mixture.
For such inter-metallic layer, the melting point of the inter metallic layer is higher than the lamination/process temperature where it was formed.
The connection metal layer may include more than 80% metal and less than 20% pores or polymers, for example.
The connection metal layer is designed for high current loads.
In one embodiment, the inter-metallic layer may have a minimum lateral size of >1 mm in each dimension, but not smaller than 0.1 mm.
The intermetallic layer may have a large cross-section, short length and good conductor and due to that is suitable for high current loads.
In one embodiment, the connection metal layer may have a thickness of 5 to 50 um, but not thicker than 0.2 mm (in case of a single layer structure).
In an exemplary implementation of the semiconductor power entity, the first laminate layer is embedding a first power semiconductor; and/or the second laminate layer is embedding a second power semiconductor.
Such a semiconductor power entity provides at least the advantage of increased power density and efficiency, short, current-capable low-parasitic interconnection paths, a very good thermal management and improved electrical isolation. Conductor traces with a high current capability of, e.g., several ten amperes up to hundreds of amperes, and power modules with an internal stray inductance, e.g., below about 10 nH can be implemented.
When defining a first power semiconductor and a second power semiconductor this does not exclude that more than one first power semiconductor can be embedded in the first laminate layer and more than one second power semiconductor can be embedded in the second laminate layer.
In an exemplary implementation of the semiconductor power entity, the connection metal layer vertically connects the second metal layer with the third metal layer providing a vertical electrical connection for the first power semiconductor and the second power semiconductor.
This provides at least the advantage that a shortest-path electrically connection can be realized which reduces stray inductance of the power entity and impedance between the two metal layers.
In an exemplary implementation of the semiconductor power entity, the connection metal layer forms a direct electrical connection path between the first power semiconductor and the second power semiconductor without a detour via through-hole vias arranged laterally to the two power semiconductors.
As described above, such a direct electrical connection path provides at least the advantage of shortest-path large area electrical connection between the two metal layers, reducing impedance and stray inductance.
In an exemplary implementation of the semiconductor power entity, the second metal layer and/or the third metal layer includes at least one of copper, gold, silver, palladium or nickel or a combination thereof; where in case of a diffusion soldering connection, the connection metal layer includes any suitable low temperature melting metal like for example tin and indium in combination with any of the metals of the second metal layer or the third metal layer or an alloy thereof; where in case of a sintering connection, the connection metal layer includes a porous layer of silver or copper or other suitable sintering metal with optional polymer filling.
This provides at least the advantage that a lot of metals and metal alloys or combinations thereof with different characteristics can be applied
Note that such connection metal layer includes also the following combination: (tin OR indium OR (tin AND indium)) in combination with any of the metals of the second metal layer or the third metal layer or an alloy thereof.
In an exemplary implementation of the semiconductor power entity, the first power semiconductor and the second power semiconductor are configured to form a half bridge configuration. It can be understood that a lot of other configurations of the two power semiconductors can be implemented as well.
This provides at least the advantage that the semiconductor power entity can be efficiently used in automotive power conversion systems and in other applications of the semiconductor power entity. The half bridge configuration is a reoccurring key topology element in power electronics conversion circuits.
In an exemplary implementation of the semiconductor power entity, the first power semiconductor is a vertical device including at least one first terminal opposing the first laminate upper main face and a second terminal opposing the first laminate lower main face; and the second power semiconductor is a vertical device including at least one first terminal opposing the second laminate upper main face and a second terminal opposing the second laminate lower main face.
This provides at least the advantage that the semiconductor power entity can provide high current density, high power dissipation and high reverse breakdown voltage.
In an alternative exemplary implementation of the semiconductor power entity, the first power semiconductor can be a lateral device and the second power semiconductor can be a lateral device.
In an exemplary implementation of the semiconductor power entity, as described below with respect to
Such a design provides at least the advantage that the shortest path between the two facing inner terminals of the power semiconductors can be used for electrical connection. This results in low parasitic impedance, high current capability of this buried connection due to large area. It can be even made larger than the die itself. Without the described technique, such connections are only possible by arrangement of through-holes at the periphery outside the projected die area.
By such design both power semiconductors can be fully embedded in the respective laminate layers which results in excellent electrical performance.
In an alternative embodiment, as shown below with respect to
These large area connections have at least the advantage that configurations are possible that allow further optimization of a) parasitic impedance by shortening the electrical path, or b) thermal path by enabling direct heat extraction without microvias at the outer surface of the entity.
In an exemplary implementation of the semiconductor power entity, as described below with respect to
Such a design provides at least the advantage of large area chip connection on one side of the chip with the respective metal layer which provides improved thermal dissipation and improved electrical performance.
In an exemplary implementation of the semiconductor power entity, the second power semiconductor has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face; where the second semiconductor upper main face is coplanar arranged with the second laminate upper main face to form an electrical connection between the at least one first terminal of the second power semiconductor and the third metal layer at the second laminate upper main face; and where the second terminal of the second power semiconductor forms an electrical connection with the fourth metal layer at the second laminate lower main face by one or more microvias extending through the second laminate layer. Alternatively, the second semiconductor lower main face is coplanar arranged with the second laminate lower main face to form an electrical connection between the second terminal of the second power semiconductor and the fourth metal layer at the second laminate lower main face; and where the at least one first terminal of the second power semiconductor forms an electrical connection with the third metal layer at the second laminate upper main face by one or more microvias extending through the second laminate layer
Such a design provides at least the same advantage of large area chip connection on one side of the chip with the respective metal layer as described above. This large area chip connection results in improved thermal dissipation and improved electrical performance.
According to the second aspect, the embodiments relate to a method for producing a semiconductor power entity, as described below with respect to
Such method or process provides at least the advantage to form the above-described vertical connections. The method or process provides at least the following advantageous characteristics: use of a standard PCB lamination process with respect to bond temperature, pressure, format; use of hybrid bonding to bond metal to metal and dielectric to dielectric in one step; several premanufactured layers can be connected to each other in one lamination step or in several sequential lamination steps; the bonding materials can be attached or applied to the surface of the laminate layers or placed between the laminate layers prior to bonding.
In an exemplary implementation of the method, the connection metal layer is formed simultaneously with the lamination of the first laminate layer, the second laminate layer and the isolation layer.
This provides at least the advantage that the fabrication method can be simplified due to performing two production steps simultaneously.
In an exemplary implementation of the method, as described below with respect to
This provides at least the advantage of flexibility in the sequence of the different production steps. It does not matter, for example, to which laminate layer the bonding metal or the isolation layer is applied to. They only need to be complementary.
In an exemplary implementation of the method, applying the bonding metal includes plating of metals, printing or dispending of pastes, placing of preforms; and where applying the isolation layer includes printing, coating, laminating or dispensing of dielectric material.
This provides at least the advantage of providing alternatives for application of the bonding metal and application of the isolation layer.
In an exemplary implementation of the method, as described below with respect to
This provides at least the advantage of flexibility in the sequence of the different production steps.
In an exemplary implementation of the method, as described below with respect to
This provides at least the advantage of flexibility in the sequence of the different production steps.
In an exemplary implementation of the method, as described below with respect to
This provides at least the advantage of providing alternatives for placement of the isolation layer.
Following process steps of the above method may be optional: drilling holes in the semiconductor power entity extending from the first metal layer to the fourth metal layer, where the holes are drilled laterally to the first and second power semiconductors; metal plating the holes to form metal plated through holes electrically connecting the first and optionally second, third metal layers with the fourth metal layer; and structuring the first metal layer and the fourth metal layer.
According to the third aspect, the embodiments relate to a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the method according to the second aspect described above.
The computer program product may run on a controller or a processor for implementing the above method to produce the semiconductor power entity according to the first aspect described above.
According to a fourth aspect, the embodiments relate to a non-transitory computer-readable medium, storing instructions that, when executed by a computer, cause the computer to execute the method according to the second aspect described above. Such a computer readable medium may be a non-transient readable storage medium. The instructions stored on the non-transitory computer-readable medium may be executed by a controller or a processor.
Further embodiments will be described with respect to the following figures, in which:
In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the embodiments may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from their scope. The following detailed description, therefore, is not to be taken in a limiting sense.
It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.
In the embodiments, diffusion soldering is described. The principle of diffusion soldering is applied to microelectronics since the 1960ies. It is also known as solid liquid interdiffusion (SLID), transient liquid phase bonding (TLPB), or isothermal solidification. It was since then applied to 3D-integration/chip-stacking and MEMS wafer level encapsulation. Diffusion soldering is an irreversible process, the connection does not remelt at the same temperature it is formed, but at a much higher temperature because all low-temperature melting solder is transformed into intermetallic compounds which have a higher melting temperature.
In the embodiments, sintering is described. Sintering is another low temperature metal joining technology that allows to make non-remeltable stable and reliable connections at a relatively low bond temperature. It is based on the high self-diffusion and surface diffusion property of some metals (silver and copper are most known and applied today), for example if the initially surface is very large. In some situations, a paste is printed and dried on a noble metal surface. The paste contains silver particles of different sizes and with a specific coating that prevents premature agglomeration and unwanted sintering. Under temperature and pressure, the dried paste densifies into a porous metal layer that forms a metallurgical bond with the compatible metal surfaces in contact. Another way to offer large sinterable metal surfaces is in form of metal filaments or wires that are grown on the contact surface, with diameters in the lower m down to upper nm range and lengths of several tens of m.
In
The semiconductor power product 13 is characterized by an indirect electrical path 14 with high parasitics (R, L) and an interrupted thermal path.
In
In contrast to the semiconductor power product 13 of
This embodiments present a method how two or more laminate layers, (with or without embedded dies), e.g., two or more of the laminate embedded power die panels 11 shown in
One basic idea of the embodiments is that during one single process step the metal areas can be electrically and thermally connected using SLID bonding, diffusion bonding, sintering or nano wires and the other areas can be bonded, laminated or glued together with nonconductive polymer material. The bonding process can be performed at a relatively low temperature. The metals and polymer bonding materials can be selected in such a way that the bonding can be realized in approximately the same or lower temperature than the curing of the polymer bonding material. The method allows to irreversibly connect two layers with embedded components vertically together with a non-remeltable connection that allows excellent electrical and thermal performance and high reliability.
The hybrid bonding method according to the embodiments includes the following steps: providing the laminate with redistribution layer (RDL); applying bond materials to the bond surfaces of the laminates or panels to be connected, e.g., metallization for SLID, TLPS, polymer/glue; the lay-up step; the lamination/bonding step; and the singulation step. It understands that additional PCB processes can be done between these steps.
Several possible options for the application of the materials to the bond surface, the structure of the bond materials, and the interaction of the bond materials with the bond surface are described below.
This embodiments provide an essential building block for power packaging on panel level, for example for laminate based large scale packaging. It enables more degrees of freedom in design of current capable in-package electrical and thermal connections in the vertical dimension. The vertical connections can have different areas and shapes by design. They can be used to effectively shorten critical conductor lengths or strengthen the thermal path.
Using hybrid bonding as shown in
The semiconductor power entity 100, also referred to as a semiconductor power product, includes a first laminate layer 110 having a first laminate upper main face 111 and a first laminate lower main face 112 opposing the first laminate upper main face 111; and a second laminate layer 120 having a second laminate upper main face 121 and a second laminate lower main face 122 opposing the second laminate upper main face 121.
The semiconductor power entity 100 includes an isolation layer 130 arranged between the first laminate layer 110 and the second laminate layer 120.
The semiconductor power entity 100 includes a first metal layer 113 arranged at the first laminate upper main face 111 of the first laminate layer 110 and a second metal layer 114 arranged at the first laminate lower main face 112 of the first laminate layer 110.
The semiconductor power entity 100 includes a third metal layer 123 arranged at the second laminate upper main face 121 of the second laminate layer 120 and a fourth metal layer 124 arranged at the second laminate lower main face 122 of the second laminate layer 120.
The semiconductor power entity 100 includes a connection metal layer 160 embedded in the isolation layer 130 between the first laminate layer 110 and the second laminate layer 120. The connection metal layer 160 is forming an electrical connection with the second metal layer 114 and the third metal layer 123.
The first, second, third and fourth metal layers 113, 114, 123, 124 can be redistribution or routing metal layers for redistributing or routing current paths.
As mentioned above, the semiconductor power entity can also be referred to as semiconductor power product. Such product can also be a module or a larger size product (PCB), for example, where the power components are embedded inside the PCB and the rest of the components on top. As described above, also part of the passives can be embedded inside the PCB.
The connection metal layer 160 can form a non-remelting electrical and mechanical connection.
Such a “non-remelting” connection is different from a normal solder connection such as formed during a conventional TC/NCP process (thermo-compression bonding with solder and pre-applied non-conductive polymer). A non-remelting connection is a connection which does not remelt in same temperatures at which the connection was formed.
The connection metal layer 160 can form one of a diffusion soldering connection or a sintering connection as described above.
The connection metal 160 can form a composed metal layer, for example. Such composed metal layer may include a compound from more than two metals, e.g., such as inter-metallic layer, or a connection of metal layers including one single metal, or a connection of a metal and a polymer or polymer mixture.
For such inter-metallic layer, the melting point of the inter metallic layer is higher than the lamination/process temperature where it was formed.
The connection metal layer may include more than 80% metal and less than 20% pores or polymers, for example.
The connection metal layer is designed for high current loads.
In one embodiment, the inter-metallic layer may have a minimum lateral size of greater than 1 mm in each dimension, but not smaller than about 0.1 mm.
The intermetallic layer may have a large cross-section, short length and good conductor and due to that is suitable for high current loads.
In one embodiment, the inter-metallic layer may have a thickness of about 5 to 50 μm, but not thicker than about 0.2 mm (in case of a single layer structure).
As mentioned above, the laminate layers may embed or not embed power dies.
The first laminate layer 110 may embed a first power semiconductor 140 as shown in
When defining a first power semiconductor and a second power semiconductor this does not exclude that more than one first power semiconductor can be embedded in the first laminate layer 110 and more than one second power semiconductor can be embedded in the second laminate layer 120.
The connection metal layer 160 may vertically connect the second metal layer 114 with the third metal layer 123 providing a vertical electrical connection for the first power semiconductor 140 and the second power semiconductor 150.
The connection metal layer 160 may form a direct electrical connection path between the first power semiconductor 140 and the second power semiconductor 150 without a detour via through-hole vias arranged laterally to the two power semiconductors 140, 150, e.g., as exemplarily illustrated by the direct connection path 24 in
The second metal layer 114 and/or the third metal layer 123 may include at least one of copper, gold, silver, palladium or nickel or a combination thereof. In case of a diffusion soldering connection, the connection metal layer 160 may include any of a suitable low temperature melting metal like for example the metals tin and indium in combination with any of the metals of the second metal layer 114 or the third metal layer 123 or an alloy thereof. In case of a sintering connection, the connection metal layer 160 may include a porous layer of silver or copper or other suitable sintering metal with optional polymer filling.
Note that such connection metal layer can include also the following combination: (tin OR indium OR (tin AND indium)) in combination with any of the metals of the second metal layer (114) or the third metal layer (123) or an alloy thereof.
The first power semiconductor 140 and the second power semiconductor 150 may be configured to form a half bridge configuration.
The first power semiconductor 140 can be a vertical device including at least one first terminal 141, 143 (e.g., source 141 and gate 143 as shown in
The second power semiconductor 150 can be a vertical device including at least one first terminal 151, 153 (e.g., source 151 and gate 153 as shown in
The semiconductor power entity 100 may include at least one first via 115 and at least one second via 116 extending through the first laminate layer 110. The at least one first via 115 may form an electrical connection between the at least one first terminal 141, 143 of the first power semiconductor 140 and the first metal layer 113. The at least one second via 116 may form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114.
The semiconductor power entity 100 may include at least one third via 125 and at least one fourth via 126 extending through the second laminate layer 120. The at least one third via 115 may form an electrical connection between the at least one first terminal 151, 153 of the second power semiconductor 150 and the third metal layer 123. The at least one fourth via 126 may form an electrical connection between the second terminal 152 of the second power semiconductor 150 and the fourth metal layer 124.
In an alternative embodiment as described below with respect to
This second embodiment is similar to the first embodiment, but the first power semiconductor 140 is directly connected to the second metal layer 114 without applying vias. Similarly, the second power semiconductor 150 is directly connected to the fourth metal layer 124 without applying vias in between.
In this second embodiment, the first power semiconductor 140 has a first semiconductor upper main face and a first semiconductor lower main face opposing the first semiconductor upper main face. The second power semiconductor 150 has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face.
The first semiconductor lower main face is coplanar arranged with the first laminate lower main face 112 to form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114 at the first laminate lower main face 112. The at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 forms an electrical connection with the first metal layer 113 at the first laminate upper main face 111 by one or more microvias 115 extending through the first laminate layer 110.
Similarly, the second semiconductor lower main face is coplanar arranged with the fourth laminate lower main face 122 to form an electrical connection between the second terminal 152 (e.g., drain) of the second power semiconductor 150 and the fourth metal layer 124 at the second laminate lower main face 122. The at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 forms an electrical connection with the third metal layer 123 at the second laminate upper main face 121 by one or more microvias 125 extending through the second laminate layer 120.
This third embodiment is similar to the first embodiment, but the first power semiconductor 140 is directly placed below and connected to the first metal layer 113 without applying vias in between. Similarly, the second power semiconductor 150 is directly placed on and connected to the fourth metal layer 124 without applying vias in between. In this third embodiment, a direct electrical and thermal path is implemented to outer surface of the power entity. This third embodiment is beneficial at least for heat extraction to external heatsink because the main thermal path has no microvias. It is further beneficial at least for lowest stray inductance for half-bridge configurations, where MOSFET 1 (140) is the low side switch and MOSFET 2 (150) is the high-side switch.
In this third embodiment, the first power semiconductor 140 has a first semiconductor upper main face and a first semiconductor lower main face opposing the first semiconductor upper main face. The second power semiconductor 150 has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face.
The first semiconductor upper main face is coplanar arranged with the first laminate upper main face 111 to form an electrical connection between the at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 and the first metal layer 113 at the first laminate upper main face 111. The second terminal 142 (e.g., drain) of the first power semiconductor 140 forms an electrical connection with the second metal layer 114 at the first laminate lower main face 112 by one or more microvias 116 extending through the first laminate layer 110.
Similarly, the second semiconductor lower main face is coplanar arranged with the fourth laminate lower main face 122 to form an electrical connection between the second terminal 152 (e.g., drain) of the second power semiconductor 150 and the fourth metal layer 124 at the second laminate lower main face 122. The at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 forms an electrical connection with the third metal layer 123 at the second laminate upper main face 121 by one or more microvias 125 extending through the second laminate layer 120.
This fourth embodiment is similar to the first embodiment, but the first power semiconductor 140 is directly placed on the second metal layer 114 without applying vias. Similarly, the second power semiconductor 150 is directly placed below the third metal layer 123 without applying vias.
In this fourth embodiment, the first power semiconductor 140 has a first semiconductor upper main face and a first semiconductor lower main face opposing the first semiconductor upper main face. The second power semiconductor 150 has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face.
The first semiconductor lower main face is coplanar arranged with the first laminate lower main face 112 to form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114 at the first laminate lower main face 112. The at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 forms an electrical connection with the first metal layer 113 at the first laminate upper main face 111 by one or more microvias 115 extending through the first laminate layer 110.
Similarly, the second semiconductor upper main face is coplanar arranged with the second laminate upper main face 121 to form an electrical connection between the at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 and the third metal layer 123 at the second laminate upper main face 121. The at second terminal 152 (e.g., drain) of the second power semiconductor 150 forms an electrical connection with the fourth metal layer 124 at the second laminate lower main face 122 by one or more microvias 125 extending through the second laminate layer 120.
This fifth embodiment is similar to the first embodiment, but the first power semiconductor 140 is directly placed below the first metal layer 113 without applying vias. Similarly, the second power semiconductor 150 is directly placed below the third metal layer 123 without applying vias.
In this fifth embodiment, the first power semiconductor 140 has a first semiconductor upper main face and a first semiconductor lower main face opposing the first semiconductor upper main face. The second power semiconductor 150 has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face.
The first semiconductor upper main face is coplanar arranged with the first laminate upper main face 111 to form an electrical connection between the at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 and the first metal layer 113 at the first laminate upper main face 111. The second terminal 142 (e.g., drain) of the first power semiconductor 140 forms an electrical connection with the second metal layer 114 at the first laminate lower main face 112 by one or more microvias 116 extending through the first laminate layer 110.
Similarly, the second semiconductor upper main face is coplanar arranged with the second laminate upper main face 121 to form an electrical connection between the at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 and the third metal layer 123 at the second laminate upper main face 121. The second terminal 152 (e.g., drain) of the second power semiconductor 150 forms an electrical connection with the fourth metal layer 124 at the second laminate lower main face 122 by one or more microvias 125 extending through the second laminate layer 120.
In all
The semiconductor power entity includes an isolation layer 130, e.g., made of polymer material, arranged between the first laminate layer 110 and the second laminate layer 120, where the isolation layer 130 can be either arranged in between the laminate layers 110, 120 during stack-up or be attached/applied to either but not both of the laminate layers 110, 120 facing main faces before stack-up.
The semiconductor power entity may include a first metal layer 113 arranged at the first laminate upper main face 111 of the first laminate layer 110 (not shown in
The semiconductor power entity of
The semiconductor power entity of
The semiconductor power entity of
The semiconductor power entity of
The semiconductor power entity of
In the semiconductor power entities shown in
The embodiments shown in
Table 1: Example of possible metal systems for low temperature joining. Columns: High temperature melting metals; Rows: Low temperature melting metals and sinter materials. The cell content denotes the type of non-remelting metal joint that can be formed by that combination: Either “Diff. sold.”=diffusion soldering (SLID, TLPB) or “Sinter”=sintering.
Table 1 is non-exhaustive. It lists some practical and available metal combinations. It can be understood that this table 1 is just an example not limiting the embodiments to these combinations. All other suitable low temperature diffusion solder metal combinations and all other low temperature sinter metals and particle shapes may be applied as well.
The following metals and bonding layer options may exist inter alia (see Table 1):
1) The high temperature melting metal can be one layer structure (e.g. Cu. Ni) or multilayer structure (e.g. Cu+Au, Cu+Ni, Ni+Au, Cu+Ni+Au).
2) The low temperature melting metal can be Sn, In or some other suitable metal, metal alloy or combination of several metals e.g., SnAg, InSn.
3) The bonding layer can be liquid or film type polymer material e.g. epoxy, epoxy mixture, BT epoxy, PI or other type of polymer that is compatible with laminate materials
4) The bonding material can be uncured, precured or semicured.
The following metal stack options are illustrated in
a) The low melting and high melting metals on laminate can be a simple one-layer structure or printed paste on only one laminate layer (high melting metal+low temperate metal/metal alloy stack), see
b) The low melting and high melting metals on laminate can be a simple one layer structure or printed paste on both laminate layers (high melting metal+low temperate metal/metal alloy stack), see
c) The low melting and high melting metals on laminate can be a multilayer sandwich or other type of structure on one or both laminate layers (high+low+high+low . . . ), see
d) The low melting temperate metal or metal alloy or metal paste can be in a separate preform that is placed between the laminates, see
The following process/step options can be applied:
1) The low temperature metal or metal alloy or metal paste layer and/or polymer bonding layer is on one or two sides of the laminate.
2) The low temperature metal or metal alloy or metal compound layer is on one or two side of the laminate and the polymer bonding layer is brought between in separate step.
3) The polymer bonding layer is on one or two side of the laminate and the low temperature metal or metal alloy or metal paste preform is brought between in separate step.
4) The polymer bonding layer and the low temperature metal or metal alloy or metal paste preform are brought between in the laminate during layup process.
The different process flow options are described below with respect to
This process option 1—Resin printing—describes a process where the polymer bonding material is printed, coated, laminated; dispensed, etc., on one (or two) laminate layers and the bonding metal is plated, printed, dispensed on one (or two) laminate layers before the bonding.
In a first step, two premanufactured laminate layers, also referred to as core layers or laminate core layers, are provided 401 which are printed with the polymer bonding material. The two premanufactured laminate layers may correspond to the first laminate layer 110 and the second laminate layer 120 described above with respect to
In a second step, the first premanufactured laminate layer 110 is coated 402a with the polymer bonding material and the second premanufactured laminate layer 120 is coated 402b with low melting point metal or metal alloy or paste.
In a third step, the second premanufactured laminate layer 120 is turned around and arranged above the first premanufactured laminate layer 110 to provide a layup 403
In a fourth step, the layup 403 is laminated 404 to provide a semiconductor power product.
In a fifth step, one or more holes are drilled 405 in the semiconductor power product.
In a sixth step, the one or more holes are plated 406 by a conductive metal layer
In a seventh step, the semiconductor power product is structured 407, e.g., by structuring the first metal layer 113 and the fourth metal layer 124.
If no holes 170 are used at this phase, the metal layer can also be structured in an earlier phase and this seventh step is not needed. This applies as well to all other process options 2 to 4 described below.
Depending on the design and application the above-described fifth, sixth and seventh steps are optional and can be applied as well to all other process options 2 to 4 described below.
This process option 2—Non-structured resin sheet—describes a process where the bonding metal is plated, printed, dispensed on one (or two) laminate layers before the bonding and the non-structured polymer material is placed between the laminate layers during layup and lamination process.
In a first step, two premanufactured laminate layers 411 are provided that may correspond to the first laminate layer 110 and second laminate layer 120 described above with respect to
In a second step one of the premanufactured laminate layers is printed or plated 412 with low melting point metal or metal alloy.
In a third step, a layup 413 is provided of the first and second premanufactured laminate layers and a polymer layer in between.
In a fourth step, the layup 403 is laminated 414 to provide a semiconductor power product.
In a fifth step, one or more holes are drilled 415 in the semiconductor power product.
In a sixth step, the one or more holes are plated 416 by a conductive metal layer
In a seventh step, the semiconductor power product is structured 417, e.g. by structuring the first metal layer 113 and the fourth metal layer 124.
If no holes 170 are used at this phase, the metal layer can also be structured in an earlier phase and this seventh step is not needed. Depending on the design and application the above-described fifth, sixth and seventh steps are optional.
This process option 3—Structured prepreg or resin sheet—describes a process where the bonding metal is plated, printed, dispensed on one (or two) laminate layers before the bonding and the structured polymer material is placed between the laminate layers during layup and lamination process.
In a first step, two premanufactured laminate layers 421 are provided that may correspond to the first laminate layer 110 and second laminate layer 120 described above with respect to
In a second step, activator material is printed, sprayed, etc. 422a on the first premanufactured laminate layer and the premanufactured second laminate layer is printed or plated 422b with low melting point metal or metal alloy.
In a third step 423, a layup 423 is provided of the first and second premanufactured laminate layers and a structured polymer layer in between.
In a fourth step, the layup 423 is laminated 424 to provide a semiconductor power product.
In a fifth step, one or more holes are drilled 425 in the semiconductor power product.
In a sixth step, the one or more holes are plated 426 by a conductive metal layer
In a seventh step, the semiconductor power product is structured 427, e.g., by structuring the first metal layer 113 and the fourth metal layer 124.
If no holes 170 are used at this phase, the metal layer can also be structured in an earlier phase and this seventh step is not needed. Depending on the design and application the above-described fifth, sixth and seventh steps are optional.
This process option 4—Preform placement—describes a process where the polymer bonding material is printed, coated, laminated, dispensed, etc., on one (or two) laminate layers and the bonding metal preform is placed (e.g. pick and placement process) on copper pad on lover laminate layers before the bonding before the bonding.
In a first step, two premanufactured laminate layers 431 are provided that may correspond to the first laminate layer 110 and second laminate layer 120 described above with respect to
In a second step, one of the two premanufactured laminate layers 431 is printed with resin and the resign is dried 432
In a third step, a low melting point metal preform is placed on the resign printed premanufactured laminate layer and a layup 433 is provided together with the other premanufactured laminate layer.
In a fourth step, the layup 423 is laminated 434 to provide a semiconductor power product.
In a fifth step, one or more holes are drilled 435 in the semiconductor power product.
In a sixth step, the one or more holes are plated 436 by a conductive metal layer
In a seventh step, the semiconductor power product is structured 437, e.g., by structuring the first metal layer 113 and the fourth metal layer 124.
If no holes 170 are used at this phase, the metal layer can also be structured in an earlier phase and this seventh step is not needed. Depending on the design and application the above-described fifth, sixth and seventh steps are optional.
The semiconductor power entity can be a semiconductor power entity 100, 100b, 100c, 100d, 100e as described above with respect to
The method 500 includes providing 501 a first laminate layer 110 embedding a first power semiconductor 140, the first laminate layer 110 having a first laminate upper main face 111 and a first laminate lower main face 112 opposing the first laminate upper main face 111, where a first metal layer 113 is arranged at the first laminate upper main face 111 of the first laminate layer 110 and a second metal layer 114 is arranged at the first laminate lower main face 112 of the first laminate layer 110, e.g., as described above with respect to
The method 500 includes providing 502 a second laminate layer 120 embedding a second power semiconductor 150, the second laminate layer 120 having a second laminate upper main face 121 and a second laminate lower main face 122 opposing the second laminate upper main face 121, where a third metal layer 123 is arranged at the second laminate upper main face 121 of the second laminate layer 120 and a fourth metal layer 124 is arranged at the second laminate lower main face 122 of the second laminate layer 120, e.g., as described above with respect to
The method 500 includes applying 503 a bonding metal at the second metal layer 114 of the first laminate layer 110 and/or the third metal layer 123 of the second laminate layer 120, the bonding metal being placed between the first power semiconductor 140 and the second power semiconductor 150 and/or between respective electrical contact pairs in the first laminate layer and the second laminate layer, e.g., as described above with respect to
The method 500 includes arranging 504 an isolation layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120, e.g., as described above with respect to
The method 500 includes laying-up and laminating 505 the first laminate layer 110, the second laminate layer 120 and the isolation layer 130 to a semiconductor power entity 100, where the laminating transforms the bonding metal to a connection metal layer 160 forming an electrical connection with the second metal layer 114 and the third metal layer 123, e.g., as described above with respect to
The connection metal layer 160 may be formed simultaneously with the lamination of the first laminate layer 110, the second laminate layer 120 and the isolation layer 130.
The method 500 may further include: applying 503 the bonding metal at the second metal layer 114 of the first laminate layer 110 before the laying-up and laminating 505; and applying the isolation layer 130 at the third metal layer 123 of the second laminate layer 120 before the laying-up and laminating 505, where the isolation layer 130 is structured to form an opening for embedding the bonding metal, e.g., as shown in
Applying 503 the bonding metal may include plating, printing or dispending; and applying the isolation layer 130 may include printing, coating, laminating or dispensing, e.g., as shown in
The method 500 may further include: applying the isolation layer 130 at the third metal layer 123 of the second laminate layer 120 before the laying-up and laminating 505, where the isolation layer 130 is structured to form an opening for embedding the bonding metal; and placing the bonding metal into the opening of the isolation layer 130 on the third metal layer 123, e.g., as shown in
The method 500 may further include: placing the isolation layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120 during the laying-up and laminating 505, where the isolation layer 130 is non-structured, e.g., as shown in
The method 500 may further include: placing the isolation layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120 during the laying-up and laminating, where the isolation layer 130 is structured to form an opening for embedding the bonding metal, e.g., as shown in
Following process steps of the method 500 are optional: drilling holes in the semiconductor power entity 100 extending from the first metal layer 113 to the fourth metal layer 124, where the holes are drilled laterally to the first and second power semiconductors 140, 150; metal plating the holes to form metal plated through holes electrically connecting the first metal layer 113 with the fourth metal layer 124; and structuring the first metal layer 113 and the fourth metal layer 124.
While a particular feature or aspect of the embodiments may have been described with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “include”, “have”, “with”, or other variants thereof are used, such terms are intended to be inclusive in a manner similar to the term “comprise”. Also, the terms “exemplary”, “for example” and “e.g.” are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.
Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the embodiments. The embodiments are intended to cover any adaptations or variations of the specific aspects discussed herein.
Although the elements in the embodiments may be recited in a particular sequence with corresponding labeling, unless the recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the embodiments beyond those described herein. While described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the embodiments. It is therefore to be understood that within the scope of the embodiments and their equivalents, the embodiments may be practiced otherwise than as specifically described herein.
This application is a continuation of International Application No. PCT/EP2022/057489, filed on Mar. 22, 2022, the disclosure of which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP2022/057489 | Mar 2023 | WO |
| Child | 18890986 | US |
