SEMICONDUCTOR STORAGE DEVICE WITH IMPROVED DEGREE OF MEMORY CELL INTEGRATION AND METHOD OF MANUFACTURING THEREOF

Abstract

A semiconductor storage device of the present invention has a configuration in which a plurality of memory cells respectively including a transistor connected to a storage element for accumulating data are used, a bit line and a word line for specifying one of a plurality of memory cells are used. A structure in which a source electrode and a drain electrode hold an active region is formed vertically to a substrate face. The same bit line is connected to the first two-memory cell unit adjacently formed in a predetermined direction. The same word line is formed, which is a gate electrode of the transistors of the second two-memory cell unit which includes one memory cell of the first two-memory cell unit and which is adjacently formed in the predetermined direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a planar layout diagram and sectional schematic view respectively showing the memory cell array of a conventional DRAM;

FIGS. 2A and 2B are a planar layout diagram and sectional schematic view respectively showing the memory cell array of the semiconductor storage device of Embodiment 1;

FIGS. 3A and 3B are a top view and a sectional view respectively for explaining operations of the semiconductor storage device of Embodiment 1;

FIGS. 4A to 4L are sectional schematic views showing a method of manufacturing the semiconductor storage device of Embodiment 1; and

FIGS. 5A and 5B are a planar layout diagram and sectional schematic view respectively showing the memory cell array of the semiconductor storage device of Embodiment 2.

Claims

1. A semiconductor storage device comprising a plurality of memory cells respectively including a transistor connected to a storage element for accumulating data, and a bit line and a word line for specifying one of said plurality of memory cells, wherein in a case of said transistor, a structure in which a source electrode and a drain electrode hold an active region is formed vertically to a substrate face,same said bit line is connected to a first two-memory cell unit adjacently formed in a predetermined direction, andsame said word line is formed, which is a gate electrode of said transistors of a second two-memory cell unit which includes one memory cell of said first two-memory cell unit and which is adjacently formed in said predetermined direction.

2. The semiconductor storage device according to claim 1, wherein each of planar shapes of said plurality of memory cells is a parallelogram.

3. The semiconductor storage device according to claim 2, wherein a plane direction of said substrate face is (110) surface according to Miller indices, and a pattern lateral of each region of said plurality memory cells respectively is a plane direction equivalent to (111) surface.

4. A method of manufacturing semiconductor storage device comprising the steps of: forming a first conductive impurity diffusion region, having a different conductivity from a substrate, at a predetermined depth from a surface of said substrate, and forming a second impurity diffusion region which is separated from a top end of said first impurity diffusion region on said surface of said substrate by a predetermined distance and which has the same conductivity as that of said first impurity diffusion region;forming a first opening passing through said first and second impurity diffusion regions and a region between these impurity regions from said surface of said substrate;embedding a first insulating film up to a height of a top end of said first impurity diffusion region in said first opening and separating said first impurity diffusion region;forming a second insulating film on a side wall of said first opening in which said first insulating film is embedded partway;embedding a conductive film up to a height of a bottom end of said second impurity diffusion region in said first opening on which said second insulating film is formed on said side wall to form a gate electrode;embedding a third insulating film up to said surface of said substrate on said first opening in which said gate electrode is formed to separate said second impurity diffusion region;forming two second openings which reach said first impurity diffusion region and which are set at symmetric positions by using said gate electrode as a central axis and in which a side wall is covered with an insulating film;forming two third openings which reach said second impurity diffusion region and which are set at symmetric positions by using said gate electrode as a central axis and which are set between said second opening and said gate electrode respectively; andembedding a conductive film in said second and third opening to form a contact plug.