Patent Application
20240429308
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or active region) extending from the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. The advantages of a FinFET may include reducing the short channel effect and providing a higher current flow.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Embodiments of forming respective metal gate structures for various transistors (e.g., FinFET and GAA FET) with different threshold voltages in a semiconductor structure are provided. The method for forming the semiconductor structure includes doping dopants (e.g., oxygen, fluorine and/or nitrogen) into a work function layer to shift the work functions of the work function layer. The threshold voltages of the FET can be adjusted without varying the material and/or thickness of the work function layer. As a result, the transistors having different threshold voltages may be achieved on a single semiconductor substrate without degrading the gate-filling capability of the metal gate electrode layer.
The semiconductor structure 100 includes a substrate 102, and a fin structure 104 over the substrate 102, in accordance with some embodiments. The fin structure 104 is the active region of the semiconductor structure 100, in accordance with some embodiments. Although one fin structure 104 is illustrated in
For a better understanding of the semiconductor structure, an X-Y-Z coordinate reference is provided in
Fin structures described below may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine lithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
The fin structure 104 extends in the X direction, in accordance with some embodiments. That is, the fin structure 104 has a longitudinal axis parallel to the X direction, in accordance with some embodiments. The X direction may also be referred to as the channel-extending direction. The current of the resulting semiconductor devices (i.e., FinFETs) flows in the X direction through the channel. The fin structure 104 is defined as several channel regions and source/drain regions, where the channel regions and the source/drain regions are alternately arranged, in accordance with some embodiments. In this disclosure, a source/drain refers to a source and/or a drain. The number of channel regions and source/drain regions may be dependent on the demands on the design of the circuit and/or performance considerations of the semiconductor device.
An isolation structure 106 is formed over the substrate 102 and surrounds the lower portion 104L of the fin structure 104, in accordance with some embodiments. Gate structures 108 are formed with longitudinal axes parallel to the Y direction and extending across or surrounding the channel regions of the fin structure 104 and the isolation structure 106, in accordance with some embodiments. The source/drain regions of the fin structure 104 are exposed from the gate structures 108, in accordance with some embodiments. The Y direction may also be referred to as a gate-extending direction.
A semiconductor structure 100 is provided, as shown in
In some embodiments, the active region 104 extends in the X direction. The active region 104 has a longitudinal axis parallel to the X direction, in accordance with some embodiments. That is, the dimension (length) of the active region 104 in the X direction is greater than the dimension (width) of the active region 104 in the Y direction. In some embodiments, the active region 104 is the fin structure 104 as shown in
The substrate 102 may be a portion of a semiconductor wafer, a semiconductor chip (or die), and the like. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. Furthermore, the substrate 102 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, or have other suitable enhancement features.
The formation of the active region 104 includes patterning the substrate 102 thereby forming trenches, in accordance with some embodiments. The portion of the substrate 102 that protrudes from between the trenches serves as the active region 104, in accordance with some embodiments. The patterning process may include photolithography and etching processes.
The isolation structure 106 is formed over the substrate 102 to partially fill the trenches, as shown in
In some embodiments, the formation of the isolation structure 106 includes depositing a dielectric material for the isolation structure 106 to overfill the trenches. In some embodiments, the dielectric material is deposited using chemical vapor deposition (CVD) (such as such as flowable CVD (FCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or high aspect ratio process (HARP)), atomic layer deposition (ALD), another suitable technique, or a combination thereof.
The dielectric material formed over the top of the active region 104 is planarized, for example, using CMP, an etching back process, or a combination thereof, in accordance with some embodiments. The dielectric material is further recessed using an etching process to expose the sidewalls of the active region 104, in accordance with some embodiments. A remainder of the dielectric material serves as the isolation structure 106, in accordance with some embodiments.
The dummy gate structure 108 extends across the channel region of the active region 104 and the isolation structure 106, as shown in
In some embodiments, the dummy gate structure 108 extends in the Y direction. The dummy gate structure 108 has longitudinal axis parallel to the Y direction, in accordance with some embodiments. That is, the dimension (length) of the dummy gate structure 108 in the Y direction are greater than the dimension (width) of the dummy gate structure 108 in the X direction.
The dummy gate structure 108 includes a dummy gate dielectric layer 110 and a dummy gate electrode layer 112 formed on the dummy gate dielectric layer 110, in accordance with some embodiments. In some embodiments, the dummy gate dielectric layer 110 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTIO, HAIO, or a combination thereof. In some embodiments, the dielectric material is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable technique, or a combination thereof.
In some embodiments, the dummy gate electrode layer 112 is made of a semiconductor material such as polysilicon, poly-silicon germanium. In some embodiments, the dummy gate electrode layer 112 is made of a conductive material such as metallic nitrides, metallic silicides, metals, or a combination thereof. In some embodiments, the material for the dummy gate electrode layer 112 is formed using CVD, another suitable technique, or a combination thereof.
In some embodiments, the formation of the dummy gate structure 108 includes depositing a dielectric material for the dummy gate dielectric layer 110 over the semiconductor structure 100, depositing a material for the dummy gate electrode layer 112 over the dielectric material, planarizing the material for the dummy gate electrode layer 112, and patterning the dielectric material and the material for the dummy gate electrode layer 112 into the dummy gate structure 108.
The patterning process includes forming a patterned mask layer (such as a patterned hard mask layer or a patterned photoresist layer) over the material for the dummy gate electrode layer 112 to cover the channel region of the active region 104, in accordance with some embodiments. The materials for the dummy gate electrode layer 112 and dielectric material, uncovered by the patterned mask layer, are etched away until the source/drain regions of the active region 104 are exposed, in accordance with some embodiments.
The gate spacer layers 116 are formed along opposite sidewalls of the dummy gate structure 108, as shown in
In some embodiments, the gate spacer layers 116 are made of a dielectric material, such as silicon-containing dielectric material, such as silicon oxide (SiO2), silicon nitride (SIN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or oxygen-doped silicon carbonitride (Si(O)CN).
In some embodiments, the formation of the gate spacer layers 116 includes conformally depositing a dielectric material for the gate spacer layers 116 over the semiconductor structure 100 followed by an anisotropic etching process such as dry etching. The portion of the dielectric material that remains on the sidewalls of the dummy gate structure 108 serves as the gate spacer layers 116, in accordance with some embodiments.
Source/drain features 118 are formed over the source/drain regions of the active region 104, as shown in
Afterward, the source/drain features 118 are grown on the exposed surfaces of the active region 104 in the source/drain recesses using an epitaxial growth process, in accordance with some embodiments. The epitaxial growth process may be molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or another suitable technique. In some embodiments, the source/drain features 118 are made of any suitable semiconductor material for an n-type semiconductor device and a p-type semiconductor device, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.
In some embodiments, the source/drain features 118 are in-situ doped during the epitaxial growth process. For example, the n-type source/drain features for n-type semiconductor devices are doped with the n-type dopant during the epitaxial growth process. For example, the n-type dopant may be phosphorous (P) or arsenic (As). For example, the n-type source/drain features may be the epitaxially grown silicon phosphorous (SiP), silicon carbon (SiC), silicon phosphorous carbon (SiPC), silicon phosphorous arsenic (SiPAs), silicon arsenic (SiAs), silicon (Si) or a combination thereof doped with phosphorous or arsenic. In some embodiments, the concentrations of the dopant (e.g., P) in the source/drain features 118 are in a range from about 2×1019 cm−3 to about 3×1021 cm−3.
For example, the p-type source/drain features for p-type semiconductor devices are doped with the p-type dopant during the epitaxial growth process. For example, the p-type dopant may be boron (B) or BF2. For example, the p-type source/drain features may be the epitaxially grown silicon germanium (SiGe), silicon germanium carbon (SiGeC), germanium (Ge), silicon (Si) or a combination thereof doped with boron (B). In some embodiments, the concentrations of the dopant (e.g., B) in the source/drain features 118 are in a range from about 1×1019 cm−3 to about 6×1020 cm−3.
A contact etching stop layer 120 is formed over the semiconductor structure 100, as shown in
In some embodiments, the contact etching stop layer 120 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxynitride (SiOC), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, a dielectric material for the contact etching stop layer 120 is globally and conformally deposited over the semiconductor structure 100 using CVD (such as LPCVD, PECVD, HDP-CVD, HARP, and FCVD), ALD, another suitable method, or a combination thereof.
A first interlayer dielectric layer 122 is formed over the contact etching stop layer 120, as shown in
In some embodiments, the first interlayer dielectric layer 122 is made of a different material than the contact etching stop layer 120. In some embodiments, the first interlayer dielectric layer 122 and the contact etching stop layer 120 have a great difference in etching selectivity. In some embodiments, the first interlayer dielectric layer 122 is made of an oxide (such as silicon oxide) and the contact etching stop layer 120 is made of a nitrogen-containing dielectric (such as silicon nitride or silicon oxynitride).
Afterward, the dielectric materials for the contact etching stop layer 120 and the first interlayer dielectric layer 122 above the upper surfaces of the dummy gate electrode layer 112 are removed using such as CMP until the upper surface of the dummy gate structure 108 is exposed, in accordance with some embodiments. In some embodiments, the upper surface of the first interlayer dielectric layer 122 is substantially coplanar with the upper surface of the dummy gate electrode layer 112.
The dummy gate structure 108 is removed using an etching process to form a gate trench T, as shown in
In some embodiments, the etching process includes one or more etching processes. For example, when the dummy gate electrode layer 112 is made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 112. For example, the dummy gate dielectric layer 110 may be thereafter removed using plasma dry etching, dry chemical etching, or wet etching.
An interfacial layer 124 is formed on the exposed surface of the active region 104, as shown in
A gate dielectric layer 126 is formed conformally along the interfacial layer 124 to surround the active region 104 and partially fills the gate trench T, as shown in
The gate dielectric layer 126 may be high-k dielectric layer. In some embodiments, the high-k dielectric layer is a dielectric material with high dielectric constant (k value), for example, greater than 3.9. In some embodiments, the gate dielectric layer 126 is made of hafnium-containing dielectric material, such as hafnium oxide (HfO2), HfZrO, HfSiO4, HfZrO, HfLaO, HfSiO, HfTaO, HfTiO. In alternative embodiments, the gate dielectric layer 126 is made of TiO2, Ta2O3, ZrO2, ZrSiO2, LaO, Al2O3, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, LaSiO, AlSiO, (Ba,Sr)TiO3 (BST), Si3N4, oxynitrides (SiON), a combination thereof, or another suitable material. The high-k dielectric layer may be deposited using ALD, PVD, CVD, or another suitable technique.
A capping layer (not shown) is conformally formed over the semiconductor structure 100, in accordance with some embodiments. The capping layer may be made of titanium nitride, silicon, titanium nitride doped with silicon (TSN), a multi-layer thereof, or a combination thereof. For example, a TSN capping layer is formed over the gate dielectric layer 126, and then an in-situ post metallization anneal (i-PMA) process is performed in accordance with some embodiments. In some embodiments, the i-PMA process is a spike anneal, which is performed at a temperature of about 850° C. to about 950° C., and in an ambient containing N2. A silicon capping layer is formed over the TSN capping layer, and then a post cap anneal (PCA) process is performed in accordance with some embodiments. In some embodiments, the PCA process is a spike anneal, which is performed in an ambient containing N2 and at a temperature in a range from about 900° C. to about 950° C.
The TSN capping layer and the silicon capping layer are removed using one or more etching processes until the gate dielectric layer 126 is exposed, in accordance with some embodiments. The etching processes may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. Afterward, a post deposition anneal (PDA) process is performed on the gate dielectric layer 126, in accordance with some embodiments. In some embodiments, the PDA process is a spike anneal, which is performed at a temperature of about 850° C. to about 950° C., and in an ambient containing NH3.
The capping layers and these anneal processes may be helpful in improving the crystallization of the gate dielectric layer 126 and reducing the defects in the gate dielectric layer 126, which may improve the quality of the gate dielectric layer 126, e.g., thereby enhancing the performance of semiconductor devices.
A metal gate electrode layer 128 is formed over the gate dielectric layer 126 to overfill a remainder of the gate trench T, as shown in
In some embodiments, the metal gate electrode layer 128 is made of more than one conductive material, such as a metal, metal alloy, conductive metal oxide or metal nitride, another suitable conductive material, or a combination thereof. As discussed in detail below, the metal gate electrode layer 128 may be a multi-layer structure with various combinations of a work function layer with a selected work function to enhance the device performance for n-type transistors and p-type transistors, a protection layer, a gate metal fill layer, or another suitable layer.
A planarization process such as CMP is performed on the semiconductor structure 100 to remove the final gate stack 130 formed over the upper surface of the first interlayer dielectric layer 122, in accordance with some embodiments. After the planarization process, the upper surface of the metal gate electrode layer 128 is substantially coplanar with the upper surface of the first interlayer dielectric layer 122, in accordance with some embodiments.
In some embodiments, the final gate stack 130 extends in the Y direction. The final gate stack 130 has a longitudinal axis parallel to the Y direction, in accordance with some embodiments. That is, the dimension (length) of the final gate stack 130 in the Y direction is greater than the dimension (width) of the final gate stack 130 in the X direction, in accordance with some embodiments.
The final gate stack 130 surrounds the channel region of the active region 104 and are interposed between the source/drain features 118, in accordance with some embodiments. The final gate stack 130 combines with the source/drain features 118 and the channel region of the active region 104 to form a FinFET device, such as an n-channel FinFET device or a p-channel FinFET device, in accordance with some embodiments. The final gate stack 130 may engage the channel region of the active region 104, so that current can flow between the source/drain features 118 during operation.
A second interlayer dielectric layer 132 is formed over the semiconductor structure 100, as shown in
Contact plugs 134 are formed in or through the second interlayer dielectric layer 132, the first interlayer dielectric layer 122 and the contact etching stop layer 120 and land on the source/drain features 118, as shown in
In some embodiments, the formation of the contact plugs 134 includes patterning the second interlayer dielectric layer 132, the first interlayer dielectric layer 122 and the contact etching stop layer 120 to form contact openings (where the contact plugs 134 are to be formed) using photolithography and etching processes until the source/drain features 118 are exposed. Silicide layers (not shown) are formed on the exposed surfaces of the source/drain features 118. In some embodiments, the silicide layers are made of WSi, NiSi, TiSi or CoSi.
Afterward, one or more conductive materials for the contact plugs 134 are deposited to overfill the contact openings, in accordance with some embodiments. In some embodiments, one or more conductive materials are deposited using CVD, PVD, e-beam evaporation, ALD, electroplating (ECP), electroless deposition (ELD), another suitable method, or a combination thereof to overfill the contact openings. The one or more conductive materials over the upper surface of the second interlayer dielectric layer 132 are planarized using, for example, CMP. After the planarization process, the upper surfaces of the contact plugs 134 and the upper surface of the second interlayer dielectric layer 132 are substantially coplanar, in accordance with some embodiments.
The contact plugs 134 may have a multilayer structure including, for example, liner layers, glue layers, barrier layers, seed layers, metal bulk layers, another suitable layer, or a combination thereof. For example, a barrier/adhesive layer (not shown) may optionally be deposited along the sidewalls and the bottom surfaces of the contact openings. A metal bulk layer is then deposited on the barrier/adhesive layer (if formed) to fill the remainder of the contact openings 150.
The barrier/adhesive layer is used to prevent the metal in the subsequently formed metal material from diffusing into the dielectric material, and to improve adhesion between the subsequently formed metal bulk material and the dielectric materials. The barrier/adhesive layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), another suitable material, or a combination thereof. If the subsequently formed metal material does not easily diffuse into the dielectric material, the barrier layer may be omitted.
In some embodiments, the metal bulk layer is formed using a selective deposition technique such as cyclic CVD process or ELD process, and it is not necessary to form an adhesive layer in the contact openings before depositing the metal bulk material. In some embodiments, the metal bulk layer is made of one or more conductive materials with low resistance and good gap-fill ability, for example, cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), another suitable metal material, or a combination thereof.
A via 136 is formed in and/or through the second interlayer dielectric layer 132 and land on the metal gate electrode layer 128 of the final gate stack 130, as shown in
In some embodiments, the formation of the via 136 includes patterning the second interlayer dielectric layer 132 to form a via opening (where the via 136 are to be formed) using photolithography and etching processes. In some embodiments, the final gate stack 130 is exposed from the via opening for the via 136.
Afterward, one or more conductive materials are deposited using CVD, PVD, e-beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof to overfill the via openings, in accordance with some embodiments. The one or more conductive materials over the upper surface of the second interlayer dielectric layer 132 are planarized using, for example, CMP. After the planarization process, the upper surface of the via 136, the upper surfaces of the contact plugs 134, and the upper surface of the second interlayer dielectric layer 132 are substantially coplanar, in accordance with some embodiments.
The via 136 may have a multilayer structure. For example, a barrier/adhesive layer (not shown) may optionally be deposited along the sidewalls and the bottom surfaces of the via opening. The barrier layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), another suitable material, or a combination thereof. A metal bulk layer is then deposited on the barrier/adhesive layer (if formed) to fill the remainder of the via opening. In some embodiments, the metal bulk layers are made of one or more conductive materials, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), molybdenum (Mo), another suitable metal material, or a combination thereof.
It is understood that the semiconductor structure 100 may undergo further CMOS processes to form various features over the semiconductor structure 100, such as a multilayer interconnect structure (e.g., metal lines, inter metal dielectric layers, passivation layers, etc.)
Although
The threshold voltage may depend on the semiconductor material of the FET channel region and/or the effective work function (EWF) value of a gate stack of the FET. For example, for an n-type FET, reducing the difference between the EWF value(s) of the NFET gate stack and the conduction band energy of the material (e.g., 4.1 eV for Si or 3.8 eV for SiGe) of the NFET channel region can reduce the NFET threshold voltage. For a p-type FET (PFET), reducing the difference between the EWF value(s) of the PFET gate stack and the valence band energy of the material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) of the PFET channel region can reduce the PFET threshold voltage. The EWF values of the FET gate structures may depend on the thickness and/or material composition of each of the layers of the gate stack. Accordingly, FETs can be manufactured with different threshold voltages by adjusting the thickness and/or material composition of the FET gate stacks.
As used herein, the term “n-type work function metal (nWFM)” defines a metal or a metal-containing material with a work function that is closer to a conduction band energy than a valence band energy of semiconductor material of a FET channel region. In some embodiments, the term “n-type work function metal (nWFM)” defines a metal or a metal-containing material with a work function of less than 4.5 eV.
As used herein, the term “p-type work function metal (pWFM)” defines a metal or a metal-containing material with a work function that is closer to a valence band energy than a conduction band energy of a semiconductor material of a FET channel region. In some embodiments, the term “p-type work function metal (pWFM)” defines a metal or a metal-containing material with a work function that is equal to or greater than 4.5 eV.
The substrate 102 includes device regions 50A, 50B, 50C and 50D, as shown in
In some embodiments, a p-type transistor P1 is predetermined to be formed on the active region 104C in the device region 50C and has a threshold voltage Vp1 (e.g., low voltage or ultra-low voltage). In some embodiments, a p-type transistor P2 is predetermined to be formed on the active region 104D in the device region 50D and has a threshold voltage Vp2 (e.g., standard voltage). Here, Vp2<Vp1<0.
In some embodiments, the n-type transistors N1 and N2 are n-channel FinFETs, and the p-type transistors P1 and P2 are p-channel FinFETs. The source/drain features 118 formed in the device regions 50A and 50B are n-type source/drain features and denoted as source/drain features 118N, and the source/drain features 118 formed in the device regions 50C and 50D are p-type source/drain features and denoted as source/drain features 118P, in accordance with some embodiments.
After the PDA process described above in
In some embodiments, the work function layer 138 is n-type work function metal, e.g., Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaAl, TaC, TaCN, TaSIN, TaAlC, Mn, Zr, another suitable n-type work function metal, or a combination thereof. The material of the work function layer 138 is selected to assist in providing a desired work function for the n-type transistor N2. The work function layer 138 is deposited using ALD, CVD, PVD, another suitable technique, or a combination thereof. In some embodiments, the work function layer 138 has a thickness T3 in a range from about 10.0 Å to about 50.0 Å.
A patterning process is performed on the work function layer 138, as shown in
In alternative embodiments, the mask layer is a patterned hard mask layer which is made of a material having a different etching selectivity from the work function layer 138. The mask layer may be made of metal oxide (e.g., AlO, TiO, LaO, HfO, etc.), a nitrogen-free anti-reflection layer (NFARL), carbon-doped silicon dioxide (e.g., SiO2:C), titanium nitride (TiN), boron nitride (BN), a multilayer thereof, another suitable material, or a combination thereof. For example, a material for the mask layer is deposited over the work function layer 138. A patterned photoresist layer may be formed over the material for the mask layer using the photolithography process described above. The material for the mask layer may be etched using the patterned photoresist layer to form the mask layer.
The patterning process also includes performing an etching process using the mask layer to remove the portion of the work function layer 138 at the device regions 50C and 50D until the gate dielectric layer 126 is exposed, in accordance with some embodiments. The remaining portions of the work function layer 138 at the device regions 50A and 50B are denoted as work function layer 138A and 138B. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. In some embodiments, the mask layer is removed in the etching process or by an additional etching process or ashing process.
A work function layer 140 is formed over the semiconductor structure 100 at the device regions 50A, 50B, 50C and 50D, as shown in
In some embodiments, the work function layer 140 is p-type work function metal, e.g., TIN, WN, WCN, TaN, Ru, Co, W, another suitable p-type work function metal, or a combination thereof. The material of the work function layer 140 is selected to assist in providing a desired work function for the p-type transistor P2. The work function layer 140 is deposited using ALD, CVD, PVD, another suitable technique, or a combination thereof. In some embodiments, the work function layer 140 has a thickness T4 in a range from about 10.0 Å to about 50.0 Å.
A patterning process is performed on the work function layer 140, as shown in
The patterning process also includes performing an etching process using the mask layer to remove the portion of the work function layer 140 at the device regions 50A and 50B until the work function layers 138A and 138B are exposed, in accordance with some embodiments. The remaining portions of the work function layer 140 at the device regions 50C and 50D are denoted as work function layers 140C and 140D. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. In some embodiments, the mask layer is removed in the etching process or by an additional etching process or ashing process. In some embodiments, a terminus the work function layer 138B is interfaced with a terminus the work function layer 140C, as shown in
A protection layer 142 is formed over the semiconductor structure 100 at the device regions 50A, 50B, 50C and 50D, as shown in
In some embodiments, the protection layer 142 is made of semiconductor material such as silicon. In alternative embodiments, the protection layer 142 is made of metal material such as titanium, metal nitride such as TiN or TSN (titanium nitride doped with silicon), or a combination thereof. The protection layer 142 is configured to block impurities and dopants (e.g., oxygen, fluorine, nitrogen, etc.) from diffusing into the work function layers 138 and 140, in accordance with some embodiments. The protection layer 142 is deposited using ALD, CVD, PVD, another suitable technique, or a combination thereof.
In some embodiments, the protection layer 142 has a thickness T5 in a range from about 10.0 Å to about 30.0 Å. In some embodiments, the thickness T5 of the protection layer 142 is less than the thickness T3 of the work function layer 138 and the thickness T4 of the work function layer 140. In some embodiments, the ratio (T5/T3 or T5/T4) of the thickness T4 to the thickness T2 or the thickness T4 to the thickness T3 is in a range from about 0.3 to about 0.9. If the thickness T5 or the ratio (T5/T3) is too small, the protection layer 142 may not sufficiently block the diffusion of the impurities and dopants. If the thickness T5 or the ratio (T5/T3) is too great, the resistance of the resulting gate electrode layer may increase.
A patterning process is performed on the protection layer 142, as shown in
The patterning process also includes performing an etching process using the mask layer to remove the portion of the protection layer 142 at the device regions 50A and 50C until the work function layer 138A and the work function layer 140C are exposed, in accordance with some embodiments. The remaining portions of the protection layer 142 at the device regions 50B and 50D are denoted as protection layers 142B and 142D. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. In some embodiments, the mask layer is removed in the etching process or by an additional etching process or ashing process.
The protection layer 142B extends over and protects the work function layer 138B, and the protection layer 142D extends over and protects the work function layer 140D, in accordance with some embodiments. In some embodiments, the protection layer 142B extends beyond the terminus 138T of the work function layer 138B, as shown in
A gate metal fill layer 144 is formed over the semiconductor structure 100 at the device regions 50A, 50B, 50C and 50D to overfill the remainder of the gate trench T, as shown in
It should be noted that the work function layer 138A and the work function layer 140C, uncovered by the protection layer 142, may be doped with dopants and/or impurities during some thermal processes (e.g., the deposition process for forming the gate metal fill layer 144). The doped work function layer 138A and the work function layer 140C are respectively denoted as 138A′ and 140C′, as shown in
In some embodiments, the gate metal fill layer 144 is made of metal material with lower resistance, for example, tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and a combination thereof. In some embodiments, the gate metal fill layer 144 is formed using ALD, CVD, PVD, electroplating process, another suitable technique, or a combination thereof. In some embodiments, the gate metal fill layer 144 has a thickness in a range from about 100 Å to about 1000 Å.
In some embodiments, the work function layer 138A′ and the gate metal fill layer 144 combine to form the metal gate electrode layer of the n-type transistor N1. In some embodiments, the work function layer 138B, the protection layer 142B and the gate metal fill layer 144 combine to form the metal gate electrode layer of the n-type transistor N2. In some embodiments, the work function layer 140C′ and the gate metal fill layer 144 combine to form the metal gate electrode layer of the p-type transistor P1. In some embodiments, the work function layer 140D, the protection layer 142D, and the gate metal fill layer 144 combine to form the metal gate electrode layer of the p-type transistor P2.
During the deposition process for forming the gate metal fill layer 144, the heat and/or ion bombardment from the deposition process drive impurities and/or dopants (e.g., oxygen, fluorine, nitrogen, etc.) to diffuse through the gate metal fill layer 144 and become doped or incorporated into the work function layer 138A and the work function layer 140C, as shown in
Meanwhile, the protection layers 142B and 142D block impurities and/or dopants from diffusing into the work function layers 138B and 140D during the deposition process for forming the gate metal fill layer 144, as shown in
The n-type work function layer 138A is doped to form a doped n-type work function layer 138A′, as shown in
The work function of the doped n-type work function layers 138A′ may increase and is higher than the work function of the non-doped n-type work function layers 138B, in accordance with some embodiments. That is, the difference between the EWF value of the gate stack and the conduction band energy of the channel material of the n-type transistor N1 is higher than the difference between the EWF value of the gate stack and the conduction band energy of the channel material of the n-type transistor N2, in accordance with some embodiments. As a result, the threshold voltage Vn1 of the n-type transistor N1 is higher than the threshold voltage Vn2 of the n-type transistor N2 (i.e., 0<Vn2<Vn1).
The p-type work function layer 140C is doped to form a doped p-type work function layer 140C′, as shown in
The work function of the doped p-type work function layers 140C′ may increase and is higher than the work function of the non-doped p-type work function layers 140D, in accordance with some embodiments. That is, the difference between the EWF value of the gate stack and the valence band energy of the channel material of the p-type transistor P1 is lower than the difference between the EWF value of the gate stack and the valence band energy of the channel material of the p-type transistor P2, in accordance with some embodiments. As a result, the absolute value of the threshold voltage Vp1 of the p-type transistor P1 is lower than the absolute value of the threshold voltage Vp2 of the p-type transistor P2 (i.e., Vp2<Vp1<0).
As the scale of semiconductor devices continues to shrink, one of the design challenges of semiconductor devices is to tune the threshold voltages of the semiconductor devices without degrading the gate-filling capability of the metal gate electrode layer. In accordance with some embodiments of the present disclosure, by doping or incorporating the dopants (e.g., oxygen, fluorine and/or nitrogen) into the work function layers 138 and/or 140 to shift the work functions of the work function layers 138 and/or 140, the threshold voltages of the NFETs and PFETs can be adjusted without varying the material and/or thickness of the work function layers 138 and/or 140. As a result, the transistors having different threshold voltages may be achieved on a single semiconductor substrate without degrading the gate-filling capability of the metal gate electrode layer. Therefore, the performance and the manufacturing yield of the resulting semiconductor device may improve.
In addition, one approach to manufacturing the p-type device with a low or ultra-low threshold is that the active region for the p-type device uses a different material than that of the active region for the n-type device, for example, silicon for an n-type device and silicon germanium for a p-type device. However, the material difference between the n-type and p-type active regions may lead to the difference in the etching amount between the n-type active region and the p-type active region in the etching process for forming the active regions, thereby resulting in the difference in the profile between the n-type and p-type active regions. Such profile differences will increase the difficulty of subsequent manufacturing processes. As a result, in accordance with the embodiments of the present disclosure, doping or incorporating the dopants (oxygen, fluorine and/or nitrogen) into the work function layers to further lower the threshold voltage of the p-type transistor P1 may be beneficial to realize the use of silicon as the active region 104C for the p-type transistor P1 instead of silicon germanium as the active region. Therefore, the difficulty of manufacturing the semiconductor device and the manufacturing yield of the resulting semiconductor device may improve.
Similarly, during the deposition process for forming the contact plugs 134 and the deposition process for forming the vias 136, the heat and/or ion bombardment from the deposition processes drive impurities and/or dopants (e.g., oxygen, fluorine, nitrogen, etc.) from the ambient and/or the reactive precursors to diffuse through the gate metal fill layer 144 and are doped or incorporated into the work function layer 138A′ and the work function layer 140C′, as shown in
In some embodiments, the gate metal fill layer 144 of the p-type transistor P1 is surrounded by the work function layer 140C′ and has a dimension D3 in the Y direction. In some embodiments, the dimension D3 is greater than the dimension D2. In some embodiments, the gate metal fill layer 144 of the p-type transistor P2 is surrounded by the protection layer 142D and has a dimension D4 in the Y direction. In some embodiments, the dimension D4 is less than the dimension D3.
The substrate 102 includes device regions 50B and 50C, as shown in
Continuing from
A patterning process is performed on the work function layer 140, as shown in
The patterning process also includes performing an etching process using the mask layer to remove the portion of the work function layer 140 at the device region 50B until the work function layer 138B is exposed, in accordance with some embodiments. The trench T is opened again, in accordance with some embodiments. The remaining portion of the work function layer 140 at the device region 50C denoted as a work function layer 140C. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. In some embodiments, the mask layer is removed in the etching process or by an additional etching process or ashing process.
A protection layer 142 is formed over the semiconductor structure 100 at the device regions 50B and 50C, as shown in
A gate metal fill layer 144 is formed over the protection layer 142 at the device regions 50B and 50C to overfill the remainder of the gate trench T, as shown in
A planarization process discussed above in
The steps discussed above in
During the deposition process for forming the contact plugs 134 and the deposition process for forming the vias 136, the heat and/or ion bombardment from the deposition processes drive impurities and/or dopants (e.g., oxygen, fluorine, nitrogen, etc.) from the ambient and/or the reactive precursors to diffuse into the work function layer 140C, in accordance with some embodiments. Meanwhile, the protection layer 142B blocks impurities and dopants from diffusing into the work function layers 138B during the deposition process for forming the contact plugs 134 and the deposition process for forming the via 136, in accordance with some embodiments.
The doped p-type work function layers 140C is denoted as 140C′, as shown in
Although the embodiments described above are used in the semiconductor structure with FinFET design, the concept of the embodiments may be also used in a semiconductor device structure with another applicable design, e.g., planar FETs, dual-gate FETs, tri-gate FETs (e.g., nanostructure FETs (such as gate-all-around (GAA) FETs), forksheet FETs, ribbon FETs, multi-bridge channel (MBC) FETs, etc.).
The GAA transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
The semiconductor structure 200 includes a substrate 102 and a fin structure 204 over the substrate 102, as shown in
The fin structure 204 extends in the X direction, in accordance with some embodiments. The fin structure 204 is defined as several channel regions and several source/drain regions, where the channel regions and the source/drain regions are alternately arranged, in accordance with some embodiments. Gate structures 108 are formed with longitudinal axes parallel to the Y direction and extending across or surrounding the channel regions of the fin structure 204, in accordance with some embodiments. The source/drain regions of the fin structure 204 are exposed from the gate structures 108, in accordance with some embodiments.
The semiconductor structure 200 includes a substrate 102, active region 204 and an isolation structure 106 over the substrate 102, and dummy gate structure 108 over the active region 204 and the isolation structure 106, as shown in
In some embodiments, the first semiconductor layers 206 are made of a first semiconductor material and the second semiconductor layers 208 are made of a second semiconductor material. The first semiconductor material for the first semiconductor layers 206 has a different lattice constant than the second semiconductor material for the second semiconductor layers 208, in accordance with some embodiments. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and/or etching selectivity. In some embodiments, the first semiconductor layers 206 are made of SiGe, where the percentage of germanium (Ge) in the SiGe is in a range from about 20 atomic % to about 50 atomic %, and the second semiconductor layers 208 are made of pure or substantially pure silicon. In some embodiments, the first semiconductor layers 206 are Si1-xGex, where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers 208 are Si or Si1-yGey, where y is less than about 0.4, and x>y.
The first semiconductor layers 206 are configured as sacrificial layers and will be removed to form gaps to accommodate gate materials, and the second semiconductor layers 208 will form nanostructures (e.g., nanowires or nanosheets) that laterally extend between source/drain features and serve as the channel layers for the resulting semiconductor devices (such as nanostructure transistors), in accordance with some embodiments.
The formation of the active region 204 further includes patterning the epitaxial stack and underlying substrate 102 using photolithography and etching processes, thereby forming trenches and the active region 204 protruding from between trenches, in accordance with some embodiments. The portion of substrate 102 protruding from between the trenches serves as the lower fin element 204L of the active region 204, in accordance with some embodiments. A remainder of the epitaxial stack (including the first semiconductor layers 206 and the second semiconductor layers 208) serves as the upper fin elements of the active region 204, in accordance with some embodiments. In some embodiments, the active region 204 is the fin structure 204 as shown in
In some embodiments, the thickness of each of the first semiconductor layers 206 is in a range from about 6 nm to about 16 nm. In some embodiments, the thickness of each of the second semiconductor layers 208 is in a range from about 4 nm to about 8 nm. The thickness of the second semiconductor layers 208 may be greater than, equal to, or less than the first semiconductor layers 206, depending on the amount of gate materials to be filled in spaces where the first semiconductor layers 206 are removed. Although two first semiconductor layers 206 and two second semiconductor layers 208 are shown in
An isolation structure 106 is formed to surround the lower fin element 204L of the active region 204, as shown in
After the source/drain recesses are formed, an etching process is performed to laterally recess, from the source/drain recesses, the first semiconductor layers 206 of the active region 204, thereby forming notches, and then inner spacer layers 210 are formed in the notches, as shown in
The inner spacer layers 210 are formed to abut the recessed side surfaces of the first semiconductor layers 206, in accordance with some embodiments. In some embodiments, the inner spacer layers 210 are located between adjacent second semiconductor layers 208 and between the lowermost second semiconductor layer 208 and the lower fin element 204L. In some embodiments, the inner spacer layers 210 extend directly below the gate spacer layers 116, in accordance with some embodiments.
The inner spacer layers 210 may avoid the source/drain features and the gate stack from being in direct contact and are configured to reduce the parasitic capacitance between the gate stack and the source/drain features (i.e., Cgs and Cgd), in accordance with some embodiments. In some embodiments, the inner spacer layers 210 are made of dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or oxygen-doped silicon carbonitride (Si(O)CN).
In some embodiments, the inner spacer layers 210 are formed by depositing a dielectric material for the inner spacer layers 210 over the semiconductor structure 200 to fill the notches, and then etching back the dielectric material to remove the dielectric material outside the notches. Portions of the dielectric material left in the notches serve as the inner spacer layers 210, in accordance with some embodiments. In some embodiments, the deposition process includes ALD, CVD (such as PECVD, LPCVD or HARP), another suitable technique, or a combination thereof. In some embodiments, the etching back process includes an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof.
Afterward, source/drain features 118 are grown in the source/drain recesses on the exposed surfaces of the lower fin element 204L, as shown in
One or more etching processes are performed to remove the dummy gate structure 108 to form a gate trench T and remove the first semiconductor layers 206 of the active region 204 to form gaps 212, in accordance with some embodiments. In some embodiments, the gate trench T exposes the sidewalls of the gate spacer layers 116 facing the channel region, in accordance with some embodiments. In some embodiments, the gaps 212 expose the sidewalls of the inner spacer layers 210 facing the channel region. The one or more etching processes may include an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof.
After the one or more etching processes, the four main surfaces of the second semiconductor layers 208 are exposed, in accordance with some embodiments. The exposed second semiconductor layers 208 form nanostructures 208, in accordance with some embodiments. The nanostructures 208 are vertically stacked and spaced apart from one other, in accordance with some embodiments. As the term is used herein, “nanostructures” refers to the semiconductor layers with cylindrical shape, bar shaped or sheet shape. The nanostructures 208 function as channel layers of the resulting semiconductor devices (e.g., nanostructure transistors such as GAA transistors), in accordance with some embodiments.
The final gate stack 130 is formed in the gate trench T and gaps 212, thereby wrapping around the nanostructures 208, as shown in
The interfacial layer 124 wraps around the nanostructures 208, in accordance with some embodiments. Semiconductor material from the nanostructures 208 and the lower fin elements 204L is oxidized to form the interfacial layer 124, in accordance with some embodiments. The gate dielectric layer 126 is formed conformally along the interfacial layer 124 to wrap around the nanostructures 208, in accordance with some embodiments. The gate dielectric layer 126 is further conformally formed along the sidewalls of the inner spacer layers 210 facing the channel region, in accordance with some embodiments. The deposition of the capping layer(s) and the anneal processes as described above in
A planarization process such as CMP is performed on the semiconductor structure 200 to remove the final gate stack 130 formed over the upper surface of the first interlayer dielectric layer 122, in accordance with some embodiments.
The final gate stack 130 surrounds the nanostructures 208 and are interposed between the source/drain features 118, in accordance with some embodiments. The final gate stack 130 combines with the source/drain features 118 and the nanostructures 208 to form a nanostructure device, such as an n-channel GAAFET device or a p-channel GAAFET device, in accordance with some embodiments. The final gate stack 130 may engage the channel region of the nanostructures 208, so that current can flow between the source/drain features 118 during operation.
A second interlayer dielectric layer 132 is formed over the semiconductor structure 200, as shown in
Although
The substrate 102 includes device regions 50A, 50B, 50C and 50D, as shown in
In some embodiments, a p-type transistor P1 is formed on the nanostructures 208C in the device region 50C and has a threshold voltage Vp1 (e.g., low voltage or ultra-low voltage). In some embodiments, a p-type transistor P2 is formed on the nanostructures 208D in the device region 50D and has a threshold voltage Vp2 (e.g., standard voltage). Here, Vp2<Vp1<0.
In some embodiments, the n-type transistors N1 and N2 are n-channel GAA FETs, and the p-type transistors P1 and P2 are p-channel GAA FETs. The source/drain features 118 formed in the device regions 50A and 50B are n-type source/drain features and denoted as source/drain features 118N, and the source/drain features 118 formed in the device regions 50C and 50D are p-type source/drain features and denoted as source/drain features 118P, in accordance with some embodiments.
In some embodiments, the metal gate electrode layer of the n-type transistor N1 includes a doped n-type work function layer 138A′ and a gate metal fill layer 144. In some embodiments, the metal gate electrode layer of the n-type transistor N2 includes a non-doped n-type work function layer 138B, a protection layer 142B and the gate metal fill layer 144. In some embodiments, the concentration of the dopant (e.g., oxygen, fluorine and/or nitrogen) in the doped n-type work function layer 138A′ is greater than the concentration of the dopant in the non-doped n-type work function layer 138A.
In some embodiments, the metal gate electrode layer of the p-type transistor P1 includes a doped p-type work function layer 140C′ and the gate metal fill layer 144. In some embodiments, the metal gate electrode layer of the p-type transistor P2 includes a non-doped p-type work function layer 140D, a protection layer 142D, and the gate metal fill layer 144. In some embodiments, the concentration of the dopant (e.g., oxygen, fluorine and/or nitrogen) in the doped p-type work function layer 140C′ is greater than the concentration of the dopant in the non-doped p-type work function layer 140D.
The material and the formation of the work function layer 138 (including 138A′ and 138B), the work function layer 140 (including 140C′ and 140D), the protection layer 142 (including 142B and 142D) and the gate metal fill layer 144 may be the same as or similar to that of the work function layer 138, the work function layer 140, the protection layer 142 and the gate metal fill layer 144 described above in
During the deposition process for forming the gate metal fill layer 144 (and/or forming the contact plugs 134 and/or the deposition process for forming the vias 136), the heat and/or ion bombardment from the deposition process drive impurities and/or dopants (e.g., oxygen, fluorine, nitrogen, etc.) to diffuse through the gate metal fill layer 144 and become doped or incorporated into the work function layer 138A and the work function layer 140C, thereby forming the doped work function layer 138A′ and the doped work function layer 140C′, in accordance with some embodiments. Meanwhile, the protection layers 142B and 142D block the impurities and/or dopants from diffusing into the work function layers 138B and 140D, in accordance with some embodiments.
The work function of the doped n-type work function layers 138A′ is higher than the work function of the non-doped n-type work function layers 138B, in accordance with some embodiments. As a result, the difference between the EWF value of the gate stack and the conduction band energy of the channel material of the n-type transistor N1 is higher than the difference between the EWF value of the gate stack and the conduction band energy of the channel material of the n-type transistor N2, in accordance with some embodiments.
The work function of the doped p-type work function layers 140C′ is higher than the work function of the non-doped p-type work function layers 140D, in accordance with some embodiments. As a result, the difference between the EWF value of the gate stack and the valence band energy of the channel material of the p-type transistor P2 is lower than the difference between the EWF value of the gate stack and the valence band energy of the channel material of the p-type transistor P1, in accordance with some embodiments.
The protection layer 142B overfills the gaps between the nanostructures 208B, and the protection layer 142D overfills the gaps between the nanostructures 208D, in accordance with some embodiments. The gaps between the nanostructures 208B are free of the gate metal fill layer 144, and the gaps between the nanostructures 208D are free of the gate metal fill layer 144, in accordance with some embodiments. In alternative embodiments, the protection layer 142B and 142D may partially fill the gaps between the nanostructures 208B and the gaps between the nanostructures 208D, and the gate metal fill layer 144 may extend in these gaps.
In some embodiments, the protection layer 142B extends beyond the terminus 138T of the work function layer 138B. In some embodiments, the terminus 142T of the protection layer 142B is located closer to the sidewalls of the active region 104C than the terminus 138T of the work function layer 138B.
In some embodiments, the gate metal fill layer 144 of the p-type transistor P1 is surrounded by the work function layer 140C′ and has a dimension D3 in the Y direction. In some embodiments, the dimension D3 is greater than the dimension D2. In some embodiments, the gate metal fill layer 144 of the p-type transistor P2 is surrounded by the protection layer 142D and has a dimension D4 in the Y direction. In some embodiments, the dimension D4 is less than the dimension D3.
The substrate 102 includes device regions 50B and 50C, as shown in
The material and the formation of the non-doped n-type work function layer 138B, the doped p-type work function layer 140C′, the protection layer 142B and the gate metal fill layer 144B may be the same as or similar to that of the work function layer 138B, the work function layer 140C′, the protection layer 142B and the gate metal fill layer 144B described above in
During the deposition process for forming the contact plugs 134 and the deposition process for forming the vias 136, the heat and/or ion bombardment from the deposition processes drive impurities and/or dopants (e.g., oxygen, fluorine, nitrogen, etc.) from the ambient and/or the reactive precursors to diffuse into the work function layer 140C, thereby forming the doped work function layer 140C′, in accordance with some embodiments. Meanwhile, the protection layer 142B blocks impurities and dopants from diffusing into the work function layers 138B, in accordance with some embodiments.
As described above, a semiconductor structure having various devices with different threshold voltages and a method for forming the same are provided. The aspect of the present disclosure is direct to tuning the threshold voltages of the semiconductor devices. The method for forming the semiconductor structure includes doping dopants (e.g., oxygen, fluorine and/or nitrogen) into the n-type work function layer 138 and/or the p-type work function layers 140 to shift the work functions of the work function layers 138 and/or 140. The threshold voltages of the NFETs and PFETs can be adjusted without varying the material and/or thickness of the work function layers 138 and/or 140. As a result, the transistors having different threshold voltages may be achieved on a single semiconductor substrate without degrading the gate-filling capability of the metal gate electrode layer. Therefore, the performance and the manufacturing yield of the resulting semiconductor device may improve.
Embodiments of a method for forming a semiconductor structure are provided. The method may include forming a protection layer over the n-type work function layer while exposing the p-type work function layer, and diffusing a dopant into the p-type work function layer while the first protection layer blocks the dopant from diffusing into the n-type work function layer. Therefore, the threshold voltage of the p-type transistor may be lowered, which may be beneficial to realize the use of silicon as the active region for the p-type transistor.
In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region over a first n-type device region and a first p-type device region of a substrate, respectively. The method includes forming a first n-type work function layer and a first p-type work function layer along the first active region and the second active region, respectively. The method includes forming a semiconductor material along the first n-type work function layer and the first p-type work function layer. The method includes removing a first portion of the semiconductor material along the first p-type work function layer, thereby leaving a second portion of the semiconductor material as a first protection layer over the first n-type work function layer. The method includes diffusing a dopant into the first p-type work function layer to form a doped p-type work function layer while the first protection layer blocks the dopant from diffusing into the first n-type work function layer.
In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region over a substrate. The method includes forming a dummy gate structure across the first active region and the second active region. The method includes removing the dummy gate structure to form a trench. The method includes forming a first work function layer on the first active region in the trench. The method includes forming a second work function layer on the second active region in the trench. The method includes forming a protection layer on the first work function layer in the trench while exposing the second work function layer. The method includes forming a metal fill layer on the protection layer and the second work function layer to overfill the trench. A dopant diffuses through the metal fill layer and into the second work function layer during formation of the metal fill layer.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first n-type transistor and a first p-type transistor adjacent to the first n-type transistor. The first n-type transistor includes a first active region extending in a first direction, a first gate dielectric layer over the first active region, and a first n-type work function layer over the first gate dielectric layer, a first protection layer over the first n-type work function layer, and a first metal fill layer over the first protection layer. The first p-type transistor includes a second active region extending in the first direction, a second gate dielectric layer over the second active region, a first p-type work function layer over the first gate dielectric layer, and a second metal fill layer over the first p-type work function layer. The first p-type work function layer is doped with oxygen, fluorine, or nitrogen.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
