Patent Application
20250183137
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers over a semiconductor substrate, and patterning the various material layers using lithography and etching to form circuit components and elements thereon. Dozens, hundreds, or thousands of integrated circuits are typically manufactured on a single semiconductor wafer. Individual dies on the wafer may be singulated by sawing between the integrated circuits along scribe lines. The individual dies are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.
Both flip-chip and wire bonding are techniques used in semiconductor packaging to establish electrical connections between chips and other components, such as substrates, printed circuit boards, or other chips. While they have different characteristics and advantages, there are situations where both flip-chip and wire bonding might be used within the same semiconductor package, depending on the specific requirements of the application. Further, in various applications, semiconductor dies having both wire bond pads and flip-chip bumps may provide flexibility in how such dies are integrated into different packaging configurations.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, this disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.
Various embodiments disclosed herein may be advantageous by providing wafer-level semiconductor structures having wire-bond pads and flip-chip bumps that have electrically conductive surfaces. In this regard, a polymer layer deposited over the wire-bond pads during formation of the flip-chip bumps may be etched subsequent to the formation of the flip-chip bumps to expose a conductive surface of the wire-bond pads. As such, wafer-level testing may be carried out on both wire-bond pads and flip-chip bumps before singulating wafer-level semiconductor structures into semiconductor dies. Such testing may provide advantages by allowing screening for potential damage that may result due to multiple CMOS fabrication processes and high temperatures used in the formation of the polymer layer. Package-level testing may be performed after the semiconductor dies have been singulated and assembled into semiconductor packages. Semiconductor dies having both wire-bond pads and flip-chip bumps may be used in situations where both flip-chip and wire bonding may be used within the same semiconductor package and may provide flexibility in how such semiconductor dies may be integrated into different packaging configurations.
An embodiment wafer-level semiconductor structure may include a semiconductor substrate having a plurality of semiconductor structures formed thereon. Each wafer-level semiconductor structure may include a plurality of bonding structures electrically connected to the semiconductor structures. The plurality of bonding structures may be formed on a dielectric substrate. Each of the plurality of bonding structures may include a wire-bond pad having a first electrically conducting surface and a flip-chip bump including a second electrically conducting surface. The semiconductor structures may include a flip-chip bond pad and a first passivation layer formed over a surface of the semiconductor structure including a plurality of electrical contact structures. The wire-bond pad may extend through the first passivation layer and may be electrically connected to a first one of the electrical contact structures and the flip-chip bump may be connected to the flip-chip bond pad, which extends through the first passivation layer and is electrically connected to a second one of the electrical contact structures.
According to a further embodiment, a semiconductor structure may include a wire-bond pad including a first electrically conducting surface, a flip-chip bump including a second electrically conducting surface, a first passivation layer, a second passivation layer, and a polymer layer formed over the second passivation layer. The first electrically conducting surface of the wire-bond pad may be located under first openings in the first passivation layer, second openings in the second passivation layer, and third openings in the polymer layer and the flip-chip bump may extend through first openings in the first passivation layer, second openings in the second passivation layer, and third openings in the polymer layer.
According to a further embodiment, a method of forming a semiconductor structure may include forming a plurality of semiconductor circuits on a semiconductor substrate, such that the plurality of semiconductor circuits includes a plurality of electrical contact structures formed at a surface of a dielectric substrate. The method may further include forming, on each of the plurality of electrical contact structures, a wire-bond pad and a flip-chip bond pad. The method may further include forming a polymer layer over the wire-bond pad and the flip-chip bond pad and etching or lithographic patterning the polymer layer to expose a first electrically conducting surface of the wire-bond pad and an intermediate electrically conducting surface of the flip-chip bond pad. The method may further include forming a patterned mask that masks the first electrically conducting surface of the wire-bond pad and exposes the intermediate electrically conducting surface of the flip-chip bond pad. The method may further include depositing a first electrically conducting material over the patterned mask to thereby form a flip-chip bump over the intermediate electrically conducting surface of the flip-chip bond pad such that the flip-chip bump comprising a second electrically conducting surface. The method may further include removing the patterned mask.
Shallow trench isolation structures 106 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 104. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures 106. Field effect transistors 108 may be formed over the top surface of the semiconductor material layer 104. For example, each field effect transistor 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 that includes a surface portion of the semiconductor substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single crystalline semiconductor material. Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. A source-side metal-semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal-semiconductor alloy region 128 may be formed on each drain electrode 112.
The first exemplary structure may include a memory array region 130 in which an array of memory cells may be subsequently formed. The first exemplary structure may further include a peripheral region 132 in which metal wiring for an array of memory devices (e.g., ferroelectric memory devices or other devices to be formed subsequently) is provided. Generally, the field effect transistors 108 in the CMOS circuitry 134 may be electrically connected to an electrode of a respective memory cell (or other device) by a respective set of metal interconnect structures.
Devices (such as field effect transistors 108) in the peripheral region 132 may provide functions that operate the array of memory cells to be subsequently formed. Specifically, devices in the peripheral region may be configured to control the programming operation, the erase operation, and the sensing (read) operation of the array of memory cells. For example, the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer 104 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry 134.
One or more of the field effect transistors 108 in the CMOS circuitry 134 may include a semiconductor channel 114 that contains a portion of the semiconductor material layer 104 in the semiconductor substrate 102. In embodiments in which the semiconductor material layer 104 may include a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 114 of each field effect transistor 108 in the CMOS circuitry 134 may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a plurality of field effect transistors 108 in the CMOS circuitry 134 may include a respective node that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed. For example, a plurality of field effect transistors 108 in the CMOS circuitry 134 may include a respective source electrode 110 or a respective drain electrode 112 that is subsequently electrically connected to a node of a respective memory cell (e.g., ferroelectric memory cell or another device) to be subsequently formed.
In one embodiment, the CMOS circuitry 134 may include a programming control circuit configured to control gate voltages of a set of field effect transistors 108 that may be used for programming a respective memory cell (e.g., a ferroelectric memory cell) and to control gate voltages of transistors (e.g., TFTs) to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a respective ferroelectric dielectric material layer in a selected ferroelectric memory cell into a first polarization state in which electrical polarization in the ferroelectric dielectric material layer points toward a first electrode of the selected ferroelectric memory cell, and to provide a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state in which the electrical polarization in the ferroelectric dielectric material layer points toward a second electrode of the selected ferroelectric memory cell.
In one embodiment, the semiconductor substrate 102 may include a single crystalline silicon substrate, and the field effect transistors 108 may include a respective portion of the single crystalline silicon substrate as a semiconducting channel. As used herein, a “semiconducting” element refers to an element having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105 S/cm upon suitable doping with an electrical dopant.
According to an aspect of the disclosure, the field effect transistors 108 may be subsequently electrically connected to drain electrodes and gate electrodes of access transistors including semiconducting metal oxide plates to be formed above the field effect transistors 108. In one embodiment, a subset of the field effect transistors 108 may be subsequently electrically connected to at least one of the drain electrodes and the gate electrodes. For example, the field effect transistors 108 may include first word line drivers configured to apply a first gate voltage to first word lines through a first subset of lower-level metal interconnect structures to be subsequently formed, and second word line drivers configured to apply a second gate voltage to second word lines through a second subset of the lower-level metal interconnect structures. Further, the field effect transistors 108 may include bit line drivers configured to apply a bit line bias voltage to bit lines to be subsequently formed, and sense amplifiers configured to detect electrical current that flows through the bit lines during a read operation.
Various metal interconnect structures formed within dielectric material layers may be subsequently formed over the semiconductor substrate 102 and the semiconductor devices thereupon (such as field effect transistors 108). In an illustrative example, the dielectric material layers may include, for example, a first dielectric material layer 136 that may be a layer that surrounds the contact structure connected to the source and drains (sometimes referred to as a contact-level dielectric material layer 136), a first interconnect-level dielectric material layer 138, and a second interconnect-level dielectric material layer 140. The metal interconnect structures may include device contact via structures 142 formed in the first dielectric material layer 136 and contacting a respective component of the CMOS circuitry 134, first metal line structures 144 formed in the first interconnect-level dielectric material layer 138, first metal via structures 146 formed in a lower portion of the second interconnect-level dielectric material layer 140, and second metal line structures 148 formed in an upper portion of the second interconnect-level dielectric material layer 140.
Each of the dielectric material layers (136, 138, 140) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metallic liner (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner may include TIN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures 146 and the second metal line structures 148 may be formed as integrated line and via structures by a dual damascene process. The dielectric material layers (136, 138, 140) are herein referred to as lower-level dielectric material layers. The metal interconnect structures (142, 144, 146, 148) formed within in the lower-level dielectric material layers are herein referred to as lower-level metal interconnect structures.
While the disclosure is described using an embodiment in which an array of memory cells may be formed over the second line-and-via-level dielectric material layer 140, embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level.
An array of transistors (e.g., thin film transistors) and an array of memory cells (e.g., ferroelectric memory cells or other types of memory cells) may be subsequently deposited over the dielectric material layers (136, 138, 140) that have formed therein the metal interconnect structures (142, 144, 146, 148). The set of all dielectric material layer that are formed prior to formation of an array of thin film transistors or an array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (136, 138, 140). The set of all metal interconnect structures that is formed within the lower-level dielectric material layers (136, 138, 140) is herein referred to as first metal interconnect structures (142, 144, 146, 148). Generally, first metal interconnect structures (142, 144, 146, 148) formed within at least one lower-level dielectric material layer (136, 138, 140) may be formed over the semiconductor material layer 104 that is located in the semiconductor substrate 102.
According to various embodiments, a planar dielectric material layer having a uniform thickness may be formed over the lower-level dielectric material layers (136, 138, 140). The planar dielectric material layer is herein referred to as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may be in a range from 20 nm to 300 nm, although lesser and greater thicknesses may also be used.
Generally, interconnect-level dielectric layers (such as the lower-level dielectric material layer (136, 138, 140)) containing therein the metal interconnect structures (such as the first metal interconnect structures (142, 144, 146, 148)) may be formed over semiconductor devices. The insulating matrix layer 150 may be formed over the interconnect-level dielectric layers. Other passive devices may be formed in back-end-of-line (BEOL) processes. For example various capacitor structures may be utilized with other BEOL devices.
As shown in
The first passivation layer 212a may be formed over a dielectric substrate 214 that may have formed therein a plurality of electrical contact structures 216 and each of the wire-bond pad 204 and the flip-chip bond pads 210 may be electrically connected to respective ones of the electrical contact structures 216. In this regard, the wire-bond pad 204 may extend through the first passivation layer 212a and may be electrically connected to a first one of the plurality of electrical contact structures 216. Similarly, each flip-chip bump 206 may be connected to a respective flip-chip bond pad 210, which may extend through the first passivation layer 212a, and may be electrically connected to a respective one of the plurality of electrical contact structures 216.
As described above, the dielectric substrate 214 may be a dielectric layer (e.g., an inter-layer dielectric or insulating matrix layer 150 from
The dielectric substrate 214 may include, for example, undoped silicate glass, a doped silicate glass (e.g., deposited by decomposition of tetraethylorthosilicate (TEOS)), organosilicate glass, silicon oxynitride, or silicon carbide nitride. Other dielectric materials are within the contemplated scope of disclosure. The dielectric material of the dielectric substrate 214 may be deposited by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating). The thickness of the dielectric substrate 214 may each be in a range from approximately 15 nm to approximately 60 nm, such as from approximately 20 nm to approximately 40 nm, although smaller and larger thicknesses may also be used.
Formation of the one or more electrical contact structures 216 may be completed by depositing a mask layer (not shown) over the dielectric substrate 214 and performing various photolithographic steps to etch a via in the dielectric substrate 214. Deposition of the at least one conductive material, which may be a combination of a metallic liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material may be performed by any of a variety of deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD)) or a self-planarizing deposition process (such as spin coating). Other conformal deposition processes may include plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a high density plasma CVD (HDPCVD) process, a metalorganic CVD (MOCVD) process, a sputtering process, laser ablation, etc.
According to various embodiments, each of the semiconductor structures 200b (as exemplified by the portion 200c of the semiconductor structure 200b of
Similarly, the first electrically conducting surface 208a of the wire-bond pad 204 may be located under a first opening in the polymer layer 218 and the flip-chip bump 206 may extend through a second opening in the polymer layer 218. As such, the first electrically conducting surface 208a of the wire-bond pad 204 may be recessed relative to a top surface 220 of the polymer layer 218, and the second electrically conducting surface 208b of the flip-chip bumps 206 may extend beyond the top surface 220 of the polymer layer 218, as shown in
According to various embodiments, the wire-bond pad 204, flip-chip bond pads 210, and the flip-chip bumps 206 may be formed of an electrically conductive material such as copper or aluminum. In other embodiments, other electrically conducting materials such as W, Co, Ru, Mo, Ta, Ti, alloys thereof, may be used. Further, as with the electrical contact structures 216, electrically conducting structures such as the wire-bond pad 204, flip-chip bond pads 210, and the flip-chip bumps 206 may further include a liner layer For example, as shown in
The first passivation layer 212a may be formed to protect the electrical contact structures 216. The first passivation layer 212a may include a dielectric material such as silicon dioxide, silicon nitride, an organic polymer material, etc. According to various embodiments, the first passivation layer 212a may be deposited using a technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin-coating, depending on the material being used and the desired properties of the first passivation layer 212a.
In this regard, after exposing the blanket layer of the photoresist to patterned radiation generated by a photomask, a developer may be applied to the exposed photoresist to remove portions of the blanket layer of the photoresist to thereby generate the patterned mask 302. As shown in
The hard mask 310 may be formed by depositing a layer of the hard mask material (not shown) over the intermediate structure 300d followed by patterning the hard mask material. The layer of the hard mask material may be deposited using various techniques such as CVD, PVD, etc. A patterned photoresist (not shown) may then be formed over the layer of the hard mask material using lithographic techniques. The patterned photoresist may then be used to etch the hard mask material to thereby form the hard mask 310. As shown in
After etching the conductive material 308 to form the wire-bond pad 204 and the flip-chip bond pads 210, the hard mask 310 may then be removed by performing a selective etching process. In various embodiments, a wet or dry etching process may be performed. With a wet etching process, for example, hydrofluoric acid (HF) may be used to etch silicon dioxide hard masks 310, and phosphoric acid (H3PO4) or hot potassium hydroxide (KOH) solutions may be used to etch Si3N4 hard masks 310. With a dry etching process, for example, a plasma containing reactive gases may be used to chemically react with the hard mask 310, causing the hard mask 310 to be removed by sputtering.
As shown in
The prebake process may be conducted at a relatively low temperature (e.g., 100-150° C.) for a short time (e.g., 15-30 minutes) to remove some of a solvent and moisture. The imidization process may be performed as the primary curing process and may be conducted at higher temperatures (e.g., 250-350° C.) for an extended period (e.g., 1-2 hours or more). During this stage, polyamic acid may undergo imidization, forming the polyimide structure. The post-cure process may be performed at a slightly higher temperature (e.g., 350-400° C.) for a shorter time to enhance the film's properties and remove any remaining volatiles.
Annealing is a heat treatment process that may follow curing and may be used to optimize the properties of the polyimide film. The specific annealing temperature and time depend on the desired properties, such as mechanical stability, stress relief, and electrical characteristics. Annealing temperatures for polyimide films typically range from 250° C. to 400° C. The duration of annealing can vary from 30 minutes to several hours, depending on the material and desired results. Longer annealing times may be used for stress relief and improved mechanical properties. The annealing process may involve multiple steps, with the temperature gradually ramping up and down to minimize thermal stress and promote uniform properties across the film.
In an alternative embodiment, the polymer layer 218 may be deposited, as shown in
Various etching processes may be used to etch the polymer layer 218. For example, when polyimide is used as the polymer layer 218, a dry etch or a wet etch process may be performed. An example dry etch process may include plasma etching in which a plasma containing reactive gases (e.g., oxygen, fluorine, or CF4) may be used to chemically react with and remove the polyimide material. The specific gas and conditions are chosen based on the polyimide formulation. Wet etching may involve introducing a chemical solution that selectively dissolves the polyimide. Common wet etchants for polyimide include N-methyl-2-pyrrolidone (NMP) or various formulations of organic solvents.
Once the flip-chip bumps 206 have been formed over the under-bump metallurgy layer 222 using the patterned photoresist 302 as a template, the patterned photoresist 302 may then be removed using a suitable removal process. The resulting intermediate structure 300n is shown in
In this regard, portions of the under-bump metallurgy layer 222 may be removed, for example, in a dry etching process in which reactants may be directed towards the under-bump metallurgy layer 222, using the flip-chip bumps 206 as masks. Alternatively, etchants may be sprayed or otherwise put into contact with the under-bump metallurgy layer 222 to remove the exposed portions of the under-bump metallurgy layer 222. After the exposed portion of the under-bump metallurgy layer 222 has been removed (e.g., etched away), the resulting semiconductor structure (200b, 200c) is shown in
In operation 410, the method 400 may include forming a patterned mask 302 that masks the first electrically conducting surface 208a of the wire-bond pad 204 and exposes the intermediate electrically conducting surface 208c of the flip-chip bond pad 210. In operation 412, the method 400 may include depositing a first electrically conducting material 309 over the patterned mask 302 to thereby form a flip-chip bump 206 over the intermediate electrically conducting surface 208c of the flip-chip bond pad 210 such that the flip-chip bump 206 includes a second electrically conducting surface 208b. In operation 414, the method 400 may include removing the patterned mask 302.
The method 400 may further include forming a first passivation layer 212a over the plurality of electrical contact structures 216 and etching the first passivation layer 212a to expose a first one of the plurality of electrical contact structures 216 and a second one of the plurality of electrical contact structures 216. The method 400 may further include depositing a second electrically conducting material 308 over the first passivation layer 212a, the first one of the plurality of electrical contact structures 216, and the second one of the plurality of electrical contact structures 216. The method 400 may further include etching the second electrically conducting material 308 to form the wire-bond pad 204 and the flip-chip bond pad 210.
According to various embodiments, the method 400 may further include forming a second passivation layer 212b over the wire-bond pad 204 and the flip-chip bond pad 210 and etching the second passivation layer 212b to expose the first electrically conducting surface 208a of the wire-bond pad 204 and the intermediate electrically conducting surface 208c of the flip-chip bond pad 210. In forming the polymer layer 218 according to operation 406, the method 400 may further include forming the polymer layer 218 over the second passivation layer 212b. The method 400 may further include forming an under-bump metallurgy layer 222 over the flip-chip bond pad 210 prior to depositing the first electrically conducting material 309 such that the under-bump metallurgy layer 222 is formed between the flip-chip bump 206 and the flip-chip bond pad 210. The method may further include forming the first electrically conducting surface 208a of the wire-bond pad 204 to be recessed relative to a surface 220 of the polymer layer 218. The method may further include forming the second electrically conducting surface 208b of the flip-chip bump 206 to extend beyond the surface 220 of the polymer layer 218.
Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor structure (200b, 200c) is provided. The semiconductor structure (200b, 200c) may include a wire-bond pad 204 including a first electrically conducting surface 208a and a flip-chip bump 206 including a second electrically conducting surface 208b. The semiconductor structure (200b, 200c) may further include a polymer layer 218 formed over a surface of the semiconductor structure (200b, 200c) such that the first electrically conducting surface 208a of the wire-bond pad 204 is located under a first opening 306c in the polymer layer 218, and the flip-chip bump 206 also extends through a second opening 306c in the polymer layer 218. The semiconductor structure (200b, 200c) may further include a flip-chip bond pad 210 and a first passivation layer 212a formed over a surface of the semiconductor structure (200b, 200c) that includes a plurality of electrical contact structures 216.
According to various embodiments, the wire-bond pad 204 may extend through the first passivation layer 212a and may be electrically connected to a first one of a plurality of electrical contact structures 216. Similarly, the flip-chip bump 206 may be connected to the flip-chip bond pad 210, which may extend through the first passivation layer 212a and may be electrically connected to a second one of the plurality of electrical contact structures 216. The semiconductor structure (200b, 200c) may further include an under-bump metallurgy layer 222 formed between the flip-chip bump 206 and the flip-chip bond pad 210. The semiconductor structure (200b, 200c) may further include a second passivation layer 212b formed over the first passivation layer 212a such that the first electrically conducting surface 208a of the wire-bond pad 204 is located under a third opening 306b in the second passivation layer 212b. Similarly, the flip-chip bump 206 may extend through a fourth opening 306b in the second passivation layer 212b. According to various embodiments, the polymer layer 218 may be formed over the second passivation layer 212b
According to various embodiments, the polymer layer 218 may include one of polyimide, benzocyclobutene, or polybenzo-bisoxazole. Further, each of the wire-bond pad 204 and the flip-chip bond pad 210 include copper or aluminum. In further embodiments, the under-bump metallurgy layer 222 may include titanium and copper and the flip-chip bump 206 may include copper. According to various embodiments, the first electrically conducting surface 208a of the wire-bond pad 204 may be recessed relative to a surface 220 of the polymer layer 218 and the second electrically conducting surface 208b of the flip-chip bump 206 may extend beyond the surface 220 of the polymer layer 218.
According to another aspect of the present disclosure, a wafer-level semiconductor structure (200a, 200b, 200c) is provided. The wafer-level semiconductor structure (200a, 200b, 200c) may include a semiconductor substrate 102 including a plurality of semiconductor structures (200b, 200c) and a plurality of bonding structures (204, 206) electrically connected to the plurality of semiconductor structures (200b, 200c) and formed on a dielectric substrate 214. Each of the plurality of bonding structures (204, 206) may include a wire-bond pad 204 including a first electrically conducting surface 208a and a flip-chip bump 206 including a second electrically conducting surface 208b.
The wafer-level semiconductor structure (200a, 200b, 200c) may further include a first passivation layer 212a; a second passivation layer 212b; and a polymer layer 218 formed over the second passivation layer 212b, wherein the first electrically conducting surface 208a of the wire-bond pad 204 is located under first openings 306a in the first passivation layer 212a, second openings 306b in the second passivation layer 212b, and third openings 306c in the polymer layer 218, and wherein the flip-chip bump 206 extends through the first openings 306a in the first passivation layer 212a, second openings 306b in the second passivation layer 212b, and third openings 306c in the polymer layer 218.
In one embodiment, the polymer layer 218 may include one of polyimide, benzocyclobutene, or polybenzo-bisoxazole. In one embodiment, the wafer-level semiconductor structure (200a, 200b, 200c) may further include: a flip-chip bond pad 210; and an under-bump metallurgy layer 222 formed over the flip-chip bond pad 210, wherein the flip-chip bump 206 is formed over the under-bump metallurgy layer 222. In one embodiment, the first electrically conducting surface 208a of the wire-bond pad 204 may be recessed relative to a top surface 220 of the polymer layer 218; and the second electrically conducting surface 208b of the flip-chip bump 206 may extend beyond the top surface 220 of the polymer layer 218.
Disclosed embodiments may be advantageous by providing wafer-level semiconductor structures (200a, 200b, 200c) having wire-bond pads 204 and flip-chip bumps 206 that have electrically conductive surfaces (208a, 208b). In this regard, a polymer layer 218 deposited over the wire-bond pads 204 during formation of the flip-chip bumps 206 may be etched following the formation of the flip-chip bumps 206 to thereby expose the conductive surface 208a of the wire-bond pads 204. As such, wafer-level testing may be carried out on both wire-bond pads 204 and flip-chip bumps 206 before singulating wafer-level semiconductor structures 200a into semiconductor dies. Such testing may provide advantages by allowing screening for potential damage that may result due to multiple CMOS fabrication processes and high temperatures used in the formation of the polymer layer 218. Package-level testing may then be carried out once the semiconductor dies have been singulated and assembled into semiconductor packages. Semiconductor dies having both wire-bond pads 204 and flip-chip bumps 206 may be used in situations where both flip-chip and wire bonding may be used within the same semiconductor package and may provide flexibility in how such dies are integrated into different packaging configurations.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of this disclosure.
