The present invention is directed to semiconductor integrated circuits and, more particularly, to a method of dicing a semiconductor wafer.
Producing semiconductor devices involves fabricating an array of the integrated circuits in a semiconductor wafer. The wafer is typically formed from mono-crystalline semiconductor material, such as silicon, or from compound semiconductor materials. The active and passive elements of the circuits are formed in and on the wafer by steps such as deposition of metals, poly-crystalline semiconductor and other materials, epitaxial growth, etching, patterning, doping and oxidation. The integrated circuits may include electronic components and micro-electromechanical systems (MEMS), for example.
After fabrication of the array of integrated circuits, the wafer is diced to produce singulated semiconductor dies. The dicing operation consists of separating the semiconductor devices along orthogonal saw streets. Conventional dicing techniques include mechanical cutting, typically by sawing, laser cutting, and laser scribing. Continued progress in reduction of the size of the semiconductor dies with the same or increased functionality and complexity of the electronic circuits integrated in the dies means that the width of the saw streets may represent a significant reduction in the density of dies formed in the wafer. It would be desirable to reduce the width of the saw streets to allow for more area on the wafer to be used for forming circuitry.
The present invention is illustrated by way of example and is not limited by embodiments thereof shown in the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, certain vertical dimensions have been exaggerated relative to horizontal dimensions.
The packaged semiconductor device 100 includes a set of exposed electrical contact elements 118, which may be formed from part of a lead frame which also provides the die support 110. The active face 104 of the semiconductor die 102 has a plurality of electrical contact elements 120 that are electrically connected with the exposed electrical contact elements 118 such as with bond wires 122, which may be done using conventional wire bonding processes and equipment. A molding compound 124 covers the first face 104, fillet 116 and bond wires 122.
As shown in
The wafer 200 on the backing 202 is installed in a saw represented in the drawing by a first saw blade 204. The first saw blade 204 is used to make a first cut in the front face of the wafer 200 to form a groove 206 part way through the thickness of the wafer 200 in the active faces 104 of the semiconductor dies 102.
The first saw blade 204 is displaced along a set of parallel saw streets and an orthogonal set of parallel saw streets between adjacent semiconductor dies 102 to form the grooves 206. The displacement of the first saw blade 204 is guided by the alignment marks on the first face 104 of the wafer 200. A width S1 of the grooves 206 is defined by the width of the first saw blade 204. Each groove 206 will form the grooves 114 in the active faces 104 and edges 108 of adjacent semiconductor dies 102.
Referring to
The saw streets in the front face of the wafer 200 have a width that is greater than the kerf width S1 of the first saw blade 204 because of the positioning tolerances of the saw cut. In practice, with currently available techniques, it is difficult to reduce the wasted width of the saw streets to less than 40 μm, which represents a significant reduction in the area of the active faces of the dies in the wafer.
The grooves 604 reduce the thickness of the wafer 200 in the saw streets so that the width S2 of the singulation and the wasted width of the saw streets can be substantially reduced. The width S1 of the grooves 604 does not reduce the area available for the active faces 104 of the dies (integrated circuits) 102, since the grooves 604 are cut from the back face 402 of the wafer 200 and are not cut through to the front face 400.
In one example of an embodiment of the method of the invention, scanning the laser beam 704 scribes the wafer 200 from the front face 400 and singulating the dies (integrated circuits) 102 includes loading the wafer 200 mechanically to cleave the wafer along the saw streets. Singulating the dies 102 includes mounting the wafer 200 with the back face 402 attached to a back face adhesive support element 700 after cutting the grooves 604. Loading the wafer 200 mechanically includes stretching the back face adhesive support element 700 radially to apply a radial tensile stress to the back face 402. In the operation of scribing the wafer 200, since the thickness of the wafer 200 is reduced by the grooves 604, the width S2 of the regions affected by the laser scans can be reduced.
In another example of an embodiment of the method of the invention, scanning the laser beam 704 cuts the wafer 200 from the front face 400 and singulates the dies 102. Again, since the thickness of the wafer 200 is reduced by the grooves 604, the width S2 of the regions affected by the laser scans can be reduced.
In one example of an embodiment of the method of the invention, the laser beam 704 alters the structure of the wafer 200 over a width less than and included within the width of the grooves 604. In the operation of scribing the wafer 200, the laser beam 704 produces defect regions below the front surface 400. The laser beam 704 is pulsed and scans each of the saw streets in a plurality of scans focused at respective depths in the wafer 200. The defects are caused by the material of the wafer 200 rapidly melting and solidifying again in the focal point of the laser beam.
In one example of an embodiment of the method of the invention, semiconductor dies produced by the method illustrated in
In one example of an embodiment of the method of the invention, cutting the grooves 604 includes mounting the wafer 200 with the front face 400 attached to a front face support element 500 and sawing partially through the wafer 200 from the back face 402. The wafer 200 includes alignment marks on the front face 400, the alignment marks being identifiable through the front face support element 500. Sawing partially through the wafer from the back face 402 is guided by the alignment marks on the front face 400. The alignment marks on the front face 400 also guide the subsequent scanning of the laser beam 704 on the front face 400.
At 904, the back of the wafer 200 is ground, to reduce the thickness of the wafer. In one example, the wafer 200 was 750 μm thick during the steps of fabricating the semiconductor dies 102 and was 150 μm thick after the back-grind operation.
At 906, the wafer 200 is then mounted with its front face 400 attached to the front face support element 500, as shown in
The saw blade 600 is used to make cuts in the back face 402 of the wafer 200 to form the grooves 604 part way through the thickness of the wafer 200 in the back face 402 of the wafer and the back faces 106 of the semiconductor dies 102 at 908. The grooves extend along the orthogonal sets of saw streets. The grooves 604 are shown as having a rectangular cross-section but it will be appreciated that the grooves 604 may have any suitable cross-section, which will typically be defined by the cross-section of the saw blade 600. The width of the grooves 604 is approximately 40 μm in this example. The depth of the grooves 604 is approximately half the thickness of the wafer 200 (after back-grinding).
After cutting the grooves 604, the support 500 is removed from the wafer 200, which is then attached by its back face 402 to an adhesive, elastic support 700 at 910. At 912, the laser 702 shown in
At 914, the semiconductor devices 102 are singulated. The singulation operation involves loading the back face 402 of the wafer 200 mechanically to cleave the wafer along the dicing streets. As shown in
After the singulation, at 916 external connection elements are provided for the semiconductor dies 102. The external connection elements may be exposed electrical contact elements 118 of the kind shown in
It will be appreciated that other ways of providing external electrical contacts may be used, such as ball grid array (BGA) or land grid array (LGA) and with or without redistributed chip packaging (RCP), in which internal electrical contact elements on the active die face are connected to exposed pads on the surface of the package by a redistribution panel to route the signals, and the power and ground connections. It will also be appreciated that semiconductor dies may be packaged in other packages than encapsulation, and alternatively may be supplied bare for incorporation in apparatus which may then be packaged.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.
For example, the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
In the claims, the word ‘comprising’ or ‘having’ does not exclude the presence of other elements or steps then those listed in a claim. The terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
Number | Date | Country | Kind |
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201210352749.3 | Jul 2012 | CN | national |