Patent Application
20130056752
1. Field of the Invention
The present invention relates to a silicon carbide substrate, a method of manufacturing a silicon carbide substrate, and a method of manufacturing a semiconductor device.
2. Description of the Background Art
In recent years, various studies have been made on the crystal growth method to obtain a silicon carbide substrate having sufficient size and sufficiently low defect. For defect reduction, reducing the micropipe density is particularly an issue.
According to the method exemplified in National Patent Publication No. 2008-515749, seed crystal having the diameter of at least approximately 100 mm is used in crystal growth. This publication teaches that the micropipe density could be reduced down to 7.23 cm−2. However, the diameter of 100 mm is still too small as compared with the diameter of a silicon substrate used in the industry of the semiconductor field. Moreover, the micropipe density of 7.23 cm−2 is still too high in the attempt to obtain a semiconductor device of higher reliability.
U.S. Application Publication No. 2004/0187766 proposes using a plurality of single crystal films transferred onto a support substrate as the growing plane. It is asserted that increasing the number of single crystal films can accommodate manufacturing a substrate having a diameter of approximately 300 mm. It is also asserted that the micropipe density can be set to less than or equal to 1 cm−2.
According to the study carried out by the inventors, it was found that a micropipe having a large cross-sectional area is formed on the border of the plurality of single crystal films in the art disclosed in the aforementioned specification. When a micropipe having a large cross-sectional area, particularly a cross-sectional area exceeding 1 μm2, is formed at the silicon carbide substrate, various problems may occur in manufacturing a semiconductor device using such a silicon carbide substrate, despite the small micropipe density. Particularly, leakage through the micropipe may become a problem. Specifically, such great leakage will render difficult the vacuum chucking of the silicon carbide substrate. Furthermore, in a process using liquid, that liquid may pass through the silicon carbide substrate to leak out.
In view of the foregoing, an object of the present invention is to provide a silicon carbide substrate having low micropipe density and without a micropipe of large cross-sectional area. Another object of the present invention is to provide a semiconductor device of high reliability.
A silicon carbide substrate of the present invention includes an edge region and a valid region. The edge region has a width of 5 mm. The valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm2. The valid region is formed such that a micropipe having a cross-sectional area exceeding 1 μm2 is not present. The valid region includes a plurality of high-quality regions occupying 70% or more of the valid region. Each of the plurality of high-quality regions has a rectangular shape, an area greater than or equal to 1 cm2, and a micropipe density less than or equal to 1 micropipe per 1 cm2.
According to this silicon carbide substrate, a micropipe having a large cross-sectional area is not present in the valid region of the silicon carbide substrate. Accordingly, inconvenience caused by the micropipe in manufacturing a semiconductor device using a silicon carbide substrate can be suppressed. Such inconvenience may be caused by leakage through the micropipe. Such great leakage will render difficult the vacuum chucking of the silicon carbide substrate. Furthermore, in a process using liquid, that liquid may pass through the silicon carbide substrate to leak out.
By manufacturing a semiconductor device using a high-quality region, i.e. a region of low micropipe density, according to the silicon carbide substrate, the reliability of the obtained semiconductor device can be improved.
Preferably, the silicon carbide substrate has a crystal structure of 4H polytype. Accordingly, the physical property of the silicon carbide substrate is rendered favorable.
Preferably, each of the plurality of high-quality regions has the shape of either a square with one side greater than or equal to 1 cm, or a rectangle with a short side greater than or equal to 1 cm. Accordingly, each high-quality region will not have an excessively small dimension. The shape of each high-quality region will be suitable for forming a semiconductor element structure.
Preferably, the in-plane variation of the plane orientation of the silicon carbide substrate is less than 0.2° with respect to one plane orientation. Accordingly, variation in the plane orientation of the silicon carbide substrate becomes smaller.
A silicon carbide substrate of the present invention can be manufactured by the method set forth below. A plurality of single crystal substrates, each having a main surface greater than or equal to 1 cm2 in area are prepared. The plurality of single crystal substrates include first to third single crystal substrates. The first single crystal substrate has a main surface surrounded by an outer edge including a first linear segment having a first end. The second single crystal substrate has a main surface surrounded by an outer edge including a second linear segment having a second end. The third single crystal substrate has a main surface surrounded by an outer edge including a third linear segment having third and fourth ends. By combining the main surface of each of the plurality of single crystal substrates to each other, a plurality of single crystal substrate are arranged to constitute one plane having an area greater than or equal to 100 cm2. The step of arranging a plurality of single crystal substrates is carried out such that the first to third single crystal substrates are adjacent to each other at the first to third linear segments, the first and the second ends meet at one point, the one point is located on the third linear segment, and the one point is located apart from each of the third and fourth ends. By depositing silicon carbide through sublimation on the one plane, single crystal silicon carbide is grown on the one plane. Then, the single crystal silicon carbide is sliced.
According to the method of manufacturing a silicon carbide substrate, the border where the first and second linear segments overlap and extend among the boundaries between the single crystal substrates runs against the section of the third linear segment extending linearly. Accordingly, the borders take a T shape. If the borders take a cross shape, a cavity that becomes the origin of generating a large micropipe is readily formed at the center of the cross shape. The T-shape border is advantageous in that such a cavity is not readily formed, which in turn suppresses generation of a large micropipe.
Preferably, each of the plurality of single crystal substrates has a hexagonal crystal structure. More preferably, the crystal structure is of the 4H polytype. Accordingly, the physical property of the silicon carbide substrate is rendered favorable.
Preferably, a side face of the first single crystal substrate including the first linear segment and a side face of the second single crystal substrate including the second linear segment each have an inclination greater than or equal to 5° to an m plane. More preferably, the component of the inclination about the c axis is greater than or equal to 5°. Accordingly, generation of a micropipe having a large cross-sectional area at the border between the first and second single crystal substrates can be suppressed.
Preferably, each of the plurality of single crystal substrates has the shape of either a square with one side greater than or equal to 1 cm, or a rectangle with a short side greater than or equal to 1 cm. Accordingly, each single crystal substrate will not have an excessively small dimension. By growing silicon carbide on the single crystal substrate, the shape of the high-quality region obtained will be suitable for forming a semiconductor element structure.
Preferably, the main surface of each of the plurality of single crystal substrates has an inclination less than 0.2° to the one plane orientation. Accordingly, variation in the plane orientation of the silicon carbide substrate is reduced.
Preferably, the outer edge of the one plane is trimmed after the step of arranging a plurality of single crystal substrates and before the step of growing single crystal silicon carbide. Accordingly, a plurality of single crystal substrates corresponding to seed crystal can take a predetermined configuration.
A method of manufacturing a semiconductor device according to the present invention includes the following steps. A silicon carbide substrate is prepared. The silicon carbide substrate includes an edge region and a valid region. The edge region has a width of 5 mm. The valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm2. The valid region is formed to avoid the presence of a micropipe exceeding 1 μm2 in cross-section. The valid region includes a plurality of high-quality regions occupying 70% or more of the valid region. Each of the plurality of high-quality regions has a rectangular shape, an area greater than or equal to 1 cm2, and a micropipe density less than or equal to 1 micropipe per 1 cm2. A plurality of semiconductor element structures are formed by forming at least one semiconductor element structure on each of the plurality of high-quality regions at the silicon carbide substrate. The silicon carbide substrate is diced such that the plurality of semiconductor element structures are separated from each other.
According to a method of manufacturing a semiconductor device, a semiconductor device is manufactured using the silicon carbide substrate set forth above. Accordingly, inconvenience caused by the micropipe in manufacturing a semiconductor device can be suppressed. Furthermore, the reliability of the semiconductor device can be improved since a semiconductor element structure is formed in the high-quality region of the silicon carbide substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Embodiments of the present invention will be described hereinafter based on the drawings.
As to the crystallographic definitions in the present specification, the individual orientation is represented by [ ], the group orientation by < >, the individual plane by ( ), and the group plane by { }. For a negative index, a negative sign is applied before the numeral in the present specification although generally a bar (−) is attached above the numeral in crystallographic expressions.
As shown in
Silicon carbide substrate 80 includes an edge region 60 and a valid region 70. The border between edge region 60 and valid region 70 is virtual, and does not necessarily have to be observable.
Edge region 60 is the portion located at the rim of silicon carbide substrate 80. The quality of edge region 60 is generally of no concern in manufacturing a semiconductor device using silicon carbide substrate 80. The width WD of edge region 60 is 5 mm. In
Valid region 70 is surrounded by edge region 60. A micropipe having a cross-sectional area exceeding 1 μm2 is not present in valid region 70. Valid region 70 includes a plurality of high-quality regions 71 occupying 70% or more of valid region 70. In valid region 70, the border between the portion of high-quality region 71 and another portion is virtual, and does not necessarily have to be observable.
Each high-quality region 71 has a micropipe density less than or equal to 1 micropipe per 1 cm2. Each high-quality region 71 has a rectangular shape, and an area greater than or equal to 1 cm2. Preferably, each high-quality region 71 has the shape of either a square with one side greater than or equal to 1 cm, or a rectangle with a short side greater than or equal to 1 cm. In the present embodiment, each high-quality region 71 corresponds to a square having one side greater than or equal to 1 cm. Furthermore, the shapes of all high-quality regions 71 are equal to each other.
A portion DF that has a relatively high micropipe density may be present between high-quality regions 71 in valid region 70. Although a micropipe exceeding a cross-sectional area of 1 μm2 is not present in portion DF, the density of micropipes having a cross-sectional area less than or equal to 1 μm2 is higher than that of high-quality region 71, and the density may exceed 1 micropipe per 1 cm2. Portion DF typically extends linearly, and may be observable more clearly by applying wet etching.
A method of manufacturing silicon carbide substrate 80 will be described hereinafter.
As shown in
Then, by combining the main surfaces of each of the plurality of single crystal substrates 10, the plurality of single crystal substrates 10 are arranged to constitute a plane FS (one plane) having an area greater than or equal to 100 cm2. Specifically, a plurality of single crystal substrates 10 are arranged on a mount 41. Mount 41 is formed of a heat-resistant material, preferably a material that can have a solid state stably at 1800° C., more preferably, a material that can have a solid state stably at 2100° C., such as graphite. Each single crystal substrate 10 and mount 41 may be fastened by an adhesive such as a carbon-based adhesive.
As shown in
By arranging a plurality of single crystal substrate 10, first to third single crystal substrates 11-13 are adjacent to each other at first-third linear segments L1-L3. Furthermore, at a point PT (one point), first end E1 and second end E2 meet. Point PT is located on third linear segment L3.
As used herein, “adjacent” implies that any gap between the substrates is substantially eliminated. This gap is preferably less than or equal to 100 μm, more preferably less than or equal to 20 μm. Furthermore, “first end E1 and second end E2 meeting at point PT (one point)” implies that each of first end E1 and second end E2 substantially overlap at point PT. In other words, there is substantially no difference in distance between each of first and second ends E1 and E2 and point PT″. This distance is less than or equal to 100 μm, more preferably less than or equal to 20 μm. “Point PT located on third linear segment L3” implies that the distance between point PT and third linear segment L3 is substantially eliminated. This distance is less than or equal to 100 μm, more preferably less than or equal to 20 μm.
Point PT is located apart from each of third end E3 and fourth end E4. In other words, point PT is apart from each of third end E3 and fourth end E4 by at least a predetermined distance. This distance is preferably greater than or equal to 0.2 mm, more preferably greater than or equal to 1 mm. As a result, linear segments L1 and L3 constitute a T-shaped border. Preferably, a T-shaped border is formed at all the sections where three or more single crystal substrates 10 are adjacent.
The outer edge of plane FS may be trimmed along a line CL (
As shown in
As shown in
As shown in
The temperature in the sublimation method is set greater than or equal to 2100° C. and less than or equal 2500° C., for example. The pressure in the sublimation method is preferably set greater than or equal to 1.3 kPa and less than or equal to the atmospheric pressure, more preferably less than or equal to 13 kPa to increase the growing rate.
Then, mount 41 is taken out from crucible 42.
As shown in
A comparative example for the present embodiment will be described hereinafter.
As shown in
According to silicon carbide substrate 80 of the present embodiment, a micropipe having a large cross-sectional area is not present in valid region 70 of silicon carbide substrate 80. Accordingly, inconvenience caused by a micropipe in the manufacturing step of a semiconductor device using silicon carbide substrate 80 can be suppressed. This inconvenience particularly occurs by the leakage through the micropipe. Such a large leakage will render difficult the vacuum chucking of silicon carbide substrate 80. Furthermore, in a process using liquid, that liquid may pass through silicon carbide substrate 80 to leak out.
According to silicon carbide substrate 80 set forth above, the reliability of a semiconductor device can be improved by manufacturing a semiconductor device using a plurality of high-quality regions 71, i.e. regions having a low micropipe density.
Preferably, silicon carbide substrate 80 has the 4H polytype crystal structure. Accordingly, the physical property of silicon carbide substrate 80 is rendered favorable.
Preferably, each of high-quality regions 71 has the shape of either a square with one side greater than or equal to 1 cm, or a rectangle with a short side greater than or equal to 1 cm. Accordingly, each high-quality region 71 will not have an excessively small dimension. The shape of each high-quality region 71 will be suitable for forming a semiconductor element structure.
Preferably, the in-plane variation orientation of the plane orientation at silicon carbide substrate 80 is less than 0.2° with respect to one plane orientation. Accordingly, variation in the plane orientation of silicon carbide substrate 80 is reduced.
According to the method of manufacturing silicon carbide substrate 80 of the present embodiment, the border where first and second linear segments L1 and L2 overlap and extend, among the borders of single crystal substrates, runs against a section of third linear segments L3 extending linearly. Accordingly, the border takes a T shape. In the case where the border takes a cross shape (
Preferably, each of the plurality of single crystal substrate 10 has a hexagonal crystal structure. More preferably, the crystal structure is of the 4H polytype. Accordingly, the physical property of silicon carbide substrate 80 is rendered favorable.
Preferably, the side face of first single crystal substrate 11 and second single crystal substrate 12 including first linear segment L1 and second linear segment L2, respectively, (
Preferably, each single crystal substrate 10 has the shape of either a square with one side greater than or equal to 1 cm, or a rectangle with a short side greater than or equal to 1 cm. Accordingly, each single crystal substrate will not have an excessively small dimension. By growing silicon carbide on each single crystal substrate 10, the shape of high-quality region 71 obtained will be suitable for forming a semiconductor element structure.
Preferably, the main surface of each of the plurality of single crystal substrates 10 has an inclination less than 0.2° to the one plane orientation. Accordingly, variation in the plane orientation of the silicon carbide substrate is reduced.
Preferably, the outer edge of plane FS is trimmed (broken line CL in
As shown in
Silicon carbide substrate 80 and buffer layer 121 are of n conductivity type. The concentration of the n type conduction impurities in buffer layer 121 is 5×1017 cm−3, for example. The thickness of buffer layer 121 is 0.5 μm, for example.
Breakdown voltage holding layer 122 is formed on buffer layer 121, made of n conductivity type silicon carbide. For example, the thickness of breakdown voltage holding layer 122 is 10 μm, and the concentration of the n type conduction impurities is 5×1015 cm−3.
At the surface of breakdown voltage holding layer 122, a plurality of p regions 123 having p type conductivity are formed spaced apart from each other. In and at the surface layer of p region 123, an n+ region 124 is formed. A p+ region 125 is formed adjacent to n+ region 124. Gate insulating film 126 is formed on a region of breakdown voltage holding layer 122 exposed between p regions 123. Specifically, gate insulating film 126 is formed extending from above n+ region 124 at one of p regions 123, over p region 123, a region of breakdown voltage holding layer 122 exposed between two p regions 123, the other p region 123, as far as above n+ region 124 at the relevant other p region 123. Gate electrode 110 is formed on gate insulating film 126. Source electrode 111 is formed on n+ region 124 and p+ region 125. Upper source electrode 127 is formed on source electrode 111.
The maximum value of the nitrogen atom concentration at a region within 10 nm from the boundary between gate insulating film 126 and the semiconductor layer including n+ region 124, p+ region 125, p region 123 and breakdown voltage holding layer 122 is greater than or equal to 1×1021 cm−3. Accordingly, the mobility at the channel region particularly under gate insulating film 126 (the region in contact with gate insulating film 126 and the portion of p region 123 located between n+ region 124 and breakdown voltage holding layer 122).
A method of manufacturing MOSFET 100 will be described hereinafter. First, silicon carbide substrate 80 (
As shown in
As shown in
By selectively implanting p type conduction impurities to a region of breakdown voltage holding layer 122, p type region 123 is formed. Then, by selectively introducing n type conduction impurities into a predetermined region, n+ region 14 is formed. By selectively introducing p type conduction impurities into a predetermined region, p+ region 125 is formed. Selective introduction of impurities is carried out using a mask made of oxide film, for example. The patterning of the oxide film mask may be carried out by photolithography.
The exposure in photolithography on a substrate of a relatively large size is often carried out over a plurality of times, instead of being completed at one time. In other words, a plurality of regions of the substrate are often sequentially exposed. The region corresponding to the exposure-by-exposure basis is preferably one or a plurality of high-quality regions 71.
Following the implantation step, activation annealing is carried out. For example, annealing is carried out for 30 minutes at the heating temperature of 1700° C. in an argon atmosphere, for example.
As shown in
Then, a nitride annealing step (step S24 (
As shown in
On gate insulating film 126, a resist film having a pattern is formed by photolithography. Using this resist film as a mask, the region of gate insulating film 126 located above n+ region 124 and p+ region 125 is removed by etching. Accordingly, an opening is formed at gate insulating film 126. At this opening, a conductor film is formed to be brought into contact with each of n+ region 124 and p+ region 125. Then, by removing the resist film, the region of the aforementioned conductor film located on the resist film is removed (lift off). The conductor film may be a metal film, for example nickel (Ni). As a result of the lift off, source electrode 111 is formed.
At this stage, heat treatment is preferably carried out for alloying. For example, heat treatment is carried out for 2 minutes at the heating temperature of 950° C. in an atmosphere of argon (Ar) gas that is inert gas.
As shown in
Thus, step S20 (
Then, silicon carbide substrate 80 is diced such that a plurality of semiconductor chips are separated from each other. For example, in the case where one semiconductor chip is formed at each of high-quality regions 71, dicing is carried out such that high-quality regions 71 are separated from each other. In the case where a plurality of semiconductor chips are formed at each of high-quality regions 71, high-quality regions 71 are separated, not only from each other, but also into a group of high-quality regions 71, by dicing.
Thus, MOSFET 100 is obtained.
According to the method of manufacturing a semiconductor device of the present embodiment, an MOSFET 100 is manufactured using silicon carbide substrate 80 set forth above. Since a micropipe having a cross-sectional area exceeding 1 μm2 is not present in valid region 70 (
Since the micropipe density of high-quality region 71 (
A configuration in which the conductivity types are interchanged, i.e. the p type and n type exchanged, may be employed. Furthermore, although the description is based on MOSFET 100, the semiconductor device may be a metal insulator semiconductor FET (MISFET) other than a MOSFET. Moreover, the semiconductor device is not limited to a MOSFET, and may be an IGBT (Insulated Gate Bipolar Transistor) or a JFET (Junction FET).
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-193463 | Sep 2011 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| 61531225 | Sep 2011 | US |
