The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. Another multi-gate device, introduced in part to address performance challenges associated with FinFETs, is the gate-all-around (GAA) transistor. GAA transistors get their name from the gate structure which extends completely around the channel, providing better electrostatic control than FinFETs. FinFETs and GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.
In general, GAA transistors may be implemented, for example, in cases where FinFETs can no longer meet performance requirements. However, despite having many desirable features, GAA transistor fabrication has continued to face challenges as a result of the ongoing scaling down of semiconductor IC dimensions.
Thus, existing techniques have not proved entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Additionally, in the discussion that follows, dimensions (e.g., such as thickness, width, length, etc.) for a given layer or other feature may at times be described using terms such as “substantially equal”, “equal”, or “about”, where such terms are understood to mean within +/−10% of the recited value or between compared values. For instance, if dimension A is described as being “substantially equal” to dimension B, it will be understood that dimension A is within +/−10% of dimension B. As another example, if a layer is described as having a thickness of about 100 nm, it will be understood that the thickness of the layer may in a range between 90-110 nm.
It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a P-type transistor or an N-type transistor. Specific examples may be presented and referred to herein as FinFETs, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) transistor. A GAA transistor includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in semiconductor channel layers. In various embodiments, the semiconductor channel layers may include nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configurations. Presented herein are embodiments of devices that may have one or more channel regions (e.g., semiconductor channel layers) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single semiconductor channel layer) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
For GAA transistors, inner spacers are formed between lateral ends of adjacent semiconductor channel layers, and between a source/drain feature and a gate structure formed in a channel region between adjacent semiconductor channel layers. In an exemplary GAA transistor process flow, fins may be formed that include an epitaxial stack of layers (e.g., alternating semiconductor channel layers and dummy layers) and one or more dummy gate stacks formed over the epitaxial stack of layers. The dummy gate stacks include one or more sidewall spacers. In some cases, formation of the sidewall spacers may also result in sidewall spacer portions which remain on sidewalls of at least a lower portion of the epitaxial stack of layers in source/drain regions of the device. After formation of the sidewall spacers, a source/drain etch process is performed to remove portions of the epitaxial stack of layers in source/drain regions of the device adjacent to the dummy gate stacks. The source/drain etch process forms trenches, in the source/drain regions of the device, that are disposed between the sidewall spacer portions which were previously formed on the sidewalls of at least the lower portion of the epitaxial stack of layers in the source/drain regions. In an example, a trench formed in the source/drain region may have a trench width defined by a distance between opposing sidewall spacer portions on either side of the trench. The trenches formed by the source/drain etch process expose sidewall surfaces of lateral ends of the epitaxial stack of layers, including sidewall surfaces of the semiconductor channel layers and the dummy layers (e.g., also referred to as a fin sidewall surface). In some cases, the trench width may be substantially equal to a width of the lateral end of the epitaxial stack of layers or substantially equal to a width of the fin sidewall surface. A dummy layer recess process may then be performed to laterally etch the dummy layers to form recesses along sidewalls of the previously formed trenches between lateral ends of adjacent semiconductor channel layers.
Thereafter, an inner spacer material is deposited over the device, including along sidewalls of the trenches, within the recesses, and over the opposing sidewall spacer portions on either side of each of the trenches. In particular, deposition of the inner spacer material over the opposing sidewall spacer portions on either side of each of the trenches effectively reduces the trench width and causes at least part of the fin sidewall surface to be covered by the deposited inner spacer material, which in turn degrades a process window for a subsequent inner spacer trim process. Thus, when the deposited inner spacer material is subsequently etched-back (trimmed) to form inner spacers along the sidewalls of the trenches between the lateral ends of adjacent semiconductor channel layers, and because of the reduced process window for the inner spacer etch process, at least some of the inner spacer material may remain on lateral ends of at least one of the semiconductor channel layers of the epitaxial stack of layers (e.g., at least the bottommost semiconductor channel layer). As a result, source/drain features that are subsequently formed within the trenches will not only contact the adjacent inner spacers and the semiconductor channel layers with lateral ends that are substantially free of inner spacer material, but also one or more semiconductor channel layers (e.g., such as the bottommost semiconductor channel layer) with at least some inner spacer material disposed on a lateral end (e.g., on a fin sidewall surface of the semiconductor channel layer). The contact resistance between the source/drain features and the semiconductor channel layers will thus be increased, and the epitaxial growth quality of the source/drain features will be degraded.
Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include methods and structures for providing multi-gate devices (e.g., such as a GAA transistors) having improved dummy gate sidewall spacers for inner spacer formation. In some embodiments, fins including an epitaxial stack of layers (e.g., alternating semiconductor channel layers and dummy layers) and one or more dummy gate stacks formed over the epitaxial stack of layers are provided. As noted above, the dummy gate stacks include one or more sidewall spacers. However, in accordance with embodiments of the present disclosure, the dummy gate sidewall spacers may include a multi-layer sidewall spacer with constituent layers having different etch rates. In some cases, the dummy gate sidewall spacers include a bilayer sidewall spacer where the two layers of the bilayer sidewall spacer each have different etch rates. In this example, a first layer of the bilayer sidewall spacer (e.g., inner sidewall spacer layer) is formed over the dummy gates and over the epitaxial stack of layers in source/drain regions of the device. Thereafter, a second layer of the bilayer sidewall spacer (e.g., outer sidewall spacer layer) is formed over the first layer of the bilayer sidewall spacer. In some cases, the first layer of the bilayer sidewall spacer has a greater etch rate than the second layer of the bilayer sidewall spacer. Generally, for a multi-layer sidewall spacer (e.g., more than two layers), the sidewall spacer layer that is deposited first (e.g., innermost sidewall spacer layer), and is thus in direct contact with the dummy gates and the epitaxial stack of layers in source/drain regions of the device, has the highest etch rate. After forming the first and second layers of the bilayer sidewall spacer, a sidewall spacer etch-back process and source/drain etch process is performed. In some cases, the sidewall spacer etch-back process and the source/drain etch process may be performed as separate etch processes. Alternatively, the sidewall spacer etch-back process and the source/drain etch process may be performed as a single etch process, for example, where a single etch process forms trenches in source/drain regions while also forming sidewall spacer portions. In some embodiments, and because of the higher etch rate of the first layer of the bilayer sidewall spacer, the sidewall spacer etch-back process and the source/drain etch process will etch the first layer of the bilayer sidewall spacer faster than the second layer of the bilayer sidewall spacer. As a result, the trenches formed in the source/drain regions (e.g., by the source/drain etch process), and which have a trench width defined by a distance between opposing sidewall spacer portions on either side of the trench, will have a funnel shape (e.g., a top width of the trench is greater than a bottom width of the trench) that is formed by a combination of the sidewall spacer etch-back process and the source/drain etch process. In some cases, the funnel shape formation may also be referred to as a lateral push of the bilayer sidewall spacer. In various embodiments, the trench funnel shape provides for at least a top portion of the trench to have a width that is greater than a width of the lateral end of the adjacent epitaxial stack of layers (the fin sidewall surface).
After the dummy layer recess process, an inner spacer material is deposited over the device, including along sidewalls of the trenches, within the recesses (e.g., within which inner spacers are defined), and over the opposing sidewall spacer portions on either side of each of the trenches. The deposition of the inner spacer material over the opposing sidewall spacer portions on either side of each of the trenches once again effectively reduces the trench width; however, because of the funnel shape of the trenches, the process window for the subsequent inner spacer trim process remains sufficiently large. Thus, when the deposited inner spacer material is subsequently etched-back (trimmed) to form the inner spacers, substantially no inner spacer material remains on lateral ends of the semiconductor channel layers of the epitaxial stack of layers, including the bottommost semiconductor channel layer. As a result, source/drain features that are subsequently formed within the trenches will contact the adjacent inner spacers and the semiconductor channel layers, each of which has lateral ends (e.g., fin sidewall surfaces) that are substantially free of inner spacer material. Therefore, contact resistance between the source/drain features and the semiconductor channel layers will be improved (reduced) to provide enhanced device performance, epitaxial growth quality of the source/drain features will be improved, and there is no extra process cost. Other embodiments and advantages will be evident to those skilled in the art upon reading the present disclosure.
For purposes of the discussion that follows,
Referring to
In addition, the semiconductor device 300 may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the semiconductor device 300 includes a plurality of semiconductor devices (e.g., transistors), including P-type transistors, N-type transistors, etc., which may be interconnected. Moreover, it is noted that the process steps of method 200, including any descriptions given with reference to the figures are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow.
The method 200 begins at block 202 where a substrate including fins and dummy gates is provided. Referring to the example of
The fins 304, which include layers 308 and 310, may be formed by growing epitaxial layers of a first composition (e.g., which are subsequently patterned to form the layers 310) interposed by epitaxial layers of a second composition (e.g., which are subsequently patterned to form the layers 308). In an embodiment, the epitaxial layers of the first composition (e.g., used to form layers 310) are SiGe and the epitaxial layers of the second composition (e.g., used to form layers 308) are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. For example, in some embodiments, either of the epitaxial layers of the first composition or the second composition may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. By way of example, epitaxial growth of the epitaxial layers of the first composition or the second composition may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. It is also noted that while the layers 308, 310 are shown as having a particular stacking sequence within the fins 304, where the layer 308 is the topmost layer of the stack of layers 308, 310, other configurations are possible. For example, in some cases, the layer 310 may alternatively be the topmost layer of the stack of layers 308, 310. Stated another way, the order of growth for the layers 308, 310, and thus their stacking sequence, may be switched or otherwise be different than what is shown in the figures, while remaining within the scope of the present disclosure.
The fins 304 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the device 300, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate, and layers formed thereupon, while a wet and/or dry etch process forms trenches in unprotected regions through the epitaxial layers of the first composition and the second composition, and into the substrate, thereby leaving the plurality of extending fins 304.
In various embodiments, each of the fins 304 includes a substrate portion 302 formed from the substrate, the layers 310 (e.g., including the first composition), and the layers 308 (e.g., including the second composition). In some examples, the epitaxial layers 308 (e.g., including the second composition), or portions thereof, may form a channel region of a GAA transistor of the device 300. For example, the layers 308 may be referred to as semiconductor channel layers that are used to form a channel region of a GAA transistor. In various embodiments, the semiconductor channel layers (e.g., the layers 308 or portions thereof) may include nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configurations.
It is noted that while the fins 304 are illustrated as including three (3) layers of the epitaxial layer 310 and three (3) layers of the epitaxial layer 308, this is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed, where for example, the number of epitaxial layers depends on the desired number of semiconductor channel layers for the GAA transistor. In some examples, the number of epitaxial layers, and thus the number of semiconductor channel layers, is selected based on the device type being implemented by the GAA transistor (e.g., such as core (logic) devices, SRAM devices, or analog devices, among others). In some embodiments, the number of epitaxial layers 308, and thus the number of semiconductor channel layers, is between 3 and 10.
In some embodiments, the epitaxial layers 310 each have a thickness range of about 4-8 nanometers (nm). In some cases, the epitaxial layers 308 each have a thickness range of about 4-8 nm. As noted above, the epitaxial layers 308 may serve as channel region(s) for a subsequently formed multi-gate device (e.g., a GAA transistor) and its thickness may be chosen based at least in part on device performance considerations. The epitaxial layers 310 may serve to define a gap distance between adjacent channel region(s) for the subsequently formed multi-gate device and its thickness may also be chosen based at least in part on device performance considerations.
In a further embodiment of block 202, and still with reference to
After depositing the dielectric material, a CMP process may be performed to remove excess portions of the dielectric material and to planarize a top surface of the device 300, and an STI recess process (e.g., including a wet and/or dry etch process) is performed to recess the dielectric material between the fins 304 and form recessed STI features 312. In various examples, the fins 304 extend above the recessed STI features 312 such that the epitaxial stack of layers 308, 310 of each of the fins 304 is exposed.
In a further embodiment of block 202, and still referring to
In some embodiments, the gate stacks 311 include a dielectric layer 309 and an electrode layer 313 over the dielectric layer. The gate stacks 311 may also include one or more hard mask layers 314, 316. In some embodiments, the hard mask layer 314 may include a nitride layer, and the hard mask layer 316 may include an oxide layer. In some embodiments, the gate stacks 311 are formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. In some examples, the layer deposition process includes CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or a combination thereof. In forming the gate stacks 311 for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.
In some embodiments, the dielectric layer 309 of the gate stacks 311 includes silicon oxide. Alternatively, or additionally, the dielectric layer 309 may include silicon nitride, a high-K dielectric material or other suitable material. In some embodiments, the electrode layer 313 may include polycrystalline silicon (polysilicon). In some embodiments, the nitride of the hard mask layer 314 includes a pad nitride layer that may include Si3N4, silicon oxynitride or silicon carbide. In some embodiments, the oxide of the hard mask layer 316 includes a pad oxide layer that may include SiO2.
The method then proceeds to block 204 where a spacer layer is deposited. In particular, the spacer layer may be deposited after formation of the gate stacks 311. Still referring to the example of
The method 200 then proceeds to block 206 where a source/drain etch process is performed. With reference to
Thereafter, and in a further embodiment of block 206, the source/drain etch process is performed to remove the exposed epitaxial layers 308, 310 in source/drain regions of the device 300 to form trenches 407 which expose underlying substrate portions 302 of the fins 304, as well as the epitaxial stack of layers 308, 310 along the plane defined by section CC′ of
In some embodiments, and because of the higher etch rate of the spacer layer 402A as compared to the spacer layer 402B, the sidewall spacer etch-back process and the source/drain etch process will etch the spacer layer 402A faster than the spacer layer 402B. As a result, the trenches 407 formed in the source/drain regions (e.g., by the source/drain etch process), and which have a trench width W1, W2 defined by a distance between opposing sidewall spacer portions 411 on either side of the trench, will have a funnel shape (e.g., a top width of the trench W1 is greater than a bottom width of the trench W2) that is formed by a combination of the sidewall spacer etch-back process and the source/drain etch process. In some embodiments, the trench funnel shape provides for at least a top portion of the trench 407 to have a width W1 that is greater than a width W3 of the lateral end of the adjacent epitaxial stack of layers 308, 310 (the fin sidewall surface). In some cases, both the top width of the trench W1 and the bottom width of the trench W2 are greater than the width W3 of the lateral end of the adjacent epitaxial stack of layers 308, 310 (the fin sidewall surface). In this case, gaps 413 may be formed between the sidewall spacer portions 411 and a plane DD′ that includes a sidewall of the adjacent epitaxial stack of layers 308, 310.
The method 200 then proceeds to block 208 where a dummy layer recess process is performed. Referring to the example of
In an embodiment of block 208, the dummy layer recess process includes a lateral etch of the epitaxial layers 310 (dummy layers) to form recesses 502 along sidewalls of the trenches 407. In some cases, the dummy layer recess process may also etch, and thus further recess, the STI features 312. In various examples, the dummy layer recess process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, and once again because of the higher etch rate of the spacer layer 402A as compared to the spacer layer 402B, the dummy layer recess process will also further etch the spacer layer 402A faster than the spacer layer 402B, and may reduce the overall size of the sidewall spacer portions 411. As a result of the dummy layer recess process, the trenches 407 formed in the source/drain regions (e.g., by the source/drain etch process) will also now have a more prominent (enlarged) funnel shape with trench widths W1′, W2′, where a top width of the enlarged trench W1′ is greater than a bottom width of the enlarged trench W2′). In some embodiments, at least the top width W1′ is larger than the top width W1 (before the dummy layer recess process). In some cases, both the top width W1′ and the bottom width W2′ are larger than the top width W1 and the bottom width W2 (before the dummy layer recess process), respectively. Further, in some examples, the trench funnel shape provides for at least the top width W1′ to be greater than the width W3 of the lateral end of the adjacent epitaxial stack of layers 308, 310 (the fin sidewall surface). In some cases, both the top width of the trench W1′ and the bottom width of the trench W2′ are greater than the width W3 of the lateral end of the adjacent epitaxial stack of layers 308, 310 (the fin sidewall surface). Due to the more prominent (enlarged) funnel shape created by the dummy layer recess process, and in some embodiments, the gaps 413 may also be enlarged (e.g., a distance between the sidewall spacer portions 411 and the plane DD′ is increased). In some cases, the distance between the sidewall spacer portions 411 and the plane DD′, which generally defines the funnel shape of the trenches 407, may be between about 3-6 nm.
The method 200 then proceeds to block 210 where an inner spacer material is deposited. Referring to the example of
In an embodiment of block 210, the inner spacer material 602 may be deposited conformally over the device 300, including along sidewalls of the trenches 407, within the recesses 502 formed along sidewalls of the trenches 407, over the adjacent fin sidewall surface including the epitaxial stack of layers 308, 310, and over the opposing sidewall spacer portions 411 on either side of the trenches 407. After deposition of the inner spacer material 602, the trenches 407 will have reduced trench widths W4, W5, where a top width W4 is greater than a bottom width W5, and where the funnel shape of the trenches 407 is preserved. In some cases, the trench widths W4, W4 may be in a range of between about 8-11 nm, and a total height H1 of the fin sidewall spacer portions 411 and the inner spacer material 602 may be in a range of between about 10-20 nm. In various examples, the reduced top trench width W4 is less than the top width W1′ (before deposition of the inner spacer material 602), and the reduced bottom trench width W5 is less than the bottom width W2′ (before deposition of the inner spacer material 602). Further, in some examples, the top trench width W4 and the bottom trench width W5 may be less than the width W3 of the lateral end of the adjacent epitaxial stack of layers 308, 310 (the fin sidewall surface). However, even though the effective trench width is reduced (e.g., widths W4, W5), the funnel shape of the trenches 407 ensures that the process window for a subsequent inner spacer trim process remains sufficiently large, as discussed below. Generally, in accordance with the embodiments disclosed herein, the funnel shape of the trenches 407 may provide for about a 3-6 nm increase in trench width (increase in process window) as compared to at least some existing implementations.
In some examples, the inner spacer material 602 may include a dielectric material such as SiCNx. More generally, and in various examples, the inner spacer material 602 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., with a dielectric constant ‘k’<7), and/or combinations thereof. In some embodiments, the inner spacer material 602 may include amorphous silicon. In some embodiments, the inner spacer material 602 may have a thickness in a range of between about 3-6 nm and a dielectric constant (K value) in a range of between about 2.0-5.5. By way of example, the inner spacer material 602 may be formed by conformally depositing a dielectric material over the device 300 using processes such as a CVD process, an SACVD process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.
The method 200 then proceeds to block 212 where an inner spacer trim process is performed. Referring to the example of
After deposition of the inner spacer material layer 602, the inner spacer trim process (inner spacer etch-back process) is performed. In some embodiments, the inner spacer trim process substantially removes the inner spacer material 602 from the device 300, except for portions of the inner spacer material 602 that remain disposed within the recesses 502 formed along sidewalls of the trenches 407 after the inner spacer trim process and which define inner spacers 602A for the device 300. In some cases, and as illustrated, a thin layer of residual inner spacer material 602 may remain at the bottom of the trenches 407, along inner sidewalls of the sidewall spacer portions 411 (e.g., occupying a space previously defined by the gaps 413), and along portions of the recessed STI features 312. However, in accordance with various embodiments and because of the funnel shape of the trenches 407, the process window for inner spacer trim process is sufficiently large to ensure that substantially no inner spacer material 602 remains on lateral ends (e.g., fin sidewall surfaces) of the semiconductor channel layers (the epitaxial layers 308), including the bottommost semiconductor channel layer. As a result, source/drain features that are subsequently formed in the trenches 407, as described below, will directly contact the adjacent inner spacers 602A and the semiconductor channel layers (without any intervening inner spacer material 602). This will ensure a high-quality, low resistance contact between the source/drain features and the semiconductor channel layers (epitaxial layers 308). It is also noted that, in various examples, the inner spacers 602A may extend beneath spacer layer 402 of the gate stacks 311, and optionally at least partially beneath the electrode layer 313 of the gate stacks 311 (e.g., depending on the size of the recesses 502 formed along sidewalls of the trenches 407), while abutting subsequently formed source/drain features, described below.
To provide additional detail regarding the structure of the device 300 after the inner spacer trim process (block 212), reference is made to
The method 200 then proceeds to block 214 where source/drain features are formed. With reference to
In some embodiments, the source/drain features 902 are formed by epitaxially growing a semiconductor material layer in the source/drain regions. In various embodiments, the semiconductor material layer grown to form the source/drain features 902 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain features 902 may be formed by one or more epitaxial (epi) processes. In some embodiments, the source/drain features 902 may be in-situ doped during the epi process. For example, in some embodiments, epitaxially grown SiGe source/drain features may be doped with boron. In some cases, epitaxially grown Si epi source/drain features may be doped with carbon to form Si:C source/drain features, phosphorous to form Si:P source/drain features, or both carbon and phosphorous to form SiCP source/drain features. In some embodiments, the source/drain features 902 are not in-situ doped, and instead an implantation process is performed to dope the source/drain features 902.
In particular, and in accordance with embodiments of the present disclosure, the source/drain features 902 will directly contact the semiconductor channel layers (epitaxial layers 308), each of which has lateral ends (e.g., fin sidewall surfaces) that are substantially free of inner spacer material. As a result, the contact resistance between the source/drain features 902 and the semiconductor channel layers (epitaxial layers 308), including the bottommost semiconductor channel layer, will be improved (reduced). In addition, and because the lateral ends of the semiconductor channel layers are substantially free of inner spacer material, the epitaxial growth quality of the source/drain features 902 will be improved. There is also no additional process cost associated with the various embodiments disclosed herein.
Generally, the semiconductor device 300 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form inter-layer dielectric (ILD) layers, may remove the dummy gate stacks 311, may perform a semiconductor channel release process (e.g., including selective removal of the epitaxial SiGe layers 310), and may form a high-K/metal gate stack, contact openings, contact metal, as well as various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices (e.g., one or more GAA transistors). In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 200, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 200. Further, while the method 200 has been shown and described as including the device 300 having a GAA transistor, it will be understood that other device configurations are possible.
With respect to the description provided herein, disclosed are methods and structures for providing multi-gate devices (e.g., such as a GAA transistors) having improved dummy gate sidewall spacers for inner spacer formation. In some embodiments, fins including an epitaxial stack of layers and one or more dummy gate stacks formed over the epitaxial stack of layers are provided. The dummy gate stacks include one or more sidewall spacers which include a multi-layer sidewall spacer with constituent layers having different etch rates. For example, the sidewall spacers may include a bilayer sidewall spacer where a first layer of the bilayer sidewall spacer is formed over the dummy gates and over the epitaxial stack of layers in source/drain regions of the device. Thereafter, a second layer of the bilayer sidewall spacer is formed over the first layer of the bilayer sidewall spacer. In some cases, the first layer of the bilayer sidewall spacer has a greater etch rate than the second layer of the bilayer sidewall spacer. After forming the first and second layers of the bilayer sidewall spacer, a sidewall spacer etch-back process and source/drain etch process is performed. In some embodiments, and because of the higher etch rate of the first layer of the bilayer sidewall spacer, the sidewall spacer etch-back process and/or the source/drain etch process will etch the first layer of the bilayer sidewall spacer faster than the second layer of the bilayer sidewall spacer. As a result, the trenches formed in the source/drain regions, and which have a trench width defined by a distance between opposing sidewall spacer portions on either side of the trench, will have a funnel shape (e.g., a top width of the trench is greater than a bottom width of the trench). After performing a dummy layer recess process, an inner spacer material is deposited over the device, including along sidewalls of the trenches, within the recesses (e.g., within which inner spacers are defined), and over the opposing sidewall spacer portions on either side of each of the trenches. The deposition of the inner spacer material over the opposing sidewall spacer portions on either side of each of the trenches may effectively reduce the trench width; however, because of the funnel shape of the trenches, the process window for the subsequent inner spacer trim process remains sufficiently large. Thus, when the deposited inner spacer material is subsequently etched-back (trimmed) to form the inner spacers, substantially no inner spacer material remains on lateral ends of the semiconductor channel layers of the epitaxial stack of layers, including the bottommost semiconductor channel layer. As a result, source/drain features that are subsequently formed within the trenches will contact the adjacent inner spacers and the semiconductor channel layers, each of which has lateral ends (e.g., fin sidewall surfaces) that are substantially free of inner spacer material. Therefore, contact resistance between the source/drain features and the semiconductor channel layers will be improved (reduced) to provide enhanced device performance, epitaxial growth quality of the source/drain features will be improved, and there is no extra process cost. Those of skill in the art will readily appreciate that the methods and structures described herein may be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from such other devices without departing from the scope of the present disclosure.
Thus, one of the embodiments of the present disclosure described a method including providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers, and where a gate structure is disposed over the fin. The method further includes depositing a first spacer layer over the gate structure and over the fin in a source/drain region adjacent to the gate structure, where the first spacer layer has a first etch rate. The method further includes depositing a second spacer layer over the first spacer layer, where the second spacer layer has a second etch rate less than the first etch rate. The method further includes removing the plurality of semiconductor channel layers from the source/drain region to form a trench having a funnel shape in the source/drain region. The method further includes after forming the trench having the funnel shape, forming inner spacers along a sidewall surface of the trench, the inner spacers interposing adjacent semiconductor channel layers of the plurality of semiconductor channel layers, where lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.
In another of the embodiments, discussed is a method that includes forming a dummy gate over a fin including plural channel layers. The method further includes forming a bilayer sidewall spacer on a sidewall of the dummy gate and along opposing sidewalls of the fin in a source/drain region adjacent to the dummy gate. The method further includes performing a source/drain etch process to remove the plural channel layers from the source/drain region to form a trench having a width defined by a distance between the opposing bilayer sidewall spacers remaining in the source/drain region, where a top width of the trench is greater than a bottom width of the trench. The method further includes after forming the trench, forming inner spacers along a sidewall surface of the trench and between adjacent channel layers of the plural channel layers, where lateral ends of a bottommost channel layer of the plural channel layers are free of an inner spacer material.
In yet another of the embodiments, discussed is a semiconductor device including a gate structure formed over a fin, where the fin includes a source/drain region adjacent to the gate structure. The semiconductor device further includes a source/drain feature disposed within the source/drain region. The semiconductor device further includes sidewall spacer portions disposed within the source/drain region and on opposing sides of the source/drain feature, where the sidewall spacer portions define a trench having a funnel shape, and where at least a bottom portion of the source/drain feature is disposed within the trench having the funnel shape. In some embodiments, the fin includes a plurality of semiconductor channel layers interposed by a plurality of inner spacers composed of an inner spacer material, where lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims priority to U.S. Prov. App. Ser. No. 63/377,692, filed Sep. 29, 2022, the entire disclosure of which is incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
63377692 | Sep 2022 | US |