Microelectronic elements such as semiconductor chips are typically provided in packages which provide physical and chemical protection for the semiconductor chip or other microelectronic element. Such a package typically includes a package substrate such as a small circuit panel formed from a dielectric material and having electrically conductive terminals thereon. The chip is preferably mounted on the panel and electrically connected to the terminals of the package substrate. Typically, the chip and portions of the substrate are covered by an encapsulant or overmolding, so that only the terminal-bearing outer surface of the substrate remains exposed. Such a package can be readily shipped, stored and handled. The package can be mounted to a larger circuit panel such as a circuit board using standard mounting techniques, most typically surface-mounting techniques. Considerable effort has been devoted in the art to making such packages smaller, so that the packaged chip occupies a smaller area on the circuit board. For example, packages referred to as chip-scale packages occupy an area of the circuit board equal to the area of the chip itself, or only slightly larger than the area of the chip itself. However, even with chip-scale packages, the aggregate area occupied by several packaged chips is greater than or equal to the aggregate area of the individual chips.
It has been proposed to provide “stacked” packages, in which a plurality of individual chip packages or units are mounted one above the other in a common package assembly. This common package assembly can be mounted on an area of the circuit panel which may be equal to or just slightly larger than the area typically required to mount a single package or unit containing a single chip. This stacked package approach conserves space on the circuit panel. Chips or other elements which are functionally related to one another can be provided in a common stacked package assembly. The assembly may incorporate interconnections between these elements. Thus, the main circuit panel to which the assembly is mounted need not include the conductors and other elements required for these interconnections. This, in turn, allows use of a simpler circuit panel and, in some cases, allows the use of a circuit panel having fewer layers of metallic connections, thereby materially reducing the cost of the circuit panel. Moreover, the interconnections within a stacked package assembly often can be made with lower electrical impedance and shorter signal propagation delay times than comparable interconnections between individual units mounted on a circuit panel. This, in turn, can increase the speed of operation of the microelectronic elements within the stacked package as, for example, by allowing the use of higher clock speeds in signal transmissions between these elements.
One form of stacked package assembly which has been proposed heretofore is sometimes referred to as a “ball stack.” A ball stack assembly includes two or more individual units. Each unit incorporates a unit substrate similar to the package substrate of an individual unit, and one or more microelectronic elements mounted to the unit substrate and connected to the terminals on the unit substrate. The individual units are stacked one above the other, with the terminals on each individual unit substrate being connected to terminals on another unit substrate by electrically conductive elements such as solder balls or pins. The terminals of the bottom unit substrate may constitute the terminals of the entire assembly or, alternatively, an additional substrate may be mounted at the bottom of the assembly which may have terminals connected to the terminals of the various unit substrates. Ball stack packages are depicted, for example, in certain preferred embodiments of U.S. Published Patent Applications 2003/0107118 and 2004/0031972, the disclosures of which are hereby incorporated by reference herein.
In another type of stack package assembly, sometimes referred to as a fold stack package, two or more chips or other microelectronic elements are mounted to a single substrate. This single substrate typically has electrical conductors extending along the substrate to connect the microelectronic elements mounted on the substrate with one another. The same substrate also has electrically conductive terminals which are connected to one or both of the microelectronic elements mounted on the substrate. The substrate is folded over on itself so that a microelectronic element on one portion lies over a microelectronic element on another portion, and so that the terminals of the package substrate are exposed at the bottom of the folded package for mounting the assembly to a circuit panel. In certain variants of the fold package, one or more of the microelectronic elements is attached to the substrate after the substrate has been folded to its final configuration. Examples of fold stacks are shown in certain preferred embodiments of U.S. Pat. No. 6,121,676; U.S. patent application Ser. No. 10/077,388; U.S. patent application Ser. No. 10/655,952; U.S. Provisional Patent Application No. 60/403,939; U.S. Provisional Patent Application No. 60/408,664; and U.S. Provisional Patent Application No. 60/408,644, the disclosures of which are hereby incorporated by reference herein. Fold stacks have been used for a variety of purposes, but have found particular application in packaging chips which must communicate with one another as, for example, in forming assemblies incorporating a baseband signal processing chip and radiofrequency power amplifier (“RFPA”) chip in a cellular telephone, so as to form a compact, self-contained assembly.
Despite all of the innovations discussed above, there remains room for improvement. For example, miniaturization of chip package assemblies is desired for use in munitions and munitions testing, among other applications. Chip assemblies for use in such applications must not only be relatively small, but also capable of withstanding relatively high G-forces. In addition to manufacturing miniaturized chip package assemblies, a method must also be devised for testing their reliability for use in such high G-force environments.
Therefore, there exists a need for a miniaturized stacked package assembly capable of withstanding harsh environments, such as high G-force applications. In addition, there is also a need for a testing fixture for testing different stacked package assemblies or individual units of the stacked packages in such a harsh environment.
A first aspect of the present invention is a chip assembly. In accordance with several embodiments, such chip assembly may include a first unit including a first substrate and one or more first electronic components mounted to the first substrate, and a second unit including a second substrate and one or more second electronic components mounted to the second substrate. The first and second units are preferably connected together so that the first electronic components project from the first substrate toward the second substrate and the second electronic components project from the second substrate toward the first substrate, and at least some of the first electronic components extend between at least some of the second electronic components.
In certain embodiments of this first aspect, the chip assembly may further include a connection between the first and second substrates. This connection may be one or more solder balls, one or more pins, or one or more shoulder pins, among others. The shoulder pins may be substantially circular in cross section and may include a wider section flanked by two narrower sections. However, such shoulder pins may be other configurations as well. Preferably, the distance between the first and second substrates of the chip assembly is less than the total combined height of one first electronic component and one second electronic component. An encapsulant or the like may ultimately be disposed between the first and second units, so as to form a solid chip assembly. One or more spacers may also be disposed between the first and second units so as to dictate the overall height between the substrates. In its most preferred form, the chip assembly is suitable for use in high-G force operations.
A second aspect of the present invention is a testing fixture suitable for subjecting chip assemblies or packages to high-G forces. In accordance with several embodiments, such fixture may include a body including at least two detachable portions defining a hollow interior, each having at least one surface suitable for accommodating one or more chip packages. In certain embodiments, the hollow interior may include at least one horizontal surface and at least one vertical surface, and is preferably capable of withstanding high G-forces and of accommodating 48 chip packages. Of course, fixtures capable of accommodating more or less packages are contemplated. In other embodiments, the two detachable portions may be fixed together by fixation means, such as screws, and a plate portion may be disposed between the two detachable portions.
In still further embodiments of the second aspect fixture, the two detachable portions may include a can portion and a base portion, where the portions each include at least one horizontal interior surface and at least one vertical interior surface. The base portion may further include at least one vertical rib, and preferably four vertical ribs defining eight vertical interior surfaces. The two portions may be affixed to one another via fixation means, such as screws.
A more complete appreciation of the subject matter of the present invention and the various advantages thereof can be realized by reference to the following detailed description in which reference is made to the accompanying drawings in which:
In accordance with the present invention, one miniaturized stacked package assembly is illustrated in
As best shown in
The configuration of the various components located on substrates 12 and 14, which allows the aforementioned puzzle-like fit or interconnection of the various components, also allows substrates 12 and 14 to be “stacked” or arranged with their top surfaces facing one another. This necessarily lowers the overall profile of assembly 10, which is beneficial in manufacturing and providing a reduced size assembly. In addition, this type of assembly configuration makes for a very stable and rugged package assembly 10. As best shown in
Once each of the mounts 30 includes sheets of substrate material having components mounted thereto, they may be stacked as mentioned above. More particularly, the top surfaces of the sheets of substrate material are sandwiched together and the various components are situated in their puzzle-like fit. Clearly, components 16 and 18 must be initially placed so as to allow such a cooperation between the two sheets of substrate material and their respective components. With the two sheets situated together, both mounts 30 are subjected to more heat to reflow any solder balls 22 that are disposed between the sheets of substrate material. This causes the two sheets to become connected together. Once this is accomplished, an encapsulant may be applied to the space between the two sheets, thus encapsulating the sheets of substrate and components therebetween. Such encapsulant may be applied by utilizing any suitable encapsulation procedures. For example, encapsulation of substrates and components in frames or mounts 30 is taught in U.S. Pat. Nos. 5,766,987, 6,046,076 and 6,329,224, the disclosures of which are hereby incorporated by reference herein.
Subsequent to the connection of the sheets of material together, and the application of encapsulant to same, solder balls, contacts or the like may be attached to at least one surface of the assembly, to allow for connection of the assemblies to circuit panels, other assemblies (shown in
Other modes of attachment of two substrates in packages according to the present invention may be employed. In fact, any suitable method of attaching two substrates may be utilized to create assemblies, such as the above-described assemblies 10 and 10′.
As is best shown in
With pins 122 connected to substrate 114, substrate 112 is preferably placed over same so that pins 122 form an electrical connection between the printed circuit boards. It is noted that the placement of the substrates with respect to one another may be dictated by the overall length of pins 122, which may be varied depending upon the desired overall thickness of assembly 110. Once the desired placement is achieved, the heretofore unassembled components may be subjected to a reflow process (possibly in addition to the one discussed above) to melt solder 124 disposed on the respective substrates at or near the interconnection with pins 122. This reflow process preferably causes solder 124 to become situated in the manner shown with respect to the connection between the left side pin 122 and substrate shown in
Finally, an encapsulant 126 (best shown in
Ultimately, assembly 110 (best shown in
Although the above described miniaturized stacked package assemblies are suitable for use in extreme environments, such as high G-force applications, it is prudent to test any and all assembly designs for such suitability. This is the case for any type of chip package design, including but not limited to those discussed above.
As shown in
In use, fixture 200 allows for the multi-axis testing of chip packages under high G-forces. Fixture 200 is preferably loaded into and shot from a barrel or the like in order to generate the desired G-forces needed for the particular test. However, other methods of providing G-forces to the fixture are also possible. Of course, fixture 200 is constructed of materials suitable for withstanding a relatively high amount of G-forces. Depending upon which surface the individual chip packages are mounted, different forces may be applied thereto. For example, a chip package mounted to one of the aforementioned horizontal surfaces will experience different forces than a chip package mounted to one of the vertical surfaces, during a single test. Clearly, forces will vary depending upon the particular manner in which fixture 200 is subjected to the G-forces (e.g.—thrown). It is noted that if fixture 200 is shot from a barrel or the like in a similar fashion in subsequent tests, a single chip may be exposed to different forces if it is mounted to different surfaces within the fixture.
Another embodiment testing fixture 300 is shown in
The chip packages are shown attached to the various surfaces of fixture 300 in
It is to be understood that
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/703,175 filed on Jul. 28, 2005 and entitled “STACKABLE ELETRONIC DEVICE ASSEMBLY AND HIGH G-FORCE TEST FIXTURE,” the disclosure of which is hereby incorporated herein by reference. In addition, this application is related to commonly owned United States Utility Provisional Patent Application No. ______ filed on even date herewith, naming William Carlson, Michael Warner, Salvador Tostado, John Riley, III, Ronald Green, Ilyas Mohammed, Michael Nystrom, Rolf Gustus and David Baker and entitled “STACKABLE ELECTRONIC DEVICE ASSEMBLY,” and commonly owned U.S. Provisional Patent Application No. ______ filed on even date herewith, naming Daniel Buckminster, Salvadore Tostado and Apolinar Alvarez, Jr. and entitled “STACKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD,” the disclosures of which are hereby incorporated herein by reference.
Number | Date | Country | |
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60703175 | Jul 2005 | US |