Patent Application
20230178507
This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 21211895.4 filed Dec. 2, 2021, the contents of which are incorporated by reference herein in their entirety.
The present application generally relates to the field of electronics and more specifically to new packaging concept for a semiconductor die
In the current electronics industry, there has been a continuing trend of miniaturization together with the need for cost effective manufacturing methods. In the traditional power packaging using a clip and a lead frame, build up stress are induced during the curing process at joint interfaces such as epoxy in between lead frame and die and solder epoxy between the semiconductor die and clip. These build up stresses are carried throughout the assembly processes. The affected areas become the initiation sites for failures, for example due to solder joint fatigue during temperature cycling. On larger dies, this build-up stress will increase the propensity for nitride passivation/die cracking.
In the current market solution such as those offered by Siptory, the die is attached to a pad forming a joint interface. Subsequently, both the die pad and lead pads are separated and connected through via holes drilled using a laser.
A similar solution is also described in US patent application US 2020/0312799 which claims a Triode packaging method. The end product as shown in the document has a strippable carrier which was covered with another metal layer, that serves as the bond pad, and protective film covering to prevent electroplating on the other areas. Subsequently, the die is “welded” on the bonding pad forming a triode template. A hole is drilled through the mould encapsulant to form aperture openings to contact leads and the die bond pads to form a “closed-loop circuit”. According to this document, to form the “closed loop circuit” (interconnect), through holes were made to the encapsulated die for subsequent electroplating onto the via and the top flat surface of the mould surface.
US patent application US 2002/0106879 also proposes a multilayer structure having a dielectric layer formed over the metal layer and a metal spacer formed on the sidewall of the aperture. However, such a method is implemented at wafer level fabrication.
Thus, there is a need to develop a cost-efficient method of packaging a semiconductor die that results in an end product that is less susceptible to joint stress while eliminating the necessary Bill of Materials, BoM, such as leadframe carrier and die attach epoxy.
A summary of aspects of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth.
In a first aspect of the present disclosure, there is presented a method of packaging a semiconductor die, the method comprising the steps of providing a semiconductor die onto a substrate, wherein the substrate comprises a carrier layer with a release tape situated thereon, wherein a bottom side of the semiconductor die is placed on the thermal release tape, such that placement of the semiconductor die forms a first raised surface and a second surface, application of a photoresist layer on both the semiconductor die and the thermal release tape.
In a further step of the method, openings are formed in the photoresist layer so as to expose the semiconductor die above the first surface and to partially expose, adjacent to the semiconductor die, the thermal release tape above the second surface, and on top thereof a metallization layer is formed such that the metallization layer contacts said exposed semiconductor die above the first surface and said partially exposed thermal release tape adjacent to the semiconductor die.
In a subsequent step, the semiconductor die as well as the thermal release tape with an insulating layer is encapsulated, and thereafter, the substrate along with the thermal release tape is removed so as to reveal said metallization layer adjacent to the semiconductor die, and the bottom side of the semiconductor die with Backside Metallization, BSM.
As a subsequent step the bottom side of the semiconductor die is further metallized to form the packaged semiconductor die.
In the present disclosure, a substrate comprised of a glass or composite carrier and a temperature sensitive tape is used to reconstruct the die. As opposed to the solutions known from the prior art, the dies are not “welded” so there is no die attach compound such as epoxy being used. In the present disclosure, a “step” interconnect is formed over a patterned photoresist through the apertures, with the metallization formed through the die sidewalls covered with resist.
The present disclosure discloses a step metallization structure made by depositing a 3D metallization structure on the exposed die bond pad following the contour of an insulated die sidewall and down to the first surface to form the contact leads. The multilayer metallization structure in prior art is used at wafer-level fabrication. The disclosure enables implementation at assembly packaging level.
After mould encapsulation—through the heat sensitive tape, carrier is separated from the moulded components. To ensure good adhesion of the photoresist to the moulding compound, plasma treatment can be made prior to moulding.
This disclosure relates to a new package concept that eliminates the need for epoxy or epoxy solder used in traditional clip/lead frame-based power packages. This disclosure will overcome this inherent disadvantage in clip-based packages by depositing the interconnect structure directly to the bod pads. The formation of the interconnect done at lower temperature leads to lower stress induced onto the die. The presence of photoresist serves as a buffer layer between the EMC and the die area to further mitigate nitride passivation/die cracking.
An advantage of the present disclosure is that semiconductor dies packaged using a method according to the present disclosure will have smaller footprint as the pads are directly built up/deposited. This disclosure also relates to low-cost packaging as the processes required allows large area processing i.e., panel level processing, PLP. Moreover, the disclosure eliminates several packaging materials which are the main cost runners for Die-Free Package Cost, DFPC, i.e., clip and lead frame, and die attach and clip attach epoxy/solder materials and its corresponding processes such as clip and die attach, solder reflow. This disclosure will use photoresist typically used in PCB manufacturing.
A step interconnect metallization, SIM, layer is formed on the photoresist aperture/openings of die bond pad and contact leads. The interconnect is formed via seed layer deposition and electroplating. The method eliminates the need for epoxy or epoxy solder used in traditional packages. The present disclosure employs depositing the interconnect structure directly to bond pads. This step can be done at a lower temperature leading to lower stress induced in the die.
A new package concept and methods are disclosed that enables the direct formation of 3D metallization contacts connecting the bonding pads through the die sidewall down to the contact leads. The die attachment, moulding/encapsulation, and formation of contacts are made through a temporary/reusable carrier. This novel package avoids the following major bill of materials: clip frame and lead frame, die attach epoxy and clip attach solder epoxy, and their corresponding processes. The package has reduced build-up stress as it eliminates the curing processes needed in the formation of the joint interfaces. This new package concept and processes are compatible for large panel level processing, PLP, further reducing the overall package cost.
According to an example, the method also comprises the steps of exposing the semiconductor die covered with photoresist to Ultra Violet, UV light to form window pads; and depositing seed layer and electroplating a further metallic layer to form the step interconnect. This step is performed to the metallized bottom side as well as the revealed metallization layer adjacent to said semiconductor die. These steps may be performed to cure the additional insulation layer at the bottom of the semiconductor die and to form openings thereon allowing contact pads to be formed at a bottom part of the packaged semiconductor die.
In an exemplary embodiment, the first metallization layer of the step interconnect is formed by seed layer deposition. For example, seed layer deposition is implemented either by laser induced metallization or by shadow mask sputtering. Such methods are well known to the skilled person and thus allow integration of existing methods to achieve the packaged semiconductor die according to the present disclosure.
According to an example, the method further comprises the step of providing a further photoresist layer on the metallized bottom side as well said revealed metallization layer adjacent to the semiconductor die. The further photoresist layer or insulation layer will be beneficial to insulate multiple contacts that need to be formed on the bottom side of the semiconductor die.
At the bottom side, the step of electroplating a Copper, Cu, layer and further metallic layer uses Tin, Sn, as the metal. This may be needed to achieve better adhesion of the bottom contact pad layer to solder when mounted on a PCB. The skilled person understands that electroplating may also be employed to deposit the metallic contacts.
According to an example, the further metallization of the bottom side of said semiconductor die is performed by electroplating.
According to an exemplary embodiment, the first surface of the semiconductor die comprises two separate regions, and wherein the step of formation of openings, forms separate openings corresponding to each of the two separate regions above said semiconductor die as well as adjacent to the semiconductor die, and further wherein during the step of forming a metallization layer, two separate metallization layers are formed wherein each of the two separate metallization layers contacts corresponding openings above the semiconductor die and adjacent to the semiconductor die.
Such structure may be needed to form a packaged three terminal device such a as Metal Oxide Semiconductor Field Effect Transistor, MOSFET, device. In such a case, for example, the source and the gate are located on the two separate regions on the first surface of the semiconductor die and the drain is formed on the bottom part of the semiconductor die. The skilled person understands that the steps of the method presented in the first aspect of the present disclosure may be extended to multiple input multiple output device such as ICs as well.
According to an example, the photoresist layer is applied by spray coating.
According to an exemplary embodiment, the method further comprises the step of cutting said packaged semiconductor die to form individual packaged semiconductor components. Such a step is known as singulation and may be needed to form individual components. A key advantage of the method according to the present disclosure is that it allows large scale, i.e., panel level processing. Such a panel may comprise multiple ICs, or transistor or any other semiconductor devices. Consequently, to obtain an end product cutting the dies may be required to end up with individual component that can be used in a circuit.
In a second aspect of the present disclosure, there is presented a packaged semiconductor die, the semiconductor die having a top surface, a bottom surface and sides, wherein the packaged semiconductor die comprises a photoresist layer on the top surface, the sides and on extending adjacent to the semiconductor die co-planar to the bottom surface; openings in photoresist layer arranged above the top surface and adjacent to the semiconductor die co-planar to the bottom surface; a stepped interconnect metallization layer connecting the semiconductor die at the opening in photoresist layer arranged above the top surface with a metallic contact via the opening adjacent to the semiconductor die co-planar to the bottom surface; a further metallic contact on the bottom surface of the semiconductor die that contacts the semiconductor die.
It is noted that the advantages and definitions associated with the first aspect of the present disclosure being a method of packaging a semiconductor die is also associated with the second aspect of the present disclosure being the packaged semiconductor die.
According to an exemplary embodiment, the packaged semiconductor die is a Metal Oxide Semiconductor Field Effect Transistor, MOSFET, device.
According to an embodiment, the packaged semiconductor die is a Multiple Input Multiple Output, MIMO, device.
The ensuing description above provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
The teachings of the technology provided herein can be applied to other systems, not necessarily the system described below. The elements and acts of the various examples described below can be combined to provide further implementations of the technology. Some alternative implementations of the technology may include not only additional elements to those implementations noted below, but also may include fewer elements.
These and other changes can be made to the technology in light of the following detailed description. While the description describes certain examples of the technology, and describes the best mode contemplated, no matter how detailed the description appears, the technology can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the technology disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the technology should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification, unless the Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the claims.
The present disclosure is described in conjunction with the appended figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
The disclosure in the present application relates to a step interconnect metallization, SIM, package by forming an insulating structure traversing from the die top and its sidewall to the bottom contact leads, Apertures/openings are made on the bond pads of the source and the gate to enable connection to the contact leads. The insulator 15 is formed over the reconstituted die 13 top, sidewall and contact lead areas to form a step insulation 15, 31. Alternative insulator can be used such as dielectrics which can be realized using Plasma Enhanced Chemical Vapor Deposition, PECVD, or Plasma Enhanced Atomic Layer Deposition, PE-ALD. Polyimide can also be used as another alternative insulator and can be deposited by using Vapor deposition Polymerization, VPD.
For the present disclosure, insulation using a photoresist is described. A step metallization is deposited making connection from gate/source pads to contact leads at the bottom of the package as depicted in
While
In
While
In a first step, as shown in
In a subsequent step, as shown in
After placing the mould, through the heat sensitive tape 15, the carrier 11 is separated from the moulded components. As explained previously, this is usually achieved by heating the moulded components to a predefined temperature such that the thermal release tape 15 loses its adhesion with the carrier layer 11. Such a process is known in the technical field.
Reference is now made to
As illustrated in
In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of implementations of the disclosed technology. It will be apparent, however, to one skilled in the art that embodiments of the disclosed technology may be practiced without some of these specific details.
The techniques introduced herein can be embodied as special-purpose hardware (e.g., circuitry), as programmable circuitry appropriately programmed with software and/or firmware, or as a combination of special-purpose and programmable circuitry. Hence, embodiments may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), magneto-optical disks, ROMs, random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. The machine-readable medium includes non-transitory medium, where non-transitory excludes propagation signals. For example, a processor can be connected to a non-transitory computer-readable medium that stores instructions for executing instructions by the processor.
| Number | Date | Country | Kind |
|---|---|---|---|
| 21211895.4 | Dec 2021 | EP | regional |
