Patent Application
20180151461
The present application relates generally to semiconductor chip packaging and more particularly to wafer level packaging of semiconductor chips.
Fan-out Wafer Level Packaging (FO-WLP) is a cost effective option with smaller footprint to meet market demand. However, as more components are placed into a system in package configuration for shorter routing, better thermal dissipation, and faster electrical performance a larger package footprint results. Many different components reside in a single molding structure introducing thermomechanical strain/stress in ball grid array (BGA) joints resulting a packaging reliability concern
The encapsulation of the semiconductor die includes using a substrate on which the die is set facedown and allowing the molding compound to flow around and over the die without coating the active surface. In the resulting semiconductor package, the molding material is thinner over the semiconductor die than the surrounding area. Thus, delamination can occur between the semiconductor die and encapsulating material as a result of the difference between the coefficients of thermal expansion (CTE) of the molding material and the semiconductor die. In addition, warpage during package assembly can occur due to different CTEs of the components.
Moreover, a mismatch of coefficients of thermal expansions (CTEs) can damage the area where the solder bumps connect to the interconnect build-up layer. As the CTE for the die may be substantially different from the CTE of the carrier, this dissimilar rate of expansion causes thermo-mechanical stress on the solder bumps. If the stress is sufficiently large, it may damage the physical connection provided by solder bumps and as a result electrical connectivity may be lost.
Accordingly, there is a need for new chip packaging techniques.
A first embodiment of the present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate and positioning one or more semiconductor dies on a surface of the substrate. The method includes forming a stiffener wall the surface of the substrate wherein the stiffener wall surrounds the one or more semiconductor dies. The method includes forming a compliant material over the one or more semiconductor dies and stiffener wall. The substrate is removed and a redistribution layer is formed on an active side of the one or more semiconductor dies. The redistribution layer includes a plurality of interconnects extending from the active side of the one or more semiconductor dies to a plurality of ball pads on a surface of the redistribution layer. A plurality of solder balls is formed on the ball pads.
A second embodiment of the present disclosure provides wafer level chip package that includes one or more semiconductor dies, each of the one or more semiconductor dies having an inactive side and an active side. A stiffener wall surrounds the one or more semiconductor dies. The stiffener wall extends from the active side to the inactive side. The wafer level chip package includes a compliant layer encasing the one or more semiconductor dies and the stiffener wall. The compliant layer extends from the active side to the inactive side. The wafer level package includes a redistribution layer disposed on the active side of the one or more semiconductor dies. The redistribution layer includes a plurality of interconnects extending from the active side of the one or more semiconductor dies to a plurality of ball pads on a surface of the redistribution layer. A plurality of solder balls is electrically connected to the plurality of ball pads.
A third embodiment of the present disclosure provides a wafer level chip package including aa plurality semiconductor dies, each of the one or more semiconductor dies having an inactive side and an active side. The wafer level chip package includes a stiffener wall encased in a metal frame. The stiffener wall has a plurality of open regions, the open regions surrounding the plurality of semiconductor dies. The stiffener wall extends from the active side to the inactive side. The wafer level chip package includes a compliant layer encasing the plurality of semiconductor dies and the stiffener wall. The compliant layer extends from the active side to the inactive side. The wafer level chip package includes a redistribution layer (RDL) disposed on the active side or the plurality of semiconductor dies. The redistribution layer includes a plurality of interconnects extending from the active side of the plurality of semiconductor dies to a plurality of ball pads on a surface of the redistribution layer. The wafer level chip package includes a plurality of solder balls electrically connected to the plurality of ball pads.
These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
The disclosure will now be described by reference to the accompanying figures. In the figures, various aspects of the structures have been shown and schematically represented in a simplified manner to more clearly describe and illustrate the disclosure. For example, the figures are not intended to be drawn to scale. In addition, the vertical cross-sections of the various aspects of the structures are illustrated as being rectangular in shape. Those skilled in the art will appreciate; however, that with practical structures these aspects will most likely incorporate more tapered features. Moreover, the disclosure is not limited to constructions of any particular shape.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.
Semiconductor devices containing semiconductor dies (also referred to semiconductor chips) are described below. The semiconductor dies may be of different types, may be manufactured by different technologies and may include for example, integrated electrical, electro-optical or electro-mechanical circuits and/or passive devices. The semiconductor dies may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or integrated passive devices. They may include control circuits, microprocessors or microelectromechanical components. Further, they may be configured as power semiconductor chips, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes. In particular, semiconductor dies having a vertical structure may be involved, that is to say that the semiconductor dies may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main faces of the semiconductor dies. Furthermore, the devices described below may include integrated circuits to control the integrated circuits of other semiconductor dies, for example, the integrated circuits of power semiconductor chips. The semiconductor dies need not be manufactured from specific semiconductor material, for example, Si, SiC, SiGe, GaAs, AlGaAs and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as, for example, insulators, plastics or metals.
In a fan-out type package at least some of the external contact pads and/or conductor tracks connecting the semiconductor die or chip to the external contact pads are located laterally outside of the outline of the semiconductor die or at least intersect the outline of the semiconductor die. Thus, in fan-out type packages, a peripherally outer part of the package of the semiconductor die is typically (additionally) used for electrically bonding the package to external applications, such as, e.g., application boards or, in stacked package applications, another package. This outer part of the package encompassing the semiconductor die effectively enlarges the contact area of the package in relation to the footprint of the semiconductor die, thus leading to relaxed constraints in view of package pad size and pitch with regard to later processing, e.g., second level assembly.
Shown in
Stiffener wall 35 is selected from a material including glass fiber, copper based alloys and nickel-iron alloys. Glass fiber has a CTE of from about 2 ppm/K to about 6 ppm/K and a modulus of from about 60 GPa to about 90 GPa, Copper based alloys have a CTE of from about 5 ppm/K to about 17 ppm/K and a modulus of from about 100 GPa to about 150 GPa, Nickel-iron alloys have a CTE of from about 4 ppm/K to about 18 ppm/K and a modulus of from about 100 GPa to about 130 GPa,
Stiffener wall 35 is embedded within compliant material 18 which may be electrically insulating. Stiffener wall 35 and compliant material 18 provide structural support to the fan-out wafer level chip package 30, resulting in enhanced resistance to warpage between the different components. Stiffener wall 35 improves planarity in the final FO-WLP and additionally provides precise solder interconnect joints. Stiffener wall 35 provides better reliability performance on both component and board level.
The modulus of compliant material 18 is from about 5 GPa to about 100 GPa. Compliant material 18 has a coefficient of thermal expansion of less than 30 ppm/K. Compliant material 18 may be a dielectric material and may be made of any appropriate duroplastic, thermoplastic or thermosetting material such as polymeric resins, epoxies and silicones. The compliant material 18 may contain filler materials. After its deposition, the compliant material 18 may be only partially hardened and may be completely hardened after application of energy (e.g., heat, UV light, etc.).
At this stage, stiffener wall 35 can be applied to the substrate 51. In an embodiment, the stiffener wall 35 is shown in
In
After applying the compliant material 18, the substrate 51 including the adhesive tape 50 is debonded from the semiconductor dies 12, compliant material 18 and stiffener wall 35. This is shown in
In
The redistribution layer 14 having the one or more interconnects 19 may generated through depositing photoresist, forming openings in the photoresist and plating or deposition of the interconnects 19 and pads 17 as is known in the art.
Solder balls 16 may be attached to the contact pads 17 as illustrated in
The semiconductor dies 12 may have been manufactured on the same semiconductor wafer, but may alternatively have been manufactured on different semiconductor wafers. Furthermore, the semiconductor dies 12 may be physically identical, but may also contain different integrated circuits and/or represent other components.
The contact pads 17 may represent the external terminals of the semiconductor package. They may be accessible from outside the package and may thus allow electrical contact to be made with the semiconductor chip(s) from outside the package. Furthermore, the contact pads 17 may be thermally conductive and may serve as heat sinks for dissipating the heat generated by the semiconductor chip or chips embedded in the semiconductor package. The contact pads 17 may be composed of any desired electrically conductive material, for example, of a metal, such as copper, aluminum or gold, a metal alloy or an electrically conductive organic material.
The interconnects 19 may be wiring layers to make electrical contact with the semiconductor dies 12 from outside the package and/or to make electrical contact with other semiconductor dies 12 and/or components contained in the package. Interconnects 19 may be manufactured with any desired geometric shape and any desired material composition. Interconnects 19 may, for example, be composed of conductor tracks, but may also be in the form of a layer covering an area. They may be used to electrical couple the contact pads 17 of the package. Any desired metal, for example, aluminum, nickel, palladium, silver, tin, gold or copper, or metal alloys may be used as the material.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
