Patent Application
20250022877
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.
Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100% of what is specified. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10 degrees in some embodiments. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y in some embodiments.
Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10% of what is specified in some embodiments. The term “about” in relation to a numerical value x may mean x±5 or 10% of what is specified in some embodiments.
Embodiments of the disclosure may relate to FinFET structure having fins. The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. However, the fins may be formed using one or more other applicable processes.
Embodiments of the disclosure may relate to the gate all around (GAA) transistor structures. The GAA structure may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In some embodiments, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and added together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrate including II-VI compound semiconductors may also be used.
In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multi-layered structure. For example, the semiconductor substrate 100 includes a silicon-germanium layer formed on a bulk silicon layer.
As shown in
In some embodiments, the semiconductor layers 102a-102c function as sacrificial layers that will be removed in a subsequent process to release the semiconductor layers 104a-104c. The semiconductor layers 104a-104c that are released may function as channel structures of one or more transistors.
In some embodiments, the semiconductor layers 104a-104c that will be used to form channel structures are made of a material that is different than that of the semiconductor layers 102a-102c. In some embodiments, the semiconductor layers 104a-104c are made of or include silicon, germanium, other suitable materials, or a combination thereof. In some embodiments, the semiconductor layers 102a-102c are made of or include silicon germanium. In some other embodiments, the semiconductor layers 104a-104c are made of silicon germanium, and the semiconductor layers 102a-102c are made of silicon germanium with different atomic concentration of germanium than that of the semiconductor layers 104a-104c. Due to the different compositions, different etching selectivity and/or different oxidation rates during subsequent processing may be achieved between the semiconductor layers 102a-102c and the semiconductor layers 104a-104c.
The present disclosure contemplates that the semiconductor layers 102a-102c and the semiconductor layers 104a-104c include any combination of semiconductor materials that can provide desired etching selectivity, desired oxidation rate differences, and/or desired performance characteristics (e.g., materials that maximize current flow).
In some embodiments, the semiconductor layers 102a-102c and 104a-104c are formed using multiple epitaxial growth operations. Each of the semiconductor layers 102a-102c and 104a-104c may be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof.
In some embodiments, the semiconductor layers 102a-102c and 104a-104c are grown in-situ in the same process chamber. In some embodiments, the growth of the semiconductor layers 102a-102c and 104a-104c are alternately and sequentially performed in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken before the epitaxial growth of the semiconductor stack is accomplished.
Afterwards, hard mask elements are formed over the semiconductor stack to assist in a subsequent patterning of the semiconductor stack. Each of the hard mask elements may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be made of different materials. One or more photolithography processes and one or more etching processes are used to pattern the semiconductor stack into multiple fin structures. The fin structures may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes may combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
The semiconductor stack is partially removed to form multiple fin structures (including fin structures 106A and 106B) and multiple trenches 112, as shown in
Afterwards, as shown in
In some embodiments, one or more dielectric layers for forming the dielectric fillings 114 are deposited over the fin structures 106A and 106B and the semiconductor substrate 100. The dielectric layers may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, one or more other suitable materials, or a combination thereof. The liner layer 113 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, one or more other suitable materials, or a combination thereof. The dielectric layers and the liner layer 113 may be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other applicable processes, or a combination thereof.
Afterwards, a planarization process is used to partially remove the dielectric layers and the liner layer 113. The hard mask elements (including the first mask layer 108 and the second mask layer 110) may also function as a stop layer of the planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or a combination thereof.
Afterwards, one or more etching back processes are used to partially remove the dielectric layers and the liner layer 113. As a result, the remaining portion of the dielectric layers forms the dielectric fillings 114 of the isolation structure 115. Upper portions of the fin structures 106A and 106B protrude from the top surface of the isolation structure 115, as shown in
In some embodiments, the etching back process for forming the isolation structure 115 is carefully controlled to ensure that the topmost surface of the isolation structure 115 is positioned at a suitable height level, as shown in
Afterwards, the hard mask elements (including the first mask layer 108 and the second mask layer 110) are removed. Alternatively, in some other embodiments, the hard mask elements are removed or consumed during the planarization process and/or the etching back process that forms the isolation structure 115.
Afterwards, dummy gate stacks 120A and 120B are formed to extend across the fin structures 106A and 106B, as shown in
As shown in
As shown in
In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structures 106A and 106B. The dummy gate dielectric material layer may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof. The dummy gate electrode layer may be deposited using a CVD process. Afterwards, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form the dummy gate stacks 120A and 120B.
In some embodiments, hard mask elements are used to assist in the patterning process for forming the dummy gate stacks 120A and 120B. With the hard mask elements as an etching mask, one or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. As a result, remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate stacks 120A and 120B.
As shown in
The spacer layers may be made of or include silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, silicon oxide, carbon-containing silicon oxide, aluminum oxide, hafnium oxide, one or more other suitable materials, or a combination thereof. In some embodiments, one or more of the spacer layers is/are made of a high-k material. The dielectric constant of the high-k material may be greater than about 7. The spacer layers may be deposited using a CVD process, an ALD process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof.
Afterwards, the spacer layers are partially removed, in accordance with some embodiments. One or more anisotropic etching processes may be used to partially remove the spacer layers. As a result, remaining portions of the spacer layers form the gate spacers 128′. The gate spacers 128′ extend along the sidewalls of the dummy gate stacks 120A and 120B, as shown in
As shown in
One or more etching processes may be used to form the recesses 130. In some embodiments, a dry etching process is used to form the recesses 130. Alternatively, a wet etching process may be used to form the recesses 130. The recesses 130 penetrate into the fin structures 106A and 106B. In some embodiments, the recesses 130 further extend into the semiconductor fins 101A and 101B, as shown in
In some embodiments, the recesses 130 have substantially vertical sidewalls. In these cases, due to the profile of the recesses 130, an upper semiconductor layer (such as the semiconductor layer 104c) is substantially as wide as a lower semiconductor layer (such as the semiconductor layer 104b).
However, embodiments of the disclosure have many variations. In some other embodiments, each of the recesses 130 has slanted sidewalls. Upper portions of the recesses 130 are larger (or wider) than lower portions of the recesses 130. In these cases, due to the profile of the recesses 130, an upper semiconductor layer (such as the semiconductor layer 104c) is shorter than a lower semiconductor layer (such as the semiconductor layer 104b).
Afterwards, as shown in
As shown in
In some embodiments, an insulating layer is deposited over the structure shown in
Afterwards, one or more etching processes are used to partially remove the insulating layer, in accordance with some embodiments. The portions of the insulating layer outside of the recesses 132 may be removed. The remaining portions of the insulating layer form the inner spacers 136, as shown in
In some embodiments, after the etching process for forming the inner spacers 136, portions of the semiconductor fins 101A and 101B originally covered by the insulating layer are exposed by the recesses 130, as shown in
As shown in
The semiconductor isolation structures 137 may be made of or include silicon, silicon germanium, another suitable material, or a combination thereof. The semiconductor isolation structures 137 may be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof. In some embodiments, the formation of the semiconductor isolation structures 137 involve one or more etching processes that are used to fine-tune the profiles of the semiconductor isolation structures 137. In some embodiments, the semiconductor isolation structures 137 on the semiconductor fins 101A and 101B are formed simultaneously.
In some embodiments, the semiconductor isolation structures 137 are formed to have substantially planar top surfaces, as shown in
As shown in
In some embodiments, a mask element layer is formed over the structure shown in
Afterwards, epitaxial structures 138N are formed on the side surfaces of semiconductor layers 104a-104c and the semiconductor fin 101B that are not covered by the mask element 302, in accordance with some embodiments. In some embodiments, the epitaxial structures 138N fill the recesses 130 that are not covered by the mask element 302, as shown in
In some embodiments, the epitaxial structures 138N connect to some of the semiconductor layers 104a-104c. Some of the semiconductor layers 104a-104c are sandwiched between the epitaxial structures 138N. In some embodiments, the epitaxial structures 138N are n-type doped epitaxial structures. The epitaxial structures 138N may include epitaxially grown silicon, epitaxially grown silicon germanium (SiGe), or another suitable epitaxially grown semiconductor material.
In some embodiments, the epitaxial structures 138N are formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof. In some embodiments, the formation of the epitaxial structures 138N involves one or more etching processes that are used to fine-tune the shapes of the epitaxial structures 138N.
In some embodiments, the epitaxial structures 138N are doped with one or more suitable n-type dopants. For example, the epitaxial structures 138N are Si source/drain features that are doped with phosphor (P), antimony (Sb), arsenic (As) or another suitable dopant. In some embodiments, each of the epitaxial structures 138N has a first region and a second region over the first region. The second region may have a greater dopant concentration than that of the first region.
In some embodiments, the epitaxial structures 138N are doped in-situ during their epitaxial growth. The initial reaction gas mixture for forming the epitaxial structures 138N contains dopants. In some other embodiments, the epitaxial structures 138N are not doped during the growth of the epitaxial structures 138N. Instead, after the formation of the epitaxial structures 138N, the epitaxial structures 138N are doped in a subsequent process. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or a combination thereof. In some embodiments, the epitaxial structures 138N are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.
As shown in
As shown in
Afterwards, the semiconductor layers 104a-104c of the fin structure 106A are recessed, as shown in
In some embodiments, recesses 306 are formed due to the lateral etching of the semiconductor layers 104a-104c, as shown in
As shown in
In some embodiments, the semiconductor isolation structures 137 formed on the semiconductor fin 101A are also partially removed during the lateral etching of the semiconductor layers 104a-104c. In some embodiments, the top surfaces of the semiconductor isolation structures 137 on the semiconductor fin 101A are substantially level with the top surface of the semiconductor fin 101A, as shown in
As shown in
Each of the gate spacers 128′ has a wider portion with a width W3 and a narrower portion (i.e., the trimmed gate spacer 128″) with a width W4, as shown in
As shown in
As shown in
In some embodiments, the isolation semiconductor structures 137 over the semiconductor fin 101A are spaced apart from the trimmed inner spacers 136′, as shown in
As shown in
In some embodiments, the epitaxial structures 138P connect to some of the semiconductor layers 104a-104c. Some of the semiconductor layers 104a-104c are sandwiched between the epitaxial structures 138P. In some embodiments, the epitaxial structures 138P are p-type epitaxial structures. The epitaxial structures 138P may include epitaxially grown silicon germanium, epitaxially grown silicon, or another suitable epitaxially grown semiconductor material.
In some embodiments, the epitaxial structures 138P are formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof. In some embodiments, the formation of the epitaxial structures 138P involves one or more etching processes that are used to fine-tune the shapes of the epitaxial structures 138P.
In some embodiments, the epitaxial structures 138P are doped with one or more suitable p-type dopants. For example, the epitaxial structures 138P are SiGe source/drain features or Si source/drain features that are doped with boron (B), gallium (Ga), indium (In), or another suitable dopant. In some embodiments, each of the epitaxial structures 138P has a first region and a second region over the first region. The second region may have a greater dopant concentration than that of the first region.
In some embodiments, the epitaxial structures 138P are doped in-situ during their epitaxial growth. The initial reaction gas mixture for forming the epitaxial structures 138P contains dopants. In some other embodiments, the epitaxial structures 138P are not doped during the growth of the epitaxial structures 138P. Instead, after the formation of the epitaxial structures 138P, the epitaxial structures 138P are doped in a subsequent process. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or a combination thereof. In some embodiments, the epitaxial structures 138P are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.
In some embodiments illustrated in
Afterwards, the mask element 304 is removed, as shown in
In some embodiments, each of the epitaxial structures 138P has multiple protruding portions extending towards the semiconductor layers 104a-104c, as shown in
In some embodiments, due to the trimmed inner spacers 136′ and the trimmed gate spacers 128″, each of the protruding portions P is has a narrow width even if the semiconductor layers 104a-104c are laterally recessed. The resistance of the protruding portions P is thus kept at an acceptable level. The performance and reliability of the semiconductor device structure are ensured.
As shown in
In some embodiments, an etch stop material layer and a dielectric material layer are sequentially deposited. The etch stop material layer may be deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. The dielectric material layer may be deposited using an FCVD process, a CVD process, an ALD process, another applicable process, or a combination thereof.
Afterwards, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. As a result, the remaining portions of the etch stop material layer and the dielectric material layer respectively form the contact etch stop layer 139 and the dielectric layer 140, as shown in
Afterwards, as shown in
As shown in
Due to high etching selectivity, the semiconductor layers 104a-104c are slightly (or substantially not) etched. The remaining portions of the semiconductor layers 104a-104c form multiple semiconductor nanostructures 104a′-104c′. The semiconductor nanostructures 104a′-104c′ are constructed by or made up of the remaining portions of the semiconductor layers 104a-104c. The semiconductor nanostructures 104a′-104c′ suspended over the semiconductor fins 101A and 101B may function as channel structures of transistors.
In some other embodiments, the etchant used for removing the semiconductor layers 102a-102c also slightly removes the semiconductor layers 104a-104c that form the semiconductor nanostructures 104a′-104c′. As a result, the obtained semiconductor nanostructures 104a′-104c′ become thinner after the removal of the semiconductor layers 102a-102c. In some embodiments, each of the semiconductor nanostructures 104a′-104c′ is thinner than the edge portions since the edge portions are surrounded by other elements and thus are prevented from being reached and etched by the etchant.
After the removal of the semiconductor layers 102a-102c (which function as sacrificial layers), the recesses 144 are formed. The recesses 144 connect to the trench 142 and surround each of the semiconductor nanostructures 104a′-104c′. As shown in
During the removal of the semiconductor layers 102a-102c (which function as sacrificial layers), the inner spacers 136 and the trimmed inner spacers 136′ protect the epitaxial structures 138N and 138P from being etched or damaged. The quality and reliability of the semiconductor device structure are improved.
As shown in
Each of the metal gate stacks 156A and 156B includes multiple metal gate stack layers. Each of the metal gate stacks 156A and 156B may include a gate dielectric layer 150 and metal gate electrodes 152P and 152N. Each of the metal gate electrodes 152P and 152N may include a work function layer. Each of the metal gate electrodes 152P and 152N may further include a conductive filling. In some embodiments, the formation of the metal gate stacks 156A and 156B involves the deposition of multiple metal gate stack layers over the dielectric layer 140 to fill the trenches 142 and the recesses 144. The metal gate stack layers extend into the recesses 144 to wrap around each of the semiconductor nanostructures 104a′-104c′.
In some embodiments, the gate dielectric layer 150 is made of or includes a dielectric material with high dielectric constant (high-K). The gate dielectric layer 150 may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-K materials, or a combination thereof. The gate dielectric layer 150 may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof.
In some embodiments, before the formation of the gate dielectric layer 150, an interfacial layers are formed on the surfaces of the semiconductor nanostructures 104a′-104c′. The interfacial layers are very thin and are made of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layers are formed by applying an oxidizing agent on the surfaces of the semiconductor nanostructures 104a′-104c′. For example, a hydrogen peroxide-containing liquid may be applied or provided on the surfaces of the semiconductor nanostructures 104a′-104c′ so as to form the interfacial layers.
The work function layer of the metal gate electrodes 152P and 152N may be used to provide the desired work function for transistors to enhance device performance including improved threshold voltage. The metal gate electrodes 152P and 152N may have different work function layers. In some embodiments, the work function layer surrounding the semiconductor nanostructures 104a′-104c′ of the fin structure 106A is used for forming a PMOS device. In these cases, the work function layer of the metal gate electrode 152P is a p-type work function layer. The p-type work function layer is capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV.
The p-type work function layer may include metal, metal carbide, metal nitride, other suitable materials, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, one or more other suitable materials, or a combination thereof.
In some embodiments, the work function layer surrounding the semiconductor nanostructures 104a′-104c′ of the fin structure 106B is used for forming an NMOS device. The work function layer of the metal gate electrode 152N is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV.
The n-type work function layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.
The work function layer may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combinations thereof. The thickness and/or the compositions of the work function layer may be fine-tuned to adjust the work function level.
The work function layer may be deposited over the gate dielectric layer 150 using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof. In some embodiments, the formation of the work function layer involves one or more patterning processes. As a result, the n-type work function layer and the p-type work function layer are selectively formed over different regions.
In some embodiments, a barrier layer is formed before the work function layer to interface the gate dielectric layer 150 with the subsequently formed work function layer. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.
In some embodiments, the conductive fillings of the metal gate electrodes 152N and 152P are made of or include a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. A conductive layer used for forming the conductive filling may be deposited over the work function layer using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin coating process, one or more other applicable processes, or a combination thereof.
In some embodiments, a blocking layer is formed over the work function layer before the formation of the conductive layer used for forming the conductive filling. The blocking layer may be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer. The blocking layer may be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The blocking layer may be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.
Afterwards, a planarization process is performed to remove the portions of the metal gate stack layers outside of the trenches 142, in accordance with some embodiments. As a result, the remaining portions of the metal gate stack layers form the metal gate stacks 156A and 156B, as shown in
In some embodiments, the conductive filling does not extend into the recesses 144 since the recesses 144 are small and have been filled with other elements such as the gate dielectric layer 150 and the work function layer. However, embodiments of the disclosure are not limited thereto. In some other embodiments, a portion of the conductive filling extends into the recesses 144.
In some embodiments, the left portion of
As mentioned above, in some embodiments, the width ratio W4/W3 is within a range from about 30% to about 90%. In some cases, if the width ratio W4/W3 is higher than about 90%, the trimmed gate spacers 128″ may be too thick. The uppermost protruding portions P of the epitaxial structures 138P may be too wide and thus have high resistance. In some other cases, if the width ratio W4/W3 is lower than about 30%, the trimmed gate spacers 128″ may be too thin. The trimmed gate spacers 128″ that are too thin may not be able to sustain the subsequent formation processes and/or may induce high capacitance.
As mentioned above, in some embodiments, the width ratio W6/W5 is within a range from about 30% to about 90%. In some cases, if the width ratio W6/W5 is higher than about 90%, the trimmed inner spacers 136′ may be too thick. The protruding portions P of the epitaxial structures 138P may be too wide and thus have high resistance. In some other cases, if the width ratio W6/W5 is lower than about 30%, the trimmed inner spacers 136′ may be too thin. The trimmed inner spacers 136′ that are too thin may not be able to sustain the subsequent formation processes and/or may induce high capacitance.
As shown in
Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the epitaxial structures 138P are formed before the epitaxial structures 138N. In some embodiments, the trimming of the gate spacers 128′ and/or the inner spacers 136 are performed before the formation of the epitaxial structures 138P and 138N.
In some embodiments, the trimming of the gate spacers is performed before the trimming of the inner spacers. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the trimming of the gate spacers and the trimming of the inner spacers are performed simultaneously.
Afterwards, an etching process is used to trim the exposed gate spacers and the exposed inner spacers, as shown in
Afterwards, the processes that are the same as or similar to those illustrated in
In some embodiments, the trimming of the gate spacers is performed before the trimming of the inner spacers. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the trimming of the inner spacers is performed before the trimming of the gate spacers.
As shown in
As shown in
Afterwards, the processes that are the same as or similar to those illustrated in
In some embodiments, some of the gate spacers and the inner spacers are further trimmed. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the gate spacers are not further trimmed, and some of the inner spacers are further trimmed.
In some embodiments, some of the gate spacers and the inner spacers are further trimmed. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the inner spacers are not further trimmed, and portions of the gate spacers are further trimmed.
Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, bottom isolation structures are formed between the epitaxial structures and the semiconductor isolation structures. The bottom isolation structures may be used to reduce or prevent leakage current from the epitaxial structures.
In some embodiments, the bottom isolation structures 802 are made of or include a dielectric material. The dielectric material may include silicon oxide, silicon nitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, carbon-containing silicon oxide, aluminum oxide, hafnium oxide, another suitable material, or a combination thereof. The formation of the bottom isolation structures 802 may involve one or more deposition processes and one or more patterning processes.
Afterwards, the processes that are the same as or similar to those illustrated in
Many variations and/or modifications can be made to embodiments of the disclosure.
In some embodiments, the bottom isolation structures 802 and 902 are made of or include a dielectric material. The dielectric material may include silicon oxide, silicon nitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, carbon-containing silicon oxide, aluminum oxide, hafnium oxide, another suitable material, or a combination thereof. The formation of the bottom isolation structures 802 and 902 may involve one or more deposition processes and one or more patterning processes.
Afterwards, the processes that are the same as or similar to those illustrated in
In some embodiments, the semiconductor nanostructures 104a′-104c′ between the epitaxial structures 138N are substantially as thick as the semiconductor nanostructures between the epitaxial structures 138P. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the semiconductor nanostructures 104a′-104c′ between the epitaxial structures 138N are thinner than the semiconductor nanostructures between the epitaxial structures 138P.
In some embodiments, an over etching process is used to partially remove the semiconductor layers 104a-104c between the epitaxial structures 138N while the semiconductor layers 104a-104c between the epitaxial structures 138P are covered by a mask element. As a result, the semiconductor nanostructures 1004a′-1004c′ that are thinner are formed, as shown in
Afterwards, the processes that are the same as or similar to those illustrated in
Embodiments of the disclosure are not limited thereto. In some other embodiments, the removal of the semiconductor layers 102a-102c of the fin structure 106A and the removal of the semiconductor layers 102a-102c of the fin structure 106B are performed simultaneously. Some n-type dopants from the epitaxial structures 138N may diffuse into the semiconductor layers 102a-102c and/or 104a-104c of the fin structure 106B. As a result, the semiconductor layers 102a-102c and/or 104a-104c of the fin structure 106B may be etched at a faster rate than the semiconductor layers 102a-102c and/or 104a-104c of the fin structure 106A. As a result, the semiconductor nanostructures 1004a′-1004c′ that are thinner than the semiconductor nanostructures 104a′-104c′ are formed.
Many variations and/or modifications can be made to embodiments of the disclosure.
In some embodiments, the portion of the metal gate stack 156A or 156B over the fin structure 106A is substantially as wide as the portion of the metal gate stack 156A or 156B over the fin structure 106B. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the portion of the metal gate stack 156A or 156B over the fin structure 106A and the portion of the metal gate stack 156A or 156B over the fin structure 106B have different widths.
Afterwards, the processes that are the same as or similar to those illustrated in
However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure.
In some embodiments, an upper semiconductor nanostructure is substantially as wide as a lower semiconductor nanostructure. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments. In some other embodiments, an upper semiconductor nanostructure and a lower semiconductor nanostructure have different widths.
Afterwards, the processes that are the same as or similar to those illustrated in
In some embodiments, an upper semiconductor nanostructure is substantially as thick as a lower semiconductor nanostructure. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments. In some other embodiments, an upper semiconductor nanostructure and a lower semiconductor nanostructure have different thicknesses.
In some embodiments, because the semiconductor nanostructures 104c′ has the thinner thickness TA, the short channel effect control of the top sheet (i.e., the semiconductor nanostructures 104c′) is improved. In some embodiments, the portion of the epitaxial structure 138N (or 138P) adjacent to the semiconductor nanostructures 104c′ has a higher dopant concentration than the portion of the epitaxial structure 138N (or 138P) adjacent to the semiconductor nanostructures 104b′ or 104a′.
Embodiments of the disclosure form a semiconductor device structure with a PMOS device and an NMOS device. The PMOS device and the NMOS device are gate-all-around (GAA) transistor structures with gate spacers and inner spacers separating the epitaxial structures from the metal gate stacks. Some of the inner spacers and/or the gate spacers are trimmed according to the characteristics of the PMOS device and/or the NMOS device. The gate spacers and/or inner spacers of the PMOS device and the NMOS device thus have different widths. The performance and reliability of each of the PMOS device and the NMOS device may be improved.
In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.
In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the first fin structure and the second fin structure to form multiple recesses exposing side surfaces of the semiconductor layers and the sacrificial layers. The method further includes forming multiple inner spacers covering the side surfaces of the sacrificial layers of the first fin structure and the second fin structure and forming n-type doped epitaxial structures on the side surfaces of the semiconductor layers of the first fin structure. In addition, the method includes recessing the semiconductor layers of the second fin structure after the n-type doped epitaxial structures are formed and trimming the inner spacers covering the side surfaces of the sacrificial layers of the second fin structure. The method also includes forming p-type doped epitaxial structures on the side surfaces of the semiconductor layers of the second fin structure.
In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures and multiple second semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure, and each of the first semiconductor nanostructures is between the first epitaxial structure and the second epitaxial structure. In addition, the semiconductor device structure includes a third epitaxial structure and a fourth epitaxial structure, and each of the second semiconductor nanostructures is between the third epitaxial structure and the fourth epitaxial structure. The semiconductor device structure includes multiple first inner spacers, and each of the first inner spacers is between the gate stack and the first epitaxial structure. The semiconductor device structure also includes multiple second inner spacers. Each of the second inner spacers is between the gate stack and the third epitaxial structure, and each of the first inner spacers is wider than each of the second inner spacers.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
