Not Applicable.
The disclosure relates generally to electromagnetic sensing and sensors and also relates to low energy electromagnetic input conditions as well as low energy electromagnetic throughput conditions. The disclosure relates more particularly, but not necessarily entirely, to optimizing the pixel array area and using a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates and associated systems, methods and features, which may also include maximizing pixel array size/die size (area optimization).
There has been a popularization of the number of electronic devices that utilize and include the use of imaging/camera technology in general. For example, smartphones, tablet computers, and other handheld computing devices all include and utilize imaging/camera technology. The use of imaging/camera technology is not limited to the consumer electronics industry. Various other fields of use also utilize imaging/camera technology, including various industrial applications, medical applications, home and business security/surveillance applications, and many more. In fact, imaging/camera technology is utilized in nearly all industries.
Due to such popularization, the demand for smaller and smaller high definition imaging sensors has increased dramatically in the marketplace. The device, system and methods of the disclosure may be utilized in any imaging application where size and form factor are considerations. Several different types of imaging sensors may be utilized by the disclosure, such as a charged-couple device (CCD), or a complementary metal-oxide semiconductor (CMOS), or any other image sensor currently known or that may become known in the future.
CMOS image sensors typically mount the entire pixel array and related circuitry, such as analog-digital converters and/or amplifiers, on a single chip. Because of the physical constraints of the chip size itself and the physical space occupied by related circuitry involved in a conventional CMOS image sensor, the area that the pixel array may occupy on the chip is often limited. Thus, even if the pixel array were maximized on a substrate that also contains the related circuitry, the pixel array is physically limited in area due to the amount of physical area and space that the related circuitry for signal processing and other functions occupies on the chip.
Further, the application or field of use in which the CMOS image sensor may be used often requires the CMOS image sensor to be limited to a certain size also limiting the physical area in which the pixel array may occupy. The size limitations of a CMOS image sensor often require trade-offs between image quality and other important functions, such as signal processing, due to the number of considerations that must be accounted for in the design and manufacture of a CMOS image sensor. Thus, for example, increasing the pixel array area may come with a trade-off in other areas, such as A/D conversion or other signal processing functions, because of the decreased area in which the related circuitry may occupy.
The disclosure optimizes and maximizes the pixel array without sacrificing quality of the signal processing by optimizing and maximizing the pixel array on a first substrate and stacking related circuitry on subsequent substrates. The disclosure utilizes advancements in back-side illumination and other areas to take advantage of optimizing the area of the pixel array on a substrate. The stacking scheme and structure allow highly functional, large-scale circuits to be utilized while maintaining a small chip size.
The features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by the practice of the disclosure without undue experimentation. The features and advantages of the disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.
The features and advantages of the disclosure will become apparent from a consideration of the subsequent detailed description presented in connection with the accompanying drawings in which:
For the purposes of promoting an understanding of the principles in accordance with the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Any alterations and further modifications of the inventive features illustrated herein, and any additional applications of the principles of the disclosure as illustrated herein, which would normally occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the disclosure claimed.
Before the devices, systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are disclosed and described, it is to be understood that this disclosure is not limited to the particular structures, configurations, process steps, and materials disclosed herein as such structures, configurations, process steps, and materials may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting since the scope of the disclosure will be limited only by the appended claims and equivalents thereof.
It must be noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.
In describing and claiming the subject matter of the disclosure, the following terminology will be used in accordance with the definitions set out below.
As used herein, the terms “comprising,” “including,” “containing,” “characterized by,” and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps.
As used herein, the phrase “consisting of” and grammatical equivalents thereof exclude any element or step not specified in the claim.
As used herein, the phrase “consisting essentially of” and grammatical equivalents thereof limit the scope of a claim to the specified materials or steps and those that do not materially affect the basic and novel characteristic or characteristics of the claimed disclosure.
As used herein, the term “proximal” shall refer broadly to the concept of a portion nearest an origin.
As used herein, the term “distal” shall generally refer to the opposite of proximal, and thus to the concept of a portion farther from an origin, or a furthest portion, depending upon the context.
Digital imaging, whether still or movie, has many constraints placed upon it with regard to the devices used to record the image data. As discussed herein, an imaging sensor may include a pixel array and supporting circuits that are disposed on at least one substrate. Devices usually have practical and optimal constraints on the form factor of the imaging sensor depending upon the application. Often it is not the pixel array that is the only consideration for fitment, but it is the supporting circuitry that needs to be accommodated. The supporting circuits may be, but are not necessarily limited to, analog to digital converters, power circuits, power harvesters, amplifier circuits, dedicated signal processors and filters, serializers for transmission preparation, etc. In addition to circuits, physical property elements may be required, such as light filters and lenses. Each of the pixels must be read from the pixel array and have the data processed by the supporting circuits. With the increase in the number of pixels in an array, more data must be handled. In regard to movie data the sensor must dump its data and be ready to operate again in short order.
Although size is an issue as stated above, pixel count numbers continue to climb industry wide no matter the specific application, and often eclipse the mediums that are used to actually view the images after they have been recorded, such as a computer monitor or television. However, it should be understood that all pixels are not created equal. In the example above, a scope configuration may be used in a limited light application.
As pixel counts continue to grow in a given space pixel pitch decreases thereby requiring greater precision for interconnect electrical contact. Accordingly, the cost of image sensor production can increase as the need for greater precision in data handling is required for the increased pixel pitch. Current technologies may be used to achieve image sensors with increased capabilities but at increased cost as yields fall during manufacture.
The above-identified issues describe the current state of the art relative to a few needs within the industry. What is needed is an image sensor having adequate resolution by way of pixel count, a vertical architecture and form factor, and as large as possible pixel size, all while constrained in a limited space. The disclosure contemplates and will discuss embodiments and methods of design that address these and potentially other issues by optimizing the size of the pixel array on a substrate/chip and remotely locating supporting circuits in a generally vertical configuration on one or more supporting substrates/chips.
High performance image sensors that use on-chip analog to digital convertors (ADC), on-chip digital and analog algorithms, on-chip complex timings, and on-chip complex analog functions provide high quality images because of the following reasons (the list below is not a complete list, but is given merely for exemplary purposes):
No pick-up noise due to long off-chip analog data lines (if no on-chip ADC, then analog signals need to be sent off-chip);
Lower temporal noise because digital conversion is carried out early in the data path (no extra amplifier, buffer that will add extra noise);
Local timing optimization using complex on-chip timing generator. Because of pad count limitation, only simple timing can be performed using external system;
Lower noise generated by I/O. On-chip systems allow for reduced pad count; and
Faster operation can be achieved (more serial on-chip operation, reduced stray capacitances and resistances). With larger and larger arrays, the need to read and processes the data created therein is paramount.
The disclosure also contemplates an image sensor that might otherwise be manufactured with its pixel array and supporting circuitry on a single, monolithic substrate/chip and separating the pixel array from all or a majority of the supporting circuitry. The disclosure may use at least two substrates/chips, which will be stacked together using three-dimensional stacking technology. The first of the two substrates/chips may be processed using an image CMOS process. The first substrate/chip may be comprised either of a pixel array exclusively or a pixel array surrounded by limited circuitry. The second or subsequent substrate/chip may be processed using any process, and does not have to be from an image CMOS process. The second substrate/chip may be, but is not limited to, a highly dense digital process in order to integrate a variety and number of functions in a very limited space or area on the substrate/chip, or a mixed-mode or analog process in order to integrate for example precise analog functions, or a RF process in order to implement wireless capability, or MEMS (Micro-Electro-Mechanical Systems) in order to integrate MEMS devices. The image CMOS substrate/chip may be stacked with the second or subsequent substrate/chip using any three-dimensional technique. The second substrate/chip may support most, or a majority, of the circuitry that would have otherwise been implemented in the first image CMOS chip (if implemented on a monolithic substrate/chip) as peripheral circuits and therefore have increased the overall system area while keeping the pixel array size constant and optimized to the fullest extent possible. The electrical connection between the two substrates/chips may be done through interconnects, which may be wirebonds, μbump and/or TSV (Through Silicon Via).
Referring now to
In an embodiment, a pixel array 450 may cover a majority of the first surface 451 of a first substrate 452. In such an embodiment the pixel array 450 may be situated or located on any portion of said first surface 451. The remaining space on the first surface 451 may be used for secondary circuit placement if desired. Situations may arise where a secondary circuit may be sized such that central placement of the pixel array is not practical.
During use, data created by individual pixels on the pixel array must be processed by supporting circuitry, as such each pixel must be electronically connected to supporting circuits. Ideally each pixel could be read simultaneously thereby creating a global shutter. Referring now to
By way of example, it will be appreciated that pixel pitch may be about 5 μm and pixel column may be any length, for example between about 2 mm and about 15 mm long. It should be noted that bump pitch is a function of pixel pitch, such that the pixel pitch will be determinative of an ideal bump pitch. For example, assuming there is a desired bump pitch of approximately 100 μm, placing a first interconnect or bump 1824 may then be accomplished by starting at the top of the first column and shifting down the next column interconnect or bump by 100 μm. All other bumps are similarly positioned until the interconnect or bump in the 20th column of the line will be located at the bottom of the pixel column. At that point, the interconnect or bump 1824 in the 21st column may again be placed at the top of the pixel column 1828. This same pattern may then be repeated until the end of the pixel array 1810. Horizontally, the interconnects or bumps 1824 may be separated by 20 columns×5 μm=100 μm. In this example, all bumps will then be separated by more than 100 μm, even though the pixel pitch is about 5 μm. Redundancy can then be introduced in the pixel column for yield purposes. For example, bumps in all columns can be doubled (i.e., the two read buses are attached by 2 interconnects or bumps). This technique would significantly increase stacking yield and lower the cost of the overall process.
As can be seen in
Likewise, greater interconnect gains may be made with area based spacing rather than column-by-column based connectivity (see figures illustrating a pixel column aspect ratio of 6/1 and circuit column aspect ratio of 6/1 and 3/2, or a pixel column aspect ratio of 8/1 and circuit column aspect ratio of 2/4). This can be accomplished with the addition of more bus structures or use of direct reading to a subsequent substrate. In either configuration, the interconnect pitch may be described thusly:
Interconnect_Pitch=√{square root over ((N*PixelPitchx)2+(M*PixelPitchy)2)}
where N is the number of pixels between two adjacent interconnects in the X-direction and M is the number of pixels between two adjacent interconnects in the Y-direction. It will be appreciated that each of the plurality of interconnects may be a bump where the bump to bump distance may be greater than two pixels in width, or greater than four pixels in width, or greater than eight pixels in width.
In many applications, the N×Pixel Pitch in the X direction will be equal to M×Pixel Pitch in the Y direction. As illustrated in
Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, the interconnect range in order to read the corresponding pixel column is 1 pixel wide and 64 pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
It should be noted that the exemplary aspect ratio of the support circuit area in
Additionally, it should be noted that various read bus architectures may be utilized depending on the desired application. As discussed above, larger dedicated support circuits may be employed to process the data read through each interconnect 1824. The staggering of the position of each interconnect/bump 1824 may also provide even greater space for support circuits relative to each area or group of pixels within the pixel array 1810.
It should also be noted that many optimum staggering configurations have been found for the same base sensor with different support circuit aspect ratios as illustrated in
In
In
Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and sixteen pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
In
Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and eight pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
In
Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and four pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.
It should also be noted that the pattern of the association of the support circuit to the pixel column may be different than that of
For example, as illustrated in
Referring now to
Each of the pixel columns 1828 in the pixel array 1810 may be divided into sub-columns. The sub-columns may be defined as a plurality of pixels within a column that is less than the entire column of pixels and that are electrically connected to a pixel sub-column bus. Thus, there may be a plurality of pixel sub-columns per pixel column 1828. Each of the sub-columns may have a contact pad and/or an interconnect illustrated as 51, 52, 53 and 54 to electrically connect each of the sub-column buses on the first substrate to an associated or corresponding circuit column bus located on the supporting substrate.
At least one pixel column bus may be used to provide an electrical connection for every pixel in the column 1828. The column 1828 may be divided into a plurality of sub-columns, where at least one pixel sub-column bus is present per pixel sub-column. The sub-column buses may be differentiated by dividers 62, 63, 64, which dividers may be a physical space or gap or other device for electrically isolating the pixel sub-column and/or sub-column bus from another sub-column and/or sub-column bus. During use, the data from the pixels may be read in a rolling type shutter manner, which is substantially simultaneous from each row of pixels in each of the sub-columns (illustrated as four sub-columns in
In other embodiments, the column may be divided into any number of sub-columns, with each division of the column (e.g., addition of a sub-column) approximating a global shutter functionality. As can be seen in the figure, the contact pads and interconnect locations can be staggered in each of the columns. As illustrated, the interconnects from the column labeled “A” from those in the column labeled “B.” Other iterations of sub-columns and interconnect staggering are possible for N number of columns.
Referring now to
As illustrated in
The figures also show one read bus 1230 per pixel sub-column 1252 and one read bus 1240 per circuit column 1256. In this embodiment, the associated circuitry 1270 in a circuit column 1256 is one pixel wide and six pixels long, but it will be appreciated that any circuit column aspect ratio may be utilized by the disclosure. As can be seen in
As noted herein above, each pixel sub-column 1252 may be electrically associated or connected to one pixel sub-column bus 1230, and each circuit column 1256 may be electrically associated or connected to one circuit column bus 1240.
a illustrate an alternative embodiment in which the pixel column has been divided into a plurality of sub-columns, each having their own bus. However, the sub-columns are illustrated as being connected by their individual buses to a single circuit column.
Similar to
The figures also show one read bus 1430 per pixel sub-column 1452 and one read bus 1440 per circuit column 1456. In this embodiment, the associated circuitry 1470 in a circuit column 1456 is two pixels wide and three pixels long, but it will be appreciated that any circuit column aspect ratio may be utilized by the disclosure. As can be seen in
As noted herein above, each pixel sub-column 1452 may be electrically associated or connected to one pixel sub-column bus 1430, and each circuit column 1456 may be electrically associated or connected to one circuit column bus 1440.
c also illustrate how differing aspect ratios between the substrates can allow for flexibility in bus contact points. In the embodiment, the column circuit bus 1440 has been designed with a general Au@ shape that so as to occupy the area of the circuit column 1456 more evenly, thereby providing options for connecting the interconnect 1424 throughout the entire circuit column 1456. Note that the pixel column bus 1430 is not generally u-shaped, but the circuit column bus 1440 may be generally u-shaped, so that the same column circuit 1456 may be used with the two adjacent, but different pixel column configurations. The first leg of the u-shaped circuit column buses 1440a and 1440b may be superimposed to the read buses 1430a and 1430b of the pixel sub-columns 1487 and 1488 (as illustrated in
As can be seen in
It should be noted that the exemplary aspect ratio of the support circuit area in
In
In
It will be appreciated that the structures and apparatuses disclosed herein are merely exemplary for optimizing an imaging sensor, and it should be appreciated that any structure, apparatus or system for optimizing an image sensor, which performs functions the same as, or equivalent to, those disclosed herein are intended to fall within the scope of this disclosure, including those structures, apparatuses or systems for imaging, which are presently known, or which may become available in the future. Anything which functions the same as, or equivalently to, a means for optimizing an imaging sensor falls within the scope of this disclosure.
Those having ordinary skill in the relevant art will appreciate the advantages provide by the features of the disclosure. For example, it is a potential feature of the disclosure to provide an optimized imaging sensor, which is simple in design and manufacture. Another potential feature of the disclosure is to provide such an imaging sensor with larger pixels relative to overall size.
In the foregoing Detailed Description, various features of the disclosure are either grouped together in a single embodiment for the purpose of streamlining the disclosure or are discussed in different embodiments. This method of disclosure is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment and various inventive features disclosed in separate embodiments may be combined to form its own embodiment as claimed more fully below. Thus, the following claims are hereby incorporated into this Detailed Description by this reference, with each claim standing on its own as a separate embodiment of the disclosure.
It is to be understood that the above-described arrangements are only illustrative of the application of the principles of the disclosure. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of the disclosure and the appended claims are intended to cover such modifications and arrangements. Thus, while the disclosure has been shown in the drawings and described above with particularity and detail, it will be apparent to those of ordinary skill in the art that numerous modifications, including, but not limited to, variations in size, materials, shape, form, function and manner of operation, assembly and use may be made without departing from the principles and concepts set forth herein.
This application is a continuation of U.S. application Ser. No. 16/886,587, filed May 28, 2020, which is a continuation of U.S. application Ser. No. 15/489,588, filed Apr. 17, 2017 (now U.S. Pat. No. 10,709,319), which is a continuation of U.S. application Ser. No. 13/471,432, filed May 14, 2012 (now U.S. Pat. No. 9,622,650) and which claims the benefit of: (1) U.S. Provisional Application No. 61/485,426, filed May 12, 2011; (2) U.S. Provisional Application No. 61/485,432, filed May 12, 2011; (3) U.S. Provisional Application No. 61/485,435, filed May 12, 2011; and, (4) U.S. Provisional Application No. 61/485,440, filed May 12, 2011, which are all hereby incorporated by reference herein in their entireties, including but not limited to those portions that specifically appear hereinafter, the incorporation by reference being made with the following exception: In the event that any portion of the above-referenced provisional applications are inconsistent with this application, this application supersedes said above-referenced provisional applications.
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Child | 17088502 | US | |
Parent | 15489588 | Apr 2017 | US |
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Parent | 13471432 | May 2012 | US |
Child | 15489588 | US |