Patent Application
20250167193
The subject matter disclosed herein relates to microelectronics packaging and integrated circuits (IC) packaging. More particularly, the subject matter disclosed herein relates to a package architecture involving the configuration of backside power networks.
Semiconductor devices may connect to additional devices and circuitry on different substrates. Forming connections between substrates can provide increased computation. However, forming connections between substrates can cause difficulties. Packaging describes the general method for connecting and integrating multiple computational components together in an integrated unit, and may involve multiple different types of integrated circuits on multiple substrates which may combine into a single unit. It is further noted that background concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. Nor should the background or field described herein be intended to limit the disclosure herein to a particular use or concept.
An example embodiment provides a device including a first layer having at least one transistor, a second layer on a first side of the first layer, the second layer including a signal network, a third layer on a second side of the first layer, the second side opposite the first side, the third layer including a backside power delivery network, and a memory module coupled to the signal network. In some embodiments, the memory module includes at least one dynamic random access memory die. In some embodiments, the at least one dynamic random access memory die may include at least one core memory die. In some embodiments, the signal network is between the first layer and the memory module, and the signal network communicatively couples the first layer and the memory module. In some embodiments, a redistribution layer is between the signal network and the memory module. In some embodiments, the redistribution layer includes at least one through-bonding via. In some embodiments, the backside power delivery network provides power to the memory module. In some embodiments, the signal network provides packet routing signals to the memory module. In some embodiments, backside power delivery network, the at least one transistor, and the signal network together may provide a logic circuit for the memory module.
An example embodiment provides a system including a substrate having a first side and a second side opposite the first side, a transistor layer may be on the first side of the substrate, the transistor layer including at least one transistor. A signal network may be on the transistor layer, and the signal network may be communicatively coupled to the transistor layer. A backside power delivery network may be on the second side of the substrate, the backside power delivery network electrically coupled to the transistor layer, and backside power delivery network, the transitory layer, and the signal network together may provide a logic circuit for the memory module. In some embodiments, the memory module includes at least one high bandwidth memory die. In some embodiments, the at least one high bandwidth memory die includes at least one core memory die. In some embodiments, the memory module is mounted on the substrate. In some embodiments, a redistribution layer is between the signal network and the memory module. In some embodiments, the redistribution layer may include at least one through-bonding via.
An example embodiment provides a method including forming a transistor layer on a first side of a first substrate, the transistor layer including at least one transistor; forming a signal network layer on the transistor layer, the signal network layer communicatively coupled to the transistor layer; forming a backside power delivery network layer on a second side of the first substrate, the second side opposite the first side, the backside power delivery network layer electrically coupled to the transistor layer; bonding a memory module to the signal network layer; and attaching the backside power delivery network to a second substrate. In some embodiments, the memory module is at least one high bandwidth memory die. In some embodiments, bonding a memory module to the signal network layer includes forming a redistribution layer on the signal network layer and bonding the memory module to the redistribution layer. In some embodiments, bonding the memory module to the redistribution layer includes a hybrid bonding process. In some embodiments, prior to forming the backside power delivery network, the second side of the first substrate is partially removed.
In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined, etc.), and a capitalized entry (e.g., “Counter Clock,” “Row Select,” “PIXOUT,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clock,” “row select,” “pixout,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.
Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein substrates may refer to a variety of materials and structures, including wafers using silicon, wafers using silicon on an insulator (SOI) such as glass, wafers of other semiconductor materials such as germanium, as well as other semiconductor materials on an insulator. In some embodiments, a substrate may include an organic material. In some embodiments, the substrates may be referred to as wafers, dies, and chips alone or in combination. Bonding substrates may be thus known in some embodiments as die-to-die (D2D) bonding, wafer-to-wafer bonding (W2 W) or die-to-wafer bonding (D2 W). In some embodiments, the substrates may contain circuits such as integrated circuits including central processing units (CPUs), logic chips, memory such as static random-access memory (SRAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), double data rate DRAM or DDR DRAM, application processors (AP), graphical processing units (GPUs), other forms of auxiliary processing units (xPU), Artificial intelligence (AI) chips, High bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASIC). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, a substrate may include a packaged chip.
As used herein, high bandwidth memory or HBM, may refer to a chip structure including one or more HBM modules. In some embodiments, the HBM may be manufactured by an advanced silicon node process.
As used herein packaging refers to a process of forming interconnections between substrates. In some embodiments, the interconnections may be between direct surfaces and involve W2 W, D2D, and D2 W bonding. In other embodiments, techniques including wire bonding and other forms of indirect bonding may be performed alone or in combination with W2 W, D2D, and D2 W bonding. In some embodiments, circuits may be bonded directly facing each other, while in other embodiments a flip-chip bonding may be used. In some embodiments, interconnections may be made between substrates on a front or circuit side of the substrate. In other embodiments, interconnections may be made on a rear or back side of the substrate opposite from the circuit structure. In some embodiments, an interconnection may include through-silicon vias (TSVs) or other forms of through-chip vias where one or more substrates may be connected using a via traveling through an interposer such as another substrate or chip. In some embodiments, an interconnection may be formed using connections on a surface of a substrate, such as a pad, and may use additional materials between the pads such as solder to form an interconnection.
As used herein, conductors may refer to a variety of conductive materials, including which materials may be used alone or in combination with other materials such as in the form of an alloy. In some embodiments the conductor is copper (Cu). In some embodiments, copper (Cu) may be in the form of Cu (II), Cu (III) or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru). Such a listing of elements is not intended to be exhaustive, and in other embodiments, any known other type of conductive material may be used.
As used herein, a System-on-a-chip or SOC refers to an integrated circuit that integrates most or all components of a computer into a single die. In some embodiments, the components may include on-chip CPU, memory interfaces, input/output (I/O) devices and interfaces, secondary storage interfaces, and may include other components such GPUs. In some embodiments a SOC may contain digital, analog, mixed-signal, and radio frequency signal processing functions. In some embodiments, the SOC may be manufactured by processes including an advanced silicon node process.
Disclosed herein are various embodiments of devices, systems and methods related to packaging architecture to combine backside power delivery networks (BSPDN), signal networks, and various forms of high bandwidth memory, including Joint Electron Device Engineering Council (JEDEC) standard HBM and non-JEDEC standard HBM. In some embodiments, other forms of DRAM may be used, including both SDRAM and other forms including DDR DRAM. In some embodiments, a BSPDN may be formed on the backside of a substrate, with a signal network formed on the front side of the same substrate. In some embodiments, the BSPDN and signal network may be formed on separate substrates and transferred to the same substrate. The BSPDN and signal network may be separated by a transistor layer. The transistor layer may include a plurality of transistors. The transistors may provide different functions and take different forms, including a logic layer. The BSPDN and signal network may form a single monolithic structure on the same die in a semiconductor foundry process. A memory module may be formed in a separate semiconductor foundry process, the same semiconductor foundry process, or may have multiple components formed in multiple semiconductor foundry processes and assembled in a packaging assembly process.
The interface structure 130 couples the memory module 102 to the base chip 104 at a redistribution layer 150. The redistribution layer 150 is coupled to a signal network layer 152, which is in turn coupled to a transistor layer 154. The redistribution layer 150 may include a series of pads, lines, traces, and other forms of connection forming the top surface of the base chip 104. The redistribution layer 150 allows for connections between the memory module 102 and the base chip 104 to be spread out from where lines and vias may emerge on the surface of the signing section, allowing additional space for the connections to be formed, as well as providing additional space to prevent inadvertent connections. The signal network layer 152 may comprise a network-on-a-chip (NOC), and may provide interconnections to transport signals to and from the memory module 102. In some embodiments, the signal network layer 152 may provide packet routing. In some embodiments, the signal network layer 152 may comprise a plurality of layers, including multiple layers providing signal routing. In some embodiments, the signal network layer 152 may comprise a plurality of conductive channels within a dielectric material, and the plurality of conductive channels may be arranged in multiple layers, with the size of the conductive channels decreasing in distance from the transistor layer 154. In some embodiments, the signal network layer 152 may have a plurality of conductive channels in 4, 8, 10, 12 or more layers. In some embodiments, the conductive channels may include a conductive material such as a metal, including copper, aluminum, tungsten, alloys thereof, or any other known suitable conductive material alternatively or in addition, the conductive materials may include various forms of other conductive materials, including doped carbon, as well as conductive nanotubes. In some embodiments, the size of the conductive channels in a top layer of the signal network layer 152 may be substantially the same size as conductive channels of the HBM.
The transistor layer 154 separates the signal network layer 152 from a BSPDN layer 158 and the transistor layer 154 includes a plurality of transistors. As used herein, the transistor layer 154 may be used to refer to both the layer containing the plurality transistors and the plurality of transistors. In some embodiments, the transistor layer 154 may act as a base logic for both the signal network layer 152 and the BSPDN layer 158. As used herein, basic logic may refer to a logic circuit providing routing of communication signals and power signals. In other embodiments, the transistor layer 154 along with the signal network layer 152 and the BSPDN layer 158 provide the base logic for the memory module 102. The BSPDN layer 158 provides a power delivery network for routing power supply lines 156 on the back side of the transistor layer 154 and may provide both power and reference voltages to transistors in transistor layer 154. The BSPDN layer 158 may include multiple different layers of power supply lines 156 routing power within an insulating material. In some embodiments the insulating material may include a dielectric material. In some embodiments, the BSPDN layer 158 may include 15 to 20 layers of the power supply lines 156, while in other embodiments, the number of layers of the power supply lines 156 may vary, and include more than 20 or less than 15 layers. In some embodiments, the size of the power supply lines 156 may decrease as they approach the transistor layer 154. The power supply lines 156 may be comprised of conductive materials, including various forms of low resistive metals, such as copper, aluminum, tungsten, alternatively or in addition, the conductive materials may include various forms of other conductive materials, including doped carbon, as well as conductive nanotubes.
A power substrate layer 160 forms the bottom of the BSPDN layer 158 and includes a via with a plug 162 to couple the BSPDN layer 158 to the supporting substrate 106 with an interconnect 170. In some embodiments, a plurality of plugs and vias may be used to connect couple the BSPDN layer 158 to the supporting substrate 106. The interconnect 170 may include conductive connections including pads, bumps, microbumps, pillars, balls, and other forms such as C4 bumps, as well as any other form of conductive connection alone or in combination. Furthermore, the interconnect 170 may include a dielectric connection, such as a dielectric material, which may include a material such as an adhesive, resin, or elastomer which may form a dielectric connection in addition to a conductive connection. In some embodiments, the combination of a conductive connection and a dielectric connection may form a hybrid bond. The supporting substrate 106 may in turn connect to other devices and dies, and in some embodiments, may take the form of an interposer supporting multiple devices and dies on an additional substrate such as a circuit board. In some embodiments, the supporting substrate 106 may support multiple sets of the memory module 102 on the base chip 104.
The auxiliary processing unit 404 may provide additional processing for a device that the card structure 400 may be utilized in, and may include any suitable form of processing device including, for example, a GPU or a CPU, and may include a plurality of cores. In some embodiments, where the auxiliary processing unit 404 takes the form of a GPU, the auxiliary processing unit 404 may include a 3-D engine 406, a display controller 407, and may include an auxiliary controller 408. In some embodiments, where the packaged memory module 402 lacks a core die, the auxiliary controller 408 may take the form of a HBM controller. In some embodiments, the auxiliary controller 408 may be omitted or reassigned. In some embodiments, where the auxiliary processing unit 404 takes the form of a CPU, the auxiliary processing unit 404 may include a multi-core processor positioned close to the packaged memory module 402 such that latency may be decreased, and the effective storage capacity may be increased.
In some embodiments, a memory module mounted on the power and signal substrate may be thermally coupled to the power and signal substrate such that a thermal path is formed between the BSPDN layer and the memory module. In some embodiments, the thermal energy from the BSPDN may be dissipated by portions of the memory module. For example, in some embodiments, the memory module may include materials or structures to assist in dissipating heat, such as fins.
In some embodiments, a package architecture which integrates a chip using backside power delivery with stacked memory may monolithically integrate a memory module with a power and signal substrate including both a signal network layer and a BSPDN layer. In some embodiments, an integrated packaged memory structure may form a monolith where the memory module and power and signal substrate are closely integrated. A monolith may, among other advantages, reduce the size of routing distances, and thus a monolith may have decrease the voltage drop due to routing distances. A monolith may also provide increased power efficiency, reduced latency, and reduced routing congestion over a non-integrated form from the decreases in routing distances and higher density of devices.
While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.
This application claims the priority benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63/602,363 filed on Nov. 22, 2023, the disclosure of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63602363 | Nov 2023 | US |
