Patent Application
20250113484
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including split support pillar structures and methods for manufacturing the same.
Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a memory device comprises: a pair of alternating stacks of insulating layers and electrically conductive layers, wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench that laterally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; a lateral isolation trench fill structure located in the lateral isolation trench; and support pillar structures vertically extending through a respective one of the pair of alternating stacks, wherein the support pillar structures comprise first-type support pillar structures each having a respective circular or elliptical horizontal cross-sectional shape, and second-type support pillar structures each having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically-extending surface.
According to another aspect of the present disclosure, a method of forming a device structure comprises: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming stepped surfaces by patterning the alternating stack; forming a retro-stepped dielectric material portion over the stepped surfaces; forming support opening fill structures through the retro-stepped dielectric material portion and an underlying portion of the alternating stack; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench through the retro-stepped dielectric material portion, through the alternating stack, and through a first row of first support pillar structures of the support pillar structures to cut each of the first support pillar structures into a respective pair of auxiliary support pillar structures, each of the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically-extending surface in opposing sidewalls of the lateral isolation trench; and replacing the sacrificial material layers with electrically conductive layers.
In an alternative embodiment, the lateral isolation trench is formed through the retro-stepped dielectric material portion, through the alternating stack, and through first and second rows of first support pillar structures of the support pillar structures to cut each of the first and second support pillar structures into a respective pair of auxiliary support pillar structures, each of the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically-extending surface in opposing sidewalls of the lateral isolation trench.
According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks comprises insulating layers and electrically conductive layers that are interlaced along a vertical direction, and wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench that laterally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements; rows of support pillar structures, wherein each row of the support pillar structures laterally extends along the first horizontal direction and vertically extends through a respective one of the pair of alternating stacks; and a lateral isolation trench fill structure having a variable width along a second horizontal direction and located in the lateral isolation trench, the lateral isolation trench fill structure comprising: a plurality of neck portions having a pair of straight sidewalls which extend along the first horizontal direction and having a first width along the second horizontal direction that is perpendicular to the first horizontal direction; and a plurality of laterally bulging portions having a second width along the second horizontal direction that is greater than the first width, wherein the plurality of laterally bulging portions is interlaced with the plurality of neck portions along the first horizontal direction.
According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method comprises: forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over a substrate; forming memory openings through the vertically alternating sequence; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; forming rows of support pillar structures, wherein each row of the support pillar structures is periodically arranged along a first horizontal direction with a uniform pitch and vertically extends through the vertically alternating sequence; forming a lateral isolation trench that generally extends along the first horizontal direction through the vertically alternating sequence, wherein the lateral isolation trench has a variable width along a second horizontal direction, the variable width having a periodic undulation along the first horizontal direction with a periodicity that is the same as the uniform pitch; and replacing remaining portions of the continuous sacrificial material layers with electrically conductive layers to form a pair of alternating stacks of insulating layers and electrically conductive layers that are separated by the lateral isolation trench along the second horizontal direction.
According to an aspect of the present disclosure, a three-dimensional memory device comprises: a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks comprises insulating layers and electrically conductive layers that are interlaced along a vertical direction, and wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench that laterally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; and a lateral isolation trench fill structure located in the lateral isolation trench and comprising a plurality of neck portions having a pair of straight sidewalls which extend along the first horizontal direction and having a first width along a second horizontal direction that is perpendicular to the first horizontal direction; and a plurality of laterally bulging portions having a second width along the second horizontal direction that is greater than the first width, wherein the plurality of laterally bulging portions is interlaced with the plurality of neck portions along the first horizontal direction.
According to an aspect of the present disclosure, a three-dimensional memory device comprises: an alternating stack of insulating layers and electrically conductive layers; memory openings vertically extending through the alternating stack in a memory array region; memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; layer contact via structures contacting a respective one of the electrically conductive layers and located in a contact region that is laterally offset from the memory array region along the first horizontal direction; a lateral isolation trench fill structure located adjacent to the alternating stack, the lateral isolation trench fill structure comprising a plurality of narrower neck portions and wider laterally bulging portions which alternate with the neck portions along the first horizontal direction and which are located in a transition region between the memory array region and the contact region along the first horizontal direction; first-type support pillar structures each vertically extending through the alternating stack in the contact region and consisting essentially of at least one dielectric material; and second-type support pillar structures each vertically extending through the alternating stack in the transition region and comprising a respective set of dielectric material layers and a respective semiconductor material layer.
As discussed above, the present disclosure is directed to a three-dimensional memory device including split support pillar structures and methods for manufacturing the same, the various aspects of which are described below.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, an element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, an element is located “directly on” a second element if there exist a physical contact between a surface of the element and a surface of the second element. As used herein, an element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0×10−5 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×107 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×10−5 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to provide electrical conductivity greater than 1.0×10−5 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×107 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
Referring to
An insulating material layer can be formed on a top surface of the carrier substrate 9. The insulating material layer can be subsequently employed as a stopping material layer for a process that removes the carrier substrate 9, and is herein referred to as a stopper insulating layer 106, or as a backside pad dielectric layer. If a polishing process such as a chemical mechanical polishing process is employed to subsequently remove the carrier substrate 9, the stopper insulating layer 106 may be subsequently employed as a polishing stopper material layer. If an etch process such as a wet etch process is employed to subsequently remove the carrier substrate 9, the stopper insulating layer 106 may be subsequently employed as an etch stop material layer. In one embodiment, the stopper insulating layer 106 comprises a dielectric material such as undoped silicate glass, a doped silicate glass, or silicon nitride. The thickness of the stopper insulating layer 106 may be in a range from 50 nm to 600 nm, such as from 100 nm to 300 nm, although lesser and greater thicknesses may also be employed.
In-process source-level material layers 110′ can be formed over the stopper insulating layer 106. The in-process source-level material layers 110′ may include various layers that are subsequently modified to form source-level material layers. The source-level material layers, upon formation, include a source contact layer that functions as a common source region for vertical field effect transistors of a three-dimensional memory device. In one embodiment, the in-process source-level material layers 110′ may include, from bottom to top, a lower source-level semiconductor layer 112, an optional lower sacrificial liner (not shown), a source-level sacrificial layer 104, an optional upper sacrificial liner (not shown), and an upper source-level semiconductor layer 116.
The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be the opposite of the conductivity of vertical semiconductor channels to be subsequently formed. For example, if the vertical semiconductor channels to be subsequently formed have a doping of a first conductivity type, the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 have a doping of a second conductivity type that is the opposite of the first conductivity type. The thickness of each of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be in a range from 10 nm to 300 nm, such as from 20 nm to 150 nm, although lesser and greater thicknesses may also be used.
The source-level sacrificial layer 104 includes a sacrificial material that may be removed selective to the lower sacrificial liner (or selective to the lower source-level semiconductor layer 112) and the upper sacrificial liner (or selective to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 may include a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 may be in a range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses may also be used. The lower sacrificial liner (if present) and the upper sacrificial liner (if present) include materials that may function as an etch stop material during removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner and the upper sacrificial liner may include silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner and the upper sacrificial liner may include a silicon oxide layer having a thickness in a range from 2 nm to 30 nm, although lesser and greater thicknesses may also be used.
An alternating stack of first material layers and second material layers can be formed over the in-process source-level material layers 110′. The alternating sequence comprises a vertically alternating stack in which the first material layers and the second material layers are interlaced along the vertical direction. In an alternative embodiment, the in-process source-level material layers 110′ and the stopper insulating layer 106 may be omitted, and the alternating stack is formed directly on a surface of the carrier substrate 9. In another alternative embodiment describe below with respect to
In the alternating stack, the first material layers may be insulating layers, and the second material layers may be spacer material layers. In one embodiment, the spacer material layers may comprise sacrificial material layers 42. In this case, an alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 can be formed over the carrier substrate 9 (e.g., over the in-process source-level material layers 110′, if present). The insulating layers 32 comprise an insulating material such as undoped silicate glass or a doped silicate glass, and the sacrificial material layers 42 comprise a sacrificial material, such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layers 32 (i.e., the first material layers) may comprise silicon oxide layers, and the sacrificial material layers 42 (i.e., the second material layers) may comprise silicon nitride layers. The alternating stack (32, 42) may comprise multiple repetitions of a unit layer stack including an insulating layer 32 and a sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in a range from 8 to 1,024, such as from 32 to 256, although lesser and greater number of repetitions may also be employed. The topmost one of the insulating layers 32 is hereafter referred to as a topmost insulating layer 32T. The bottommost one of the insulating layers 32 is an insulating layer 32 that is most proximal to the carrier substrate 9 is herein referred to as a bottommost insulating layer 32B. Each of the insulating layers 32 other than the topmost insulating layer 32 may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each of the sacrificial material layers 42 may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the topmost insulating layer 32 may have a thickness of about one half of the thickness of other insulating layers 32.
The first exemplary structure comprises a memory array region 100 in which a three-dimensional array of memory elements is to be subsequently formed, and a contact region 300 in which layer contact via structures contacting word lines are to be subsequently formed. The first exemplary structure further comprises a transition region 200 in which support openings and composite support pillar structures including multiple materials are to be subsequently formed. The insulating layers 32 continuously extend across the memory array region 100 and the contact region 300 without a pattern, and may be referred to as continuous insulating layers 32. The sacrificial material layers 42 continuously extend across the memory array region 100 and the contact region 300 without a pattern, and may be referred to as continuous sacrificial material layers 42. Thus, a vertically alternating sequence of continuous insulating layers 32 and continuous sacrificial material layers 42 can be formed.
Referring to
The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the in-process source-level material layers 110′. In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.
Each sacrificial material layer 42 other than a topmost sacrificial material layer 42 within the alternating stack (32, 42) laterally extends farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the terrace region. The stepped surfaces of the alternating stack (32, 42) continuously extend from a bottommost layer within the alternating stack (32, 42) (such as the bottommost insulating layer 32B) to a topmost layer within the alternating stack (32, 42) (such as the topmost insulating layer 32T).
A stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65, which can be a retro-stepped dielectric material portion. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may, or may not, be doped with dopants such as B, P, and/or F.
Optionally, drain-select-level isolation structures (not shown) can be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 located at drain-select-levels. The drain-select-level isolation structures can be formed, for example, by forming drain-select-level lateral isolation trenches and filling the drain-select-level lateral isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer 32T.
Referring to
In one embodiment, the memory array region 100 may be laterally spaced apart from the contact region 300 along a first horizontal direction hd1 by the transition region 200. The memory openings 49 may comprise rows of memory openings 49 that are arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd2. Multiple clusters of memory openings 49, each containing a respective two-dimensional periodic array of memory openings 49, may be formed in the memory array region 100. The clusters of memory openings 49 may be laterally spaced apart along the second horizontal direction hd2 by strip regions that are free of any opening (49, 19). Likewise, multiple clusters of first-type support openings 19A may be formed in the contact region 300 such that the clusters of first-type support openings 19A may be laterally spaced apart along the second horizontal direction hd2 by the strip regions that are free of any opening (49, 19). Further, multiple clusters of second-type support openings 19B may be formed in the transition region such that the clusters of second-type support openings 19B may be laterally spaced apart along the second horizontal direction hd2 by the strip regions that are free of any opening (49, 19).
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A semiconductor channel material layer 60L can be deposited over the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L may have a doping of a first conductivity type, which may be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a doping of the first conductivity type. In an illustrative example, the atomic concentration of dopants of the first conductivity type in the semiconductor channel material layer 60L may be in a range from 1.0×1013/cm3 to 3.0×1017/cm3, such as 1.0×1014/cm3 to 3.0×1016/cm3, although lesser and greater atomic concentrations may also be employed. A dielectric core layer 62L comprising a dielectric fill material can be deposited in remaining volumes of the memory openings 49 and over the alternating stack (32, 42).
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Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel material layer 60L can be removed from above the horizontal plane including the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel 60.
Each portion of the layer stack including the memory material layer 54 that remains in a respective memory opening 49 constitutes a memory film 50. In one embodiment, a memory film 50 may comprise an optional blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each contiguous combination of a memory film 50 and a vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 comprises a respective vertical stack of memory elements, which may comprise portions of the memory material layer 54 located at levels of the sacrificial material layers 42, or generally speaking, at levels of spacer material layers that may be subsequently replaced at least partly with electrically conductive layers.
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Each of the second-type support pillar structures 20B comprises a respective set of dielectric material layers and a respective semiconductor material layer. Each set of dielectric material layers may have a same set of material layers as the memory film 50. In other words, each memory film 50 has a same set of materials as, and has a same thickness as, a set of dielectric material layers in a second-type support pillar structure 20B. Furthermore, each of the memory opening fill structures 58 comprises a vertical semiconductor channel 60 having a same material composition and a same thickness as a semiconductor material layer in a second-type support pillar structure 20B. Each semiconductor material layer may have the same material composition and the same thickness as a vertical semiconductor channel 60. Thus, the second-type support pillar structures 20B comprise dummy memory opening structures which have the same structure and composition as the memory opening fill structures 58, but which are not electrically connected to bit lines and which are not used to store data during operation of the memory device.
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A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80, and can be lithographically patterned to form various openings therein. The openings in the photoresist layer comprise elongated laterally-undulating openings that generally extend along the first horizontal direction hd1 in the strip regions located between neighboring clusters of memory opening fill structures 58 (e.g., between adjacent memory block areas).
An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42) (i.e., the vertically alternating sequence (32, 42)), and the stepped dielectric material portion 65, and into the in-process source-level material layers 110′ (if present). Lateral isolation trenches 79 can be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the in-process source-level material layers 110′ (if present). The lateral isolation trenches 79 vertically extend through each layer within the alternating stack (32, 42) and into an upper portion of a semiconductor material layer (which may be located in the in-process source-level material layers 110′ or which may comprise a top portion of the carrier substrate 9 if the in-process source-level material layers 110′ are omitted). The lateral isolation trenches 79 laterally extend along the first horizontal direction hd1 (e.g., a word line direction). Each of the lateral isolation trenches 79 may comprise a respective pair of laterally-undulating lengthwise sidewalls that generally extend along the first horizontal direction hd1, have a respective width modulation along the second horizontal direction hd2, and vertically extend from the stopper insulating layer 106 to the top surface of the contact-level dielectric layer 80. In one embodiment, the lower source-level semiconductor layer 112 may be physically exposed underneath each lateral isolation trench 79.
In one embodiment, the lateral isolation trenches 79 may have a respective vertical cross-sectional profile including an inflection line 79I, at which a tapered surface segment of a continuously-extending sidewall is adjoined to a reverse-tapered surface segment of a continuously-extending sidewall. As used herein, a tapered surface segment refers to a surface segment at which a lateral dimension of a volume of an element increases with a vertical distance from an underlying substrate, and a reverse-tapered surface segment refers to a surface segment at which the lateral dimension of the volume of the element decreases with a vertical distance from the underlying substrate. Thus, in one embodiment, the sidewall of the lateral isolation trenches 79 may optionally have gradually changing slopes, and may optionally have a bowing vertical cross-sectional profile, with the largest width being at the inflection line 79I. The lateral isolation trenches 79 may have a maximum lateral width at along the second horizontal direction hd2 at the inflection line 79I. Each inflection line may laterally extend generally along the first horizontal direction hd1, and may have a respective periodic lateral undulation along the second horizontal direction hd2.
In summary, lateral isolation trenches 79 can be formed through the vertically alternating sequence (32, 42). Each lateral isolation trench 79 may comprise a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1. A vertical cross-sectional profile of the lateral isolation trench 79 in a vertical plane that is perpendicular to the first horizontal direction hd1 has a variable width that increases with a vertical distance from a horizontal plane including a bottommost surface of the vertically alternating sequence (32, 42) in a lower portion of the vertically alternating sequence (32, 42) to the horizontal plane including the inflection line 79I, and decreases with the vertical distance from the horizontal plane including the inflection line 79I located in an upper portion of the vertically alternating sequence (32, 42), as shown in
In one embodiment shown in
In the embodiment shown in
In one embodiment shown in
In one embodiment, each of the laterally convex surface segments of the laterally-bulging portions 79B may be laterally bounded by concave surfaces of alternating stacks of insulating layers 32 and sacrificial material layers 42 in a horizontal cross-sectional view. The plurality of laterally bulging portions 79B are formed at least in the transition region 200, and may be formed in the memory array region 100 and/or in the contact region 300. In one embodiment, a first subset of the laterally bulging portions 79B may be located in the transition region 200, a second subset of the laterally bulging portions 79B may be located in the memory array region 100, and a third subset of the laterally bulging portions 79B may be located in the contact region 300.
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In one embodiment, the maximum of the variable width is a second width w2. In the first alternative configuration, an entire portion of each lateral isolation trench 79 located in the memory array region 100 may have a uniform array-region width w_a that is less than the second width w2, and an entire portion of each lateral isolation trench 79 located in the contact region 300 may have a uniform contact-region width w_c that is less than the second width w2. In one embodiment, the uniform array-region width w_a is not less than the first width w1; and the uniform contact-region width w_c is not less than the first width w1. In one embodiment, the uniform array-region width w_a and the uniform contact-region width w_c may be the same as the first width w1 of the neck portions 79N. In one embodiment, the plurality of laterally bulging portions 79B in each lateral isolation trench 79 has a uniform pitch along the first horizontal direction hd1, which may be the same as the first pitch p1.
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Wet etch chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as the p-doped semiconductor material and/or the n-doped semiconductor material of the upper source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Thus, use of selective wet etch chemicals such as hot TMY and TMAH for the wet etch process that forms the source cavity 109 provides a large process window against etch depth variation during formation of the lateral isolation trenches 79. Specifically, even if sidewalls of the upper source-level semiconductor layer 116 are physically exposed or even if a surface of the lower source-level semiconductor layer 112 is physically exposed upon formation of the source cavity 109, collateral etching of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 is minimal, and the structural change to the first exemplary structure caused by accidental physical exposure of the surfaces of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 during manufacturing steps do not result in device failures. Each of the memory opening fill structures 58 is physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 includes a sidewall and that are physically exposed to the source cavity 109.
A sequence of isotropic etchants, such as wet etchants, may be applied to the physically exposed portions of the memory films 50 to sequentially etch the various component layers of the memory films 50 from outside to inside, and to physically expose cylindrical surfaces of the vertical semiconductor channels 60 at the level of the source cavity 109. The upper sacrificial liner 105 (if present) and the lower sacrificial liner 103 (if present) may be collaterally etched during removal of the portions of the memory films 50 located at the level of the source cavity 109. The source cavity 109 may be expanded in volume by removal of the portions of the memory films 50 at the level of the source cavity 109 and the upper and lower sacrificial liners. A top surface of the lower source-level semiconductor layer 112 and a bottom surface of the upper source-level semiconductor layer 116 may be physically exposed to the source cavity 109. The source cavity 109 is formed by isotropically etching the source-level sacrificial layer 104 and a bottom portion of each of the memory films 50 selective to at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channels 60.
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In one embodiment, the doped semiconductor material of the second conductivity type may be deposited on the physically exposed semiconductor surfaces around the source cavity 109 by a selective semiconductor deposition process. A semiconductor precursor gas, an etchant, and a dopant gas may be flowed concurrently into a process chamber including the first exemplary structure during the selective semiconductor deposition process. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of a dopant atom such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which may contact sidewalls of the vertical semiconductor channels 60. The atomic concentration of the dopants of the second conductivity type in the deposited semiconductor material may be in a range from 1.0×1020/cm3 to 2.0×1021/cm3, such as from 2.0×1020/cm3 to 8.0×1020/cm3. The source contact layer 114 as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or voidless source contact layer 114.
The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material having a doping of the second conductivity type from semiconductor surfaces around the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source-level sacrificial layer 104 may be replaced with the source contact layer 114. The layer stack including the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116 constitutes source-level material layers 110, which replaces the in-process source-level material layers 110′. The source-level material layers 110 contact an end portion of each of the vertical semiconductor channels 60. Optionally, a dielectric surface conversion process, such as an oxidation process or a nitridation process, may be performed to convert physically exposed surface portions of the source-level material layers 110 from underneath each lateral isolation trench 79 to form trench bottom dielectric liners 129. The source-level material layers 110 include semiconductor material layers such as a stack of a lower source-level semiconductor layer 112, a source contact layer 114, and an upper source-level semiconductor layer 116.
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A plurality of alternating stacks (32, 46) of insulating layers 32 and electrically conductive layers 46 can be formed, which can be laterally spaced apart from each other by the lateral isolation trenches 79. Each laterally-neighboring pair of alternating stacks (32, 46) can be laterally spaced from each other by a lateral isolation trench 79 that laterally extends along a first horizontal direction hd1. Memory openings 49 vertically extend through a respective one of the alternating stacks (32, 46). Memory opening fill structures 58 can be located in a respective one of the memory openings 49. Each of the memory opening fill structures 58 comprises a respective vertical semiconductor channel 60 and a respective vertical stack of memory elements (e.g., portions of the memory film 50) located at levels of the electrically conductive layers 46.
Referring to
The insulating spacers 74 comprise an insulating material, such as undoped silicate glass or a doped silicate glass. Each of the insulating spacers 74 may comprise a pair of laterally-undulating outer sidewalls and a pair of laterally-undulating inner sidewalls. A lateral isolation cavity 79′ can be present within each lateral isolation trench 79.
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Each lateral isolation trench fill structure (74, 76) comprises an insulating spacer 74 and a conductive fill structure 76 that is laterally surrounded by the insulating spacer 74. In one embodiment, each insulating spacer 74 comprises a pair of outer lengthwise sidewalls each comprising a plurality of laterally-convex surface segments that are interlaced with a plurality of first laterally-straight surface segments, and a pair of inner lengthwise sidewalls each comprising a plurality of laterally-concave surface segments that are interlaced with a plurality of second laterally-straight surface segments.
Each lateral isolation trench fill structure (74, 76) may comprise a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1. A vertical cross-sectional profile of the lateral isolation trench fill structure (74, 76) in a vertical plane that is perpendicular to the first horizontal direction hd1 has a variable width that increases with a vertical distance from a horizontal plane including a bottommost surface of the vertically alternating sequence (32, 42) in a lower portion of the vertically alternating sequence (32, 42) to the above described inflection line 79I, and decreases with the vertical distance from the horizontal plane including the inflection line 79I in an upper portion of the vertically alternating sequence (32, 42). In one embodiment, each lateral isolation trench fill structure (74, 76) has a width modulation along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 as a function of a lateral distance along the first horizontal direction hd1.
In one embodiment, each lateral isolation trench fill structure (74, 76) comprises a periodic laterally alternating sequence of neck portions (e.g., regions) 78N having a minimum width along the second horizontal direction hd2 and bulging portions (e.g., regions) 78B having a maximum width along the second horizontal direction hd2. In the embodiment shown in
Each lateral isolation trench fill structure (74, 76) generally extends along a first horizontal direction hd1 through the vertically alternating sequence (32, 42). Each lateral isolation trench fill structure (74, 76) comprises a plurality of neck portions 78N having a first width w1 along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 between a respective pair of straight surface segments that extend along the first horizontal direction hd1. Each lateral isolation trench fill structure (74, 76) further comprises a plurality of laterally bulging portions 78B having a variable width along the second horizontal direction that is greater than the first width w1. The plurality of laterally bulging portions 78B are interlaced with the plurality of neck portions 78N along the first horizontal direction hd1. In one embodiment, the maximum of the variable width may be a second width w2 at the middle of the laterally bulging portions 78B.
In one embodiment shown in
In one embodiment, each of the laterally convex surface segments of the laterally-bulging portions 78B may have a respective pair of convex surfaces in a horizontal cross-sectional view. The plurality of laterally bulging portions 78B are formed at least in the transition region 200, and may be formed in the memory array region 100 and/or in the contact region 300. In one embodiment, a first subset of the laterally bulging portions 78B may be located in the transition region 200, a second subset of the laterally bulging portions 78B may be located in the memory array region 100, and a third subset of the laterally bulging portions 78B may be located in the contact region 300.
The airgaps 767 are formed due to the second metal layer 766 necking at the top of the lateral isolation trenches 79, which may have a narrowing width above the inflection line 79I. If the airgaps 767 were continuous along the entire length of the lateral isolation trench fill structures (74, 76) along the first horizontal direction hd1, then such continuous airgaps 767 would structurally weaken the lateral isolation trench fill structures (74, 76). However, by forming lateral isolation trench fill structure (74, 76) with lateral undulations (e.g., with the alternating bulging and neck portions), the airgaps are closed off at the interface between the lateral undulations.
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In one embodiment, the maximum of the variable width is a second width w2. In the first alternative configuration, an entire portion of each lateral isolation trench fill structure (74, 76) located in the memory array region 100 may have a uniform array-region width w_a that is less than the second width w2, and an entire portion of each lateral isolation trench fill structure (74, 76) located in the contact region 300 may have a uniform contact-region width w_c that is less than the second width w2. In one embodiment, the uniform array-region width w_a is not less than the first width w1; and the uniform contact-region width w_c is not less than the first width w1. In one embodiment, the uniform array-region width w_a and the uniform contact-region width w_c may be the same as the first width w1 of the neck portions 78N. In one embodiment, the plurality of laterally bulging portions in each lateral isolation trench fill structure (74, 76) has a uniform pitch along the first horizontal direction hd1, which may be the same as the first pitch p1.
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At least one conductive material, such as a combination of a metallic barrier material and a metallic fill material, can be deposited in the drain contact via cavities and the layer contact via cavities. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which may employ a recess etch process and/or a chemical mechanical polishing process. Remaining portions of the at least one conductive material that fill the drain contact via cavities constitute drain contact via structures 88 contacting a top surface of a respective one of the drain regions 63. Remaining portions of the at least one conductive material that fill the layer contact via cavities constitute layer contact via structures 86 contacting a top surface of a respective one of the electrically conductive layers 46.
Referring to
A bit-line-level dielectric layer 120 can be formed above the connection-level dielectric layer 90. Bit-line-level line cavities can be formed through the bit-line-level dielectric layer 120, and can be filled with at least one conductive material (which may comprise at least one metallic material) to form bit-line-level metal lines (128, 126). The bit-line-level metal lines may comprise bit lines 128 that laterally extend along the second horizontal direction hd2, and bit-line-level interconnect metal lines 126 (not individually shown) that can be employed to provide electrical connection to the layer connection via structures 96.
Referring to
Metal bonding pads, which are herein referred to as memory-side bonding pads 988, may be formed at the topmost level of the memory-side dielectric material layers 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structures 980 and various nodes of the three-dimensional memory array including the alternating stacks of insulating layers 32 and electrically conductive layers 46 and the memory opening fill structures 58. A memory die 900 can thus be provided.
The memory-side dielectric material layers 960 are formed over the alternating stacks (32, 46). The memory-side metal interconnect structures 980 are embedded in the memory-side dielectric material layers 960. The memory-side bonding pads 988 can be embedded within the memory-side dielectric material layers 960, and specifically, within the topmost layer among the memory-side dielectric material layers 960. The memory-side bonding pads 988 can be electrically connected to the memory-side metal interconnect structures 980.
In one embodiment, the memory die 900 may comprise: a three-dimensional memory array comprising an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46, a two-dimensional array of memory openings 49 vertically extending through the alternating stack (32, 46), and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel 60; a two-dimensional array of drain contact via structures 88 electrically connected to a respective one of the vertical semiconductor channels 60; and a two-dimensional array of layer contact via structures 86 electrically connected to a respective one of the electrically conductive layers 46, a subset of which functions as word lines for the three-dimensional memory array.
Generally, a memory die 900 is provided, which comprises a memory array, memory-side metal interconnect structures 980, and memory-side bonding pads 988 embedded within memory-side dielectric material layers 960. The memory die 900 comprises a memory device, which may comprise a three-dimensional memory array including an alternating stack of insulating layers 32 and electrically conductive layers 46, and further comprises a two-dimensional array of NAND strings (e.g., the memory opening fill structures 58) vertically extending through the alternating stack (32, 46). In one embodiment, the electrically conductive layers 46 comprise word lines of the two-dimensional array of NAND strings. In one embodiment, the memory-side metal interconnect structures 980 comprise the bit lines 128 for the two-dimensional array of NAND strings.
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The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988. The bonding between the memory die 900 and the logic die 700 may be performed employing a wafer-to-wafer bonding process in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700, by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within a respective memory die 900.
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Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: a pair of alternating stacks (32, 46), wherein each alternating stack (32, 46) within the pair of alternating stacks (32, 46) comprises insulating layers 32 and electrically conductive layers 46 that are interlaced along a vertical direction, and wherein the pair of alternating stacks (32, 46) are laterally spaced from each other by a lateral isolation trench 79 that laterally extends along a first horizontal direction hd1; memory openings 49 vertically extending through a respective one of the pair of alternating stacks (32, 46); memory opening fill structures 58 located in a respective one of the memory openings 49 and comprising a respective vertical stack of memory elements (e.g., portions of the memory film 50) and a respective vertical semiconductor channel 60; and a lateral isolation trench fill structure (74, 76) located in the lateral isolation trench 79. The lateral isolation trench fill structure (74, 76) comprises a plurality of neck portions 78N having a pair of straight sidewalls which extend along the first horizontal direction hd1 and having a first width w1 along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1; and a plurality of laterally bulging portions 78B having a second width w2 along the second horizontal direction hd2 that is greater than the first width w1, wherein the plurality of laterally bulging portions 78B is interlaced with the plurality of neck portions 78N along the first horizontal direction hd1.
In one embodiment, the memory opening fill structures 58 are located in a memory array region 100; layer contact via structures 86 contacting a respective one of the electrically conductive layers 46 and located in a contact region 300 that is laterally offset from the memory array region 100 along the first horizontal direction hd1; and the plurality of laterally bulging portions is located at least in a transition region 200 that is located between the memory array region 100 and the contact region 300. In one embodiment, each of the memory opening fill structures 58 further comprises a respective drain region 63 that is contacted by a respective drain contact via structure 88; and the transition region 200 and the contact region 300 are free of any drain contact via structure 88.
In one embodiment, the three-dimensional memory device comprises: first-type support pillar structures 20A each vertically extending through a respective one of the pair of alternating stacks (32, 46) and located in the contact region 300 and consisting essentially of at least one dielectric material; and second-type support pillar structures 20B each vertically extending through a respective one of the pair of alternating stacks (32, 46) and located in the transition region 200 and comprising a respective set of dielectric material layers and a respective semiconductor material layer. In one embodiment, each of the plurality of laterally bulging portions 78B is located adjacent to a respective one of the plurality of the second-type support pillar structures 20B along the second horizontal direction hd2; the respective vertical stack of memory elements comprises portions of a respective memory film 50 located at levels of the electrically conductive layers 46; and the respective memory film 50 has a same set of materials as and has a same thickness as the respective set of dielectric material layers. In one embodiment, the vertical semiconductor channel 60 has a same material composition and a same thickness as the respective semiconductor material layer.
In one embodiment, the plurality of laterally bulging portions 78B are located only in the transition region 200, and are not located in the memory array region 100 or in the contact region 300. In this embodiment, the plurality of interlaced laterally bulging portions 78B and neck portions 78N are located between a respective pair of straight surface segments 78S that extend along the first horizontal direction hd1 in the memory array region 100 and in the contact region 300. In another embodiment, the plurality of laterally bulging portions are also located within the memory array region 100.
In one embodiment, the plurality of laterally bulging portions 78B has a uniform pitch along the first horizontal direction hd1, and each of the plurality of laterally bulging portions has the second width w2 which is variable along the second horizontal direction hd2, and a pair of laterally convex surface segments that are laterally spaced from each other along the second horizontal direction hd2.
In one embodiment, each of the plurality of laterally bulging portions 78B comprises four laterally convex surface segments that are laterally spaced from each other and that do not directly contact each other. In one embodiment, each of the plurality of laterally bulging portions comprises a respective uniform width portion having a second width w2.
In one embodiment, the lateral isolation trench fill structure (74, 76) comprises an insulating spacer 74 and a conductive fill structure 76 that is laterally surrounded by the insulating spacer 74. In one embodiment, the conductive fill structure 76 comprises discrete airgaps 767 located in middle of the laterally bulging portions 78B and in middle of the neck portions 78N; and the discrete airgaps 767 are closed off and do not continue through interface regions between the laterally bulging portions 78B and the neck portions 78N along the first horizontal direction hd1.
In one embodiment, the insulating spacer 74 comprises: a pair of outer lengthwise sidewalls each comprising a plurality of laterally-convex surface segments that are interlaced with a plurality of first laterally-straight surface segments; and a pair of inner lengthwise sidewalls each comprising a plurality of laterally-concave surface segments that are interlaced with a plurality of second laterally-straight surface segments.
The various embodiments of the present disclosure can be employed to provide enhanced structural support by forming lateral isolation trenches 79 having laterally bulging portions 79B, and by forming conductive fill structures 76 having portions that are free of voids (i.e., airgaps) at interfaces between the bulging portions 78B and the neck portions 78N.
Referring to
Generally, the areas in which the first-type support pillar structures 20A are formed may be the same or approximately the same across the second exemplary structure and the first exemplary structure. In one embodiment, a set of rows of first-type support pillar structures 20A can be located between two strip-shaped areas in which a neighboring pair of lateral isolation trenches are to be subsequently formed. Such a set of rows of first-type support pillar structures 20A may be arranged as a rectangular array of first-type support pillar structures 20A. In this case, the geometrical centers of the first-type support pillar structures 20A may be arranged in a rectangular array in a plan view.
Within a Cartesian coordinate system employing a first axis that is parallel to the first horizontal direction hd1 and a second axis that is parallel to the second horizontal direction hd2 and representing each coordinate with a combination of a first component and a second component, the centers of gravity of the two-dimensional array of first-type support pillar structures 20A may be contained with a set of first Euclidean planes EP1 that are laterally spaced from each other by integer multiples of the pillar-to-pillar pitch p_pp. In this case, the first Euclidean planes EP1 that contain locations of geometrical centers of the first-type support pillar structures 20A are represented by a first set of fixed values for the first component in the Cartesian coordinate system. In an illustrative example, if an (x, y, z) coordinate system employs an x-axis that is parallel to the first horizontal direction hd1 and employs a y-axis that is parallel to the second horizontal direction hd2, the first Euclidean planes EP1 that contain locations of geometrical centers of the first-type support pillar structures 20A are represented by a first set of fixed x values in the (x, y, z) coordinate system. In other words, each first Euclidean plane EP1 can be a set of all points having a respective fixed value for the value of the x coordinate, and thus, is perpendicular to the first horizontal direction hd1. In this case, each fixed value within the first set of fixed values can be offset among one another by integer multiples of the uniform pitch within each row of first-type support pillar structures, i.e., the pillar-to-pillar pitch p_pp. The geometrical centers of the first-type support pillar structures 20A within the rows first-type support pillar structures 20A may be located entirely within the first Euclidean planes EP1.
In one embodiment, the rows of first-type support pillar structures 20A may consist of only dielectric material or materials, such as silicon oxide. The vertically alternating sequence (32, 42) comprises a staircase region in which lateral extents of the continuous sacrificial material layers 42 vary (e.g., decrease) along the first horizontal direction hd1 with a vertical distance from a horizontal plane including the bottommost surface of the vertically alternating sequence (32, 42). The rows of first-type support pillar structures 20A are located in the staircase region of the vertically alternating sequence (32, 42). The maximum lateral dimension (such as a diameter) of each first-type support pillar structure 20A may be in a range from 100 nm to 600 nm, although lesser and greater lateral dimensions may also be employed. In contrast, the maximum lateral dimension (such as a diameter) of each memory opening fill structure 58 described in the first embodiment may be in a range from 100 nm to 300 nm, although lesser and greater lateral dimensions may also be employed. Thus, the maximum lateral dimension of the first-type support pillar structures 20A may be the same as or larger than the maximum lateral dimension of the memory opening fill structures 58.
Referring to
In second embodiment, at least one of the lateral isolation trenches 79 comprises a respective plurality of laterally bulging portions 79B that are interlaced along the first horizontal direction hd1 with the neck portions 79N and with the rows of first-type support pillar structures 20A. Each of the neck portions 79N adjoined to a respective pair of the laterally bulging portions 79B of the lateral isolation trench 79. Thus, at least one of the lateral isolation trenches 79 comprises a respective plurality of laterally bulging portions 79B that is interlaced along the first horizontal direction hd1 with a respective most proximal row of the rows of the first-type support pillar structures 20A. The plurality of laterally bulging portions 79B are laterally spaced along the second horizontal direction hd2 from the rows of first-type support pillar structures 20A, such as from the most proximal row of first-type support pillar structures 20A. In other words, each neck portion 79N of the lateral isolation trench 79 is located adjacent along the second horizontal direction hd2 to a respective one of the first-type support pillar structures 20A of the most proximal row of first-type support pillar structures 20A. In contrast, each of the lateral bulging portion 79B is located adjacent along the second horizontal direction hd2 to a space between respective two of the first-type support pillar structures 20A of the most proximal row of first-type support pillar structures 20A.
Within a Cartesian coordinate system employing a first axis that is parallel to the first horizontal direction hd1 and a second axis that is parallel to the second horizontal direction hd2 and representing each coordinate with a combination of a first component and a second component, and the first Euclidean planes EP1 that contain locations of geometrical centers of the most proximal row of first-type support pillar structures 20A are represented by a first set of fixed values for the first component in the Cartesian coordinate system, second Euclidean planes EP2 that contain locations of maxima for the variable width (i.e., the maxima of the laterally bulging portions 79B) are represented by a second set of fixed values for first component in the Cartesian coordinate system, and each fixed value within the second set of fixed values is offset from a fixed value within the first set of fixed values by a product of an odd number (e.g., one) and one half of the uniform pitch, which is the pillar-to-pillar pitch p_pp. Thus, a first Euclidean plane EP1 may be located midway between a neighboring pair of second Euclidean planes EP2, and a second Euclidean plane EP2 may be located midway between a neighboring pair of first Euclidean planes EP1.
In the second embodiment, the rows of first-type support pillar structures 20A may be arranged as rectangular arrays of first-type support pillar structures 20A that are aligned along the first horizontal direction hd1, and thus, are laterally offset from the memory array region 100 by a same lateral offset distance.
In the second embodiment, each of the plurality of neck portions 79N may have a uniform width which is a first width w1, and each of the laterally bulging portions 79B may have a maximum width which is a second width w2. The second width w2 may be greater than the first width w1. For example, the second width w2 may be greater than the first width w1 by a difference that is in a range from 50% to 150%, such as from 75% to 125%, of the maximum lateral dimension (such as a diameter) of at least one of the first-type support pillar structures 20A. In one embodiment, the second width w2 is greater than the first width w1 by more than the maximum lateral dimension (such as a diameter) of at least one of the first-type support pillar structures 20A.
In one embodiment, for at least one of the lateral isolation trenches 79, each neighboring pair of first-type support pillar structures 20A within the most proximal row of first-type support pillar structures 20A may be laterally spaced apart from each other along the first horizontal direction hd1 by a pillar-to-pillar spacing s_pp. In one embodiment, a minimum distance s_pt between the most proximal row of support pillar structures (such as first-type support pillar structures 20A) and the lateral isolation trench 79 may be less than the pillar-to-pillar spacing s_pp. In one embodiment, for at least one of the lateral isolation trenches 79, the plurality of laterally bulging portions 79B are more proximal to the most proximal row of first-type support pillar structures 20A than the plurality of neck regions 79N are to the most proximal row of first-type support pillar structures 20A. For example, each bulging portion 79B in a lateral isolation trench 79 is spaced by the distance s_pt from two closest first-type support pillar structures 20A in the most proximal row, while each neck portion 79N in the same lateral isolation trench 79 is spaced by a distance that is greater than s_pt from the closest first-type support pillar structures 20A in the most proximal row.
In one embodiment, at least one of the lateral isolation trenches 79 has a uniform width throughout within a region that is located between neighboring clusters of the memory opening fill structures 58 that are laterally spaced from each other by a respective lateral isolation trench 79.
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The second exemplary structure comprises a three-dimensional memory device. The three-dimensional memory device comprises: a pair of alternating stacks (32, 46), wherein each alternating stack (32, 46) within the pair of alternating stacks (32, 46) comprises insulating layers 32 and electrically conductive layers 46 that are interlaced along a vertical direction, and wherein the pair of alternating stacks (32, 46) are laterally spaced from each other by a lateral isolation trench 79 that laterally extends along a first horizontal direction hd1; memory openings 49 vertically extending through a respective one of the pair of alternating stacks (32, 46); memory opening fill structures 58 located in a respective one of the memory openings 49 and comprising a respective vertical stack of memory elements (which may comprise as portions of a memory material layer 54 located at levels of the electrically conductive layers 46) and a respective vertical semiconductor channel 60 and a respective vertical stack of memory elements; rows of support pillar structures (such as first-type support pillar structures 20A), wherein each row of the support pillar structures laterally extends along the first horizontal direction hd1 and vertically extends through a respective one of the pair of alternating stacks (32, 46); and a lateral isolation trench fill structure (74, 76) having a variable width along a second horizontal direction hd2 and located in the lateral isolation trench 79, the lateral isolation trench fill structure comprising: a plurality of neck portions 78N having a pair of straight sidewalls which extend along the first horizontal direction hd1 and having a first width w1 along the second horizontal direction hd2 that is perpendicular to the first horizontal direction; and a plurality of laterally bulging portions 78B having a second width w2 along the second horizontal direction hd2 that is greater than the first width w1, wherein the plurality of laterally bulging portions 78B is interlaced with the plurality of neck portions 78B along the first horizontal direction hd1.
In one embodiment, each row of the support pillar structures (such as first-type support pillar structures 20A) is extends along the first horizontal direction hd1 with a uniform pitch p_pp; and the variable width of the lateral isolation trench fill structure (74, 76) has a periodic undulation along the first horizontal direction hd1 with a periodicity that is the same as the uniform pitch p_pp.
In one embodiment, the lateral isolation trench fill structure (74, 76) is laterally spaced along the second horizontal direction hd2 from a most proximal row of the rows of the support pillar structures (such as first-type support pillar structures 20A).
In one embodiment, within a Cartesian coordinate system employing a first axis that is parallel to the first horizontal direction hd1 and a second axis that is parallel to the second horizontal direction hd2 and representing each coordinate with a combination of a first component and a second component, first Euclidean planes EP1 that contain locations of geometrical centers of the most proximal row of support pillar structures (such as first-type support pillar structures 20A) are represented by a first set of fixed values for the first component in the Cartesian coordinate system, second Euclidean planes EP2 that contain locations of maxima for the variable width are represented by a second set of fixed values for first component in the Cartesian coordinate system, and each fixed value within the second set of fixed values is offset from a fixed value within the first set of fixed values by a product of an odd number and one half of the uniform pitch p_pp. In one embodiment, geometrical centers of the support pillar structures (such as first-type support pillar structures 20A) within the rows of support pillar structures (such as first-type support pillar structures 20A) are located entirely within the first Euclidean planes EP1.
In one embodiment, each of the plurality of neck portions has a uniform width which is the first width w1; and each of the laterally bulging portions has a maximum width which is the second width w2. In one embodiment the second width w2 of greater than the first width w1 by a difference that is in a range from 50% to 150% of a maximum lateral dimension (such as a diameter) of one of the support pillar structures (such as the first-type support pillar structures 20A).
In one embodiment, each neighboring pair of support pillar structures (such as first-type support pillar structures 20A) within the most proximal row of support pillar structures (such as first-type support pillar structures 20A) is laterally spaced apart from each other along the first horizontal direction hd1 by a pillar-to-pillar spacing s_pp; and a minimum distance between the most proximal row of support pillar structures (such as first-type support pillar structures 20A) and the lateral isolation trench fill structure (74, 76) is less than the pillar-to-pillar spacing s_pp. In one embodiment, the plurality of laterally bulging portions 78B are more proximal to the most proximal row of support pillar structures (such as first-type support pillar structures 20A) than the plurality of neck regions 78N are to the most proximal row of support pillar structures (such as first-type support pillar structures 20A).
In one embodiment, each of the plurality of bulging portions 78B protrude along the second horizontal direction hd2 into the space between two adjacent support pillar structures 20A in the most proximal row of support pillar structures. In one embodiment, the plurality of laterally bulging portions 78B are more proximal to the most proximal row of the support pillar structures 20A than the plurality of neck regions 78N are to the most proximal row of support pillar structures 20A.
In one embodiment, the rows of support pillar structures (such as first-type support pillar structures 20A) contain only dielectric material or dielectric materials. In one embodiment, the rows of support pillar structures (such as first-type support pillar structures 20A) are arranged as two rectangular arrays of support pillar structures (such as first-type support pillar structures 20A) located within a respective alternating stack (32, 46) of the pair of alternating stacks (32, 46).
In one embodiment, each alternating stack (32, 46) of the pair of alternating stacks (32, 46) comprises a respective staircase region in which lateral extents of electrically conductive layers 46 within said each alternating stack (32, 46) along the first horizontal direction hd1 vary with a vertical distance from a horizontal plane including bottommost surfaces of the pair of alternating stacks (32, 46); and the rows of support pillar structures (such as first-type support pillar structures 20A) are located in the staircase regions of the pair of alternating stacks (32, 46). In one embodiment, the lateral isolation trench fill structure (74, 76) has a uniform width throughout within a region that is located between a first subset of the memory opening fill structures 58 vertically extending through a first alternating stack (32, 46) within the pair of alternating stacks (32, 46) and a second subset of the memory opening fill structures 58 vertically extending through a second alternating stack (32, 46) within the pair of alternating stacks (32, 46).
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Subsequently, the processing steps described with reference to
The laterally bulging portions 78B of the lateral isolation trench fill structures (74, 76) in the second embodiment of the second exemplary structure can reduce mechanical distortion of the three-dimensional memory array in the contact region 300. Specifically, the bulging portions 78B protrude along the second horizontal direction hd2 into the space between two adjacent first-type support pillar structures 20A in the most proximal row. This reduces the distance between the lateral isolation trench fill structure (74, 76) and the closest first-type support pillar structures 20A in the most proximal row. This reduces deflection of the alternating stacks (32, 46) along the second horizontal direction hd2 and tilting of the alternating stacks into the lateral isolation trenches 79 during fabrication. Thus, the mechanical stability and reliability of the three-dimensional memory array may be enhanced.
Referring to
Each of the first-type support openings 19A may have a respective circular or elliptical horizontal cross-sectional shape. Each of the second-type support openings 19B that are formed in the transition region 200 may have a respective circular or elliptical horizontal cross-sectional shape. Each of the third-type support openings 19C may have a respective circular or elliptical horizontal cross-sectional shape.
In one embodiment shown in
The multiple rows of the first-type support openings 19A may be spaced from each other along the second horizontal direction hd2. In one embodiment, a group of rows of first-type support openings 19A may be arranged as a two-dimensional periodic array, such as a rectangular periodic array, of first-type support openings 19A.
In one embodiment, the third-type support openings 19C may be formed in rows that also laterally extend along the first horizontal direction hd1. Each row of third-type support openings 19C may be formed around an area in which a lateral isolation trench is to be subsequently formed. In one embodiment, each row of third-type support openings 19C may be formed between a neighboring pair of rectangular arrays of first-type support openings 19A. In one embodiment, third-type support openings 19C within each row of third-type support openings 19C may be arranged with a second periodicity along the first horizontal direction hd1. The second periodicity of the third-type support openings 19C within each row corresponds to a center-to-center distance between geometrical centers of a neighboring pair of third-type support openings 19C, and is herein referred to as a second center-to-center pitch pcc2.
In one embodiment, the horizontal cross-sectional shape of each third-type support opening 19C may be a circular shape having a uniform radius of curvature, which equals the radius of the circular shape. In one embodiment, each first-type support opening 19A may have a first maximum lateral dimension (such as a diameter) in a horizontal cross-sectional view, and the radius of curvature of each third-type support opening 19C may be in a range from 50% to 200%, such as from 75% to 150%, of one half of the first maximum lateral dimension. In one embodiment, the radius of curvature of each third-type support opening 19C may be the same as one half of the first maximum lateral dimension.
In one embodiment, each row of the first-type support openings 19A may have the first center-to-center pitch pcc1 along the first horizontal direction hd1, and each row of the third-type support openings 19C may have a second center-to-center pitch pcc2 along the first horizontal direction hd1 that equals the first center-to-center pitch pcc1. In one embodiment, each row of third-type support openings 19C may be laterally offset from a most proximal row of first-type support openings 19A by one half of the second center-to-center pitch pcc2 which equals the first center-to-center pitch pcc1. In one embodiment, the center of gravity of one of the third-type support opening 19C may be laterally offset from a center of gravity of a most proximal first-type openings 19A among the first-type support openings 19A by a lateral offset distance that equals one half of the first center-to-center pitch pcc1, which equals one half of the second center-to-center pitch pcc2. As used herein, a center of gravity of a volume refers to the center of gravity of a hypothetical object that fills the volume and having a uniform density throughout. The center of gravity of a volume has a set of Cartesian coordinates which is the average of all Cartesian coordinates of the volume.
In one embodiment, each neighboring pair of first-type support openings 19A that are laterally spaced from each other along the first horizontal direction hd1 may be spaced from each other by a first spacing s1. Each neighboring pair of first-type support openings 19A that are laterally spaced from each other along the second horizontal direction hd2 may be spaced from each other by a second spacing s2. Neighboring pairs of a first-type support opening 19A and an third-type support opening 19C may be spaced from each other by a third spacing s3. The first spacing s1 may be in a range from 20 nm to 300 nm, such as from 40 nm to 150 nm, although lesser and greater spacings may also be employed. The ratio of the second spacing s2 to the first spacing s1 may be in a range from 0.5 to 2.0, such as from 0.75 to 1.5, although lesser and greater ratios may also be employed. The ratio of the third spacing s3 to the first spacing s1 may be in a range from 0.5 to 2.0, such as from 0.75 to 1.5, although lesser and greater ratios may also be employed.
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Each of the first-type support pillar structures 20A and the third-type support pillar structures 20C comprise has a respective circular or elliptical horizontal cross-sectional shape. In one embodiment, each horizontal cross-sectional shape of the first-type support pillar structures 20A and the third-type support pillar structures 20C may have a uniform radius of curvature that equals the radius of the respective horizontal cross-sectional shape. In one embodiment, each of the first-type support pillar structures 20A may have a first maximum lateral dimension in a horizontal cross-sectional view. In one embodiment, each radius of curvature of the first-type support pillar structures 20A and the third-type support pillar structures 20C may be in a range from 50% to 200% of one half of the first maximum lateral dimension.
In one embodiment, the first-type support pillar structures 20A may be arranged in multiple rows that laterally extend along the first horizontal direction hd1, and the third-type support pillar structures 20C may be arranged in rows that laterally extend along the first horizontal direction hd1. In one embodiment, the first-type support pillar structures 20A may be arranged in rectangular periodic arrays, and the third-type support pillar structures 20C may be arranged in rows located between a respective neighboring pair of rectangular periodic arrays of first-type support pillar structures 20A. In one embodiment, each row of the first-type support pillar structures 20A has the first center-to-center pitch pcc1 along the first horizontal direction hd1, and each row of the third-type support pillar structures 20C has the second center-to-center pitch pcc2 along the first horizontal direction hd1 that equals the first center-to-center pitch pcc1.
In one embodiment, a center of gravity of one of the third-type support pillar structures 20C may be laterally offset from a center of gravity of a most proximal first-type support pillar structure 20A among the first-type support pillar structures 20A by a lateral offset distance that equals one half of the first center-to-center pitch pcc1.
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A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80, and can be lithographically patterned to form various openings therein. The openings in the photoresist layer comprise elongated laterally-undulating openings that generally extend along the first horizontal direction hd1 in the strip regions located between neighboring clusters of memory opening fill structures 58.
An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42) (i.e., the vertically alternating sequence (32, 42)), and the stepped dielectric material portion 65, and into the in-process source-level material layers 110′ (if present). Lateral isolation trenches 79 can be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the in-process source-level material layers 110′ (if present). The lateral isolation trenches 79 vertically extend through each layer within the alternating stack (32, 42) and into an upper portion of a semiconductor material layer (which may be located in the in-process source-level material layers 110′ or which may comprise a top portion of the carrier substrate 9 if the in-process source-level material layers 110′ are omitted). The lateral isolation trenches 79 laterally extend along the first horizontal direction hd1 (e.g., a word line direction). In one embodiment, the lower source-level semiconductor layer 112 may be physically exposed underneath each lateral isolation trench 79.
In one embodiment, each lateral isolation trench 79 may have a uniform width along the second horizontal direction hd2. The uniform width is less than the lateral dimension of each third-type support pillar structure 20C. Each row of third-type support pillar structures 20C can be cut by a respective lateral isolation trench 79 into a respective pair of rows of remaining portions of the dielectric material of the third-type support pillar structures 20C. The lateral isolation trenches 79 can be formed through the retro-stepped dielectric material portion 65 and the alternating stack (32, 42), and through rows of third-type support pillar structures 20C while the first-type support pillar structures 20A are not etched or cut during formation of the lateral isolation trenches 79. Thus, the first-type support pillar structures 20A are not changed during formation of the lateral isolation trenches 79.
Each remaining portion of the third-type support pillar structures 20C is herein referred to as an auxiliary support pillar structure 20P. In one embodiment, the first-type support pillar structures 20A are arranged in multiple rows that laterally extend along the first horizontal direction hd1. In one embodiment, each row of third-type support pillar structures 20C can be arranged along the first horizontal direction hd1. In one embodiment, each third-type support pillar structure 20C within a row of third-type support pillar structures 20C comprises a respective center portion that is etched through during formation of the lateral isolation trenches 79 and a respective pair of peripheral portions that remain after formation of the lateral isolation trenches 79 constitutes a respective pair of auxiliary support pillar structures 20P.
In one embodiment shown in
In one embodiment, each of the first-type support pillar structures 20A has a respective circular or elliptical horizontal cross-sectional shape. In one embodiment, each of the auxiliary support pillar structures 20P may have a respective horizontal cross-sectional shape of a sector of a circle or an ellipse. Further, each of the auxiliary support pillar structures 20P may have a planar vertically-extending surface 20S that is exposed to a respective lateral isolation trench 79 upon formation of the lateral isolation trenches 79. In one embodiment, a curved portion of the horizontal cross-sectional shape of the sector may have a radius of curvature that is greater than one half of a width of each lateral isolation trench 79. In one embodiment, the first-type support pillar structures 20A may have a first maximum lateral dimension in a horizontal cross-sectional view, and the radius of curvature is in a range from 50% to 200% of one half of the first maximum lateral dimension.
In one embodiment, the first-type support pillar structures 20A may be arranged in multiple rows that laterally extend along the first horizontal direction hd1, and the auxiliary support pillar structures 20P may be arranged in two rows that laterally extend along the first horizontal direction hd1. In one embodiment, the two rows of auxiliary support pillar structures 20P are laterally spaced from each other by a lateral spacing that equals the width of the lateral isolation trenches 79.
In one embodiment, the two rows of auxiliary support pillar structures 20P may be formed around each lateral isolation trench 79. In one embodiment, the two rows of the auxiliary support pillar structures 20P comprise a first row and a second row. In one embodiment, centers of curvature for a curved sidewall of an auxiliary support pillar structure 20P within the first row are located within a vertical line passing through the lateral isolation trench 79, and centers of curvature for a curved sidewall of another auxiliary support pillar structure 20P within the second row are located within the vertical line. The two auxiliary support pillar structures 20P that share the same vertical line as the centers of curvature for the curved sidewalls can be remaining portions of the same third-type support pillar structure 20C.
If the third-type support pillar structures 20C are arranged in the first or second configurations shown in
If the third-type support pillar structures 20C are arranged in the second configuration shown in
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At least one metallic material can be conformally deposited in remaining volumes of the lateral isolation trenches 79 on the physically exposed surfaces of the insulating spacers 74, the source-level material layers 110, and the contact-level dielectric layer 80. The at least one metallic material may comprise at least one metallic nitride barrier material and at least one metal fill material. Excess portions of the at least one metallic material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the at least one metallic material located within a respective lateral isolation trench 79 constitutes a conductive fill structure 76. Each contiguous combination of an insulating spacer 74 and a conductive fill structure 76 constitutes a lateral isolation trench fill structure (74, 76).
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At least one conductive material, such as a combination of a metallic barrier material and a metallic fill material, can be deposited in the drain contact via cavities and the layer contact via cavities. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which may employ a recess etch process and/or a chemical mechanical polishing process. Remaining portions of the at least one conductive material that fill the drain contact via cavities constitute drain contact via structures 88 contacting a top surface of a respective one of the drain regions 63. Remaining portions of the at least one conductive material that fill the layer contact via cavities constitute layer contact via structures 86 contacting a top surface of a respective one of the electrically conductive layers 46.
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Referring to all drawings and according to various embodiments of the present disclosure, a memory device comprises: a pair of alternating stacks (32, 46) of insulating layers 32 and electrically conductive layers 46, wherein the pair of alternating stacks (32, 46) are laterally spaced from each other by a lateral isolation trench 79 that laterally extends along a first horizontal direction hd1; memory openings 49 vertically extending through a respective one of the pair of alternating stacks (32, 46); memory opening fill structures 58 located in the memory openings 49, wherein each of the memory opening fill structures 58 comprises a respective vertical stack of memory elements (e.g., portions of the memory film 50) and a vertical semiconductor channel 60; a lateral isolation trench fill structure (74, 76) located in the lateral isolation trench 79; and support pillar structures 20 vertically extending through a respective one of the pair of alternating stacks (32, 46), wherein the support pillar structures 20 comprise first-type support pillar structures 20A each having a respective circular or elliptical horizontal cross-sectional shape, and auxiliary support pillar structures 20P each having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically-extending surface 20S.
In one embodiment, a curved portion of the horizontal cross-sectional shape of the sector has a radius of curvature that is greater than one half of a width of the lateral isolation trench fill structure (74, 76). In one embodiment, the first-type support pillar structures 20A have a first maximum lateral dimension in a horizontal cross-sectional view; and the radius of curvature is in a range from 50% to 200% of one half of the first maximum lateral dimension.
In one embodiment, the first-type support pillar structures 20A are arranged in multiple rows that laterally extend along the first horizontal direction hd1; and the auxiliary support pillar structures 20P are arranged in two rows that laterally extend along the first horizontal direction hd1. In one embodiment, the two rows of auxiliary support pillar structures 20P are laterally spaced from each other by a lateral spacing that equals a width of the lateral isolation trench fill structure (74, 76).
In one embodiment, each row of the first-type support pillar structures 20A has a first center-to-center pitch pcc1 along the first horizontal direction hd1; and each row of the auxiliary support pillar structures 20P has a second center-to-center pitch pcc2 along the first horizontal direction hd1 that equals the first center-to-center pitch pcc1. In one embodiment, a center of gravity of one of the auxiliary support pillar structures 20P is laterally offset from a center of gravity of a most proximal first-type support pillar structure 20 among the first-type support pillar structures 20A by a lateral offset distance that equals one half of the first center-to-center pitch pcc1.
In one embodiment, the two rows of the auxiliary support pillar structures 20P comprise a first row and a second row; centers of curvature for a curved sidewall of an auxiliary support pillar structure 20 within the first row are located within a vertical line passing through the lateral trench fill structure; and centers of curvature for a curved sidewall of another auxiliary support pillar structure 20 within the second row are located within the vertical line.
In one embodiment, a first alternating stack (32, 46) within the pair of alternating stacks (32, 46) comprises first stepped surfaces; a second alternating stack (32, 46) within the pair of alternating stacks (32, 46) comprises second stepped surfaces; and each of the support pillar structures 20 vertically extends through the first stepped surfaces or the second stepped surfaces. In one embodiment, the memory device further comprises: a first retro-stepped dielectric material portion 65 overlying the first stepped surfaces; a second retro-stepped dielectric material portion 65 overlying the second stepped surfaces; first layer contact via structures 86 vertically extending through the first retro-stepped dielectric material portion 65 and contacting a respective electrically conductive layer within the first alternating stack (32, 46); and second layer contact via structures 86 vertically extending through the second retro-stepped dielectric material portion 65 and contacting a respective electrically conductive layer within the second alternating stack (32, 46).
In one embodiment, the planar vertically-extending surface 20S extends parallel to at least a portion of a sidewall (e.g., sidewall of the spacer 74 at levels of the insulating layers 32) of the lateral isolation trench fill structure (74, 76). In one embodiment shown in
In one embodiment, the memory device comprises at least one source layer 114 underlying the pair of alternating stacks (32, 46), wherein each of the memory opening fill structures 58 comprises a respective vertical semiconductor channel 60 having a bottom end that is electrically connected to a respective one of the at least one source layer 114. In one embodiment, the pair of alternating stacks (32, 46), the memory opening fill structures 58, the lateral isolation trench fill structure (74, 76), and the support pillar structures 20 are located in a memory die 900; and the memory die 900 is bonded to a logic die 700 including a peripheral circuit configured to control operation of the electrically conductive layers 46 and the vertical stacks of memory elements.
In one embodiment, each of the memory opening fill structures 58 comprises a memory film 50 and a vertical semiconductor channel 60; the memory film 50 comprises a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56; and portions of the charge storage layer 54 located at levels of the electrically conductive layers 46 comprise the vertical stack of memory elements.
The various embodiments of the present disclosure may be employed to provide additional auxiliary support pillar structures 20P which can be employed to provide mechanical support to a three-dimensional memory device during replacement of sacrificial material layers 42 with electrically conductive layers 46, and to reduce or prevent deflection of the electrically conductive layers 46 at the diagonal between the support pillar structures 20 and the lateral isolation trench 79. Furthermore, unintended vertical penetration of the lateral isolation trench 79 into areas located under the auxiliary support pillar structures 20P is also reduced. Still further, additional process steps are not required to form the auxiliary support pillar structures 20P, thus reducing the number of process steps.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Whenever two or more elements are listed as alternatives in a same paragraph of in different paragraphs, a Markush group including a listing of the two or more elements is also impliedly disclosed. Whenever the auxiliary verb “can” is employed in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device can provide an equivalent result. As such, the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. If publications, patent applications, and/or patents are cited herein, each of such documents is incorporated herein by reference in their entirety.
This application is a continuation-in-part (CIP) application of U.S. patent application Ser. No. 18/508,638 filed on Nov. 14, 2023, which is a continuation-in-part application of U.S. patent application Ser. No. 18/477,907 filed on Sep. 29, 2023, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18508638 | Nov 2023 | US |
| Child | 18421417 | US | |
| Parent | 18477907 | Sep 2023 | US |
| Child | 18508638 | US |
