Patent Application
20240306392
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including coaxial double contact via structures and methods for manufacturing the same.
Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a device structure comprises: an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise a vertically neighboring pair of a first-type electrically conductive layer and a second-type electrically conductive layer that overlies the first-type electrically conductive layer; a dielectric material portion overlying the alternating stack; memory openings vertically extending through the alternating stack; memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; and a coaxial double contact via structure vertically extending through the dielectric material portion and comprising: an inner layer contact via structure contacting the first-type electrically conductive layer; at least one insulating spacer layer comprising a respective tubular insulating portion that laterally surrounds the inner layer contact via structure; and an outer layer contact via structure comprising a tubular conductive portion that laterally surrounds the at least one insulating spacer layer and contacting the second-type electrically conductive layer.
According to another aspect of the present disclosure, a method of forming a device structure comprises: forming a combination of an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise a vertically neighboring pair of a first-type electrically conductive layer and a second-type electrically conductive layer that overlies the first-type electrically conductive layer; forming a dielectric material portion over the alternating stack; forming a memory opening through the alternating stack; forming a memory opening fill structure comprising a vertical stack of memory elements and a vertical semiconductor channel in the memory opening; and forming a coaxial double contact via structure comprising a combination of an outer layer contact via structure, at least one insulating spacer layer, and an inner layer contact via structure through the retro-stepped dielectric material portion and on the first-type electrically conductive layer and the second-type electrically conductive layer such that the inner layer contact via structure contacts the first-type electrically conductive layer, the at least one insulating spacer layer laterally surrounds the inner layer contact via structure, and the outer layer contact via structure laterally surrounds the at least one insulating spacer layer and contacts the second-type electrically conductive layer.
Embodiments of the present disclosure are directed to double wall contact via structures for a three-dimensional memory device and methods for manufacturing the same. Embodiments of the disclosure can be employed to form various structures including a three-dimensional memory structure, non-limiting examples of which include three-dimensional NAND memory devices.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, an element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, an element is located “directly on” a second element if there exist a physical contact between a surface of the element and a surface of the second element. As used herein, an element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1×10−5 S/m to 1×105 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1×10−5 S/m to 1 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1 S/m to 1×107 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to provide electrical conductivity greater than 1×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1×10−5 S/m to 1×107 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
Referring to
An alternating stack of first material layers and second material layers can be formed over the carrier substrate 9. The first material layers may be insulating layers, and the second material layers may be spacer material layers. In one embodiment, the spacer material layers may comprise sacrificial material layers 42. In this case, an alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 can be formed over the carrier substrate 9. The insulating layers 32 comprise an insulating material such as undoped silicate glass or a doped silicate glass, and the sacrificial material layers 42 comprise a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layers 32 (i.e., the first material layers) may comprise silicon oxide layers, and the sacrificial material layers 42 (i.e., the second material layers) may comprise silicon nitride layers.
The alternating stack (32, 42) may comprise multiple repetitions of a unit layer stack including an insulating layer 32 and a sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in a range from 8 to 1,024, such as from 32 to 256, although lesser and greater number of repetitions may also be employed. The topmost one of the insulating layers 32 is hereafter referred to as a topmost insulating layer 32T. The bottommost one of the insulating layers 32 (i.e., an insulating layer 32 that is most proximal to the carrier substrate 9) is herein referred to as a bottommost insulating layer 32B.
Each of the insulating layers 32 other than the topmost insulating layer 32T may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each of the sacrificial material layers 42 may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the topmost insulating layer 32T may have a thickness of about one half of the thickness of other insulating layers 32.
The exemplary structure comprises a memory array region 100 in which a three-dimensional array of memory elements is to be subsequently formed, and a contact region 300 in which layer contact via structures contacting word lines are to be subsequently formed.
While an embodiment is described in which the spacer material layers are formed as sacrificial material layers 42, the spacer material layers may be formed as electrically conductive layers in an alternative embodiment. Generally, spacer material layers of the present disclosure may be formed as, or may be subsequently replaced at least partly with, electrically conductive layers.
Referring to
Each sacrificial material layer 42 other than a topmost sacrificial material layer 42 within the alternating stack (32, 42) laterally extends farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in each staircase. Each contiguous set of stepped surfaces of the alternating stack (32, 42) within a respective staircase continuously extend from a bottommost layer within the alternating stack (32, 42) (such as the bottommost insulating layer 32B) to a topmost layer within the alternating stack (32, 42) (such as the topmost insulating layer 32T).
A stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a “stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases or decreases stepwise as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may, or may not, be doped with dopants such as B, P, and/or F.
Referring to
Each of the memory openings 49 and the support openings 19 can vertically extend into the carrier substrate 9. In one embodiment, bottom surfaces of the memory openings 49 and the support openings 19 may be formed at or below the top surface of the carrier substrate 9. The memory openings 49 may have a diameter in a range from 60 nm to 400 nm, such as from 120 nm to 300 nm, although lesser and greater diameters may be employed. The support openings 19 may have a diameter in a range from 60 nm to 400 nm, such as from 120 nm to 300 nm, although lesser and greater diameters may be employed.
Each cluster of memory openings 49 (which corresponds to an area of a memory block) may comprise a plurality of rows of memory openings 49. Each row of memory openings 49 may comprise a plurality of memory openings 49 that are arranged along the first horizontal direction hd1 (which may be a word line direction) with a uniform pitch. The rows of memory openings 49 may be laterally spaced from each other along the second horizontal direction hd2 (which may be a bit line direction), which may be perpendicular to the first horizontal direction hd1. In one embodiment, each cluster of memory openings 49 may be formed as a two-dimensional periodic array of memory openings 49.
Referring to
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A dielectric fill material, such as silicon oxide, can be deposited in the support openings 19 by a conformal deposition process. Excess portions of the dielectric fill material can be removed from above the top surface of the topmost insulating layer 32T, for example, by a recess etch process. Each portion of the dielectric fill material that fills a respective support opening 19 constitutes a support pillar structure 20, which can be employed to provide structural support to the insulating layers 32 and the stepped dielectric material portion 65 during replacement of the sacrificial material layers 42 with electrically conductive layers. Alternatively, the support openings 19 can be formed at a later step at the same time as the memory openings, and the support pillar structures 20 can be formed in the support openings 19 at the same time as the memory opening fill structures are formed in the memory openings, as will be described below.
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Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel material layer 60L can be removed from above the horizontal plane including the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel 60.
Each portion of the layer stack including the memory material layer 54 that remains in a respective memory opening 49 constitutes a memory film 50. In one embodiment, a memory film 50 may comprise an optional blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each contiguous combination of a memory film 50 and a vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 comprises a respective vertical stack of memory elements, which may comprise portions of the memory material layer 54 located at levels of the sacrificial material layers 42, or generally speaking, at levels of spacer material layers that may be formed as, or may be subsequently replaced at least partly with, electrically conductive layers.
In the alternative embodiment, the support pillar structures 20 may be formed in the support openings 19 at the same time as the memory opening fill structures 58 are formed in the memory openings 49. In this case, the support pillar structures 20 comprise the same materials as the memory opening fill structures 58.
An anneal process can be performed to activate electrical dopants in the drain region 63 and in the vertical semiconductor channel 60. In this case, any amorphous semiconductor material in the vertical semiconductor channel 60 is converted into a polycrystalline semiconductor material. In one embodiment, grains within the vertical semiconductor channel 60 may extends predominantly along a respective local direction that is perpendicular to a respective proximal portion of an inner sidewall of the vertical semiconductor channel 60 and perpendicular to a respective proximal portion of an outer sidewall of the vertical semiconductor channel 60. As used herein, the grains extend predominantly along a specific direction if more than 50% of the drains extend along the specific direction.
Referring to
Thus, an alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 is formed over a substrate (such as a carrier substrate 9). The spacer material layers are formed as or are subsequently replaced with electrically conductive layers. Memory openings 49 are formed through the alternating stack (32, 42). Memory opening fill structures 58 are formed in the memory openings 49. Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60 that is laterally surrounded by the respective memory film 50. The memory opening fill structures 58 are arranged in rows laterally extending along a first horizontal direction hd1, and the rows are laterally spaced apart from each other along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. Each of the memory opening fill structures 58 comprises a vertical stack of memory elements (which may comprise portions of a memory film 50 located at levels of the sacrificial material layers 42), and a respective drain region 63.
Referring to
A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80, and can be lithographically patterned to form elongated openings that laterally extend along the first horizontal direction hd1 between neighboring clusters of memory opening fill structures 58. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42), and the stepped dielectric material portion 65, and to a top surface of the carrier substrate 9. Lateral isolation trenches 79 laterally extending along the first horizontal direction hd1 can be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the contact-level dielectric layer 80. Each of the lateral isolation trenches 79 may comprise a respective pair of lengthwise sidewalls that are parallel to the first horizontal direction hd1 and vertically extend from the top surface of the contact-level dielectric layer 80 to the top surface of the carrier substrate 9. A surface of the carrier substrate 9 can be physically exposed underneath each lateral isolation trench 79. The photoresist layer can be subsequently removed, for example, by ashing.
Referring to
The etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the lateral isolation trenches 79. For example, if the sacrificial material layers 42 include silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structures 55 provide structural support while the lateral recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.
Each lateral recess 43 can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess 43 can be greater than the height of the lateral recess 43. A plurality of lateral recesses 43 can be formed in the volumes from which the second material of the sacrificial material layers 42 is removed.
Each of the plurality of lateral recesses 43 can extend substantially parallel to the top surface of the carrier substrate 9. A lateral recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32. In one embodiment, each lateral recess 43 can have a uniform height throughout.
Referring to
At least one conductive material can be deposited in the lateral recesses 43 by providing at least one reactant gas into the lateral recesses 43 through the lateral isolation trenches 79. A metallic barrier layer can be deposited in the lateral recesses 43. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer can consist essentially of a conductive metal nitride such as TiN.
A metal fill material is deposited in the plurality of lateral recesses 43, on the sidewalls of each lateral isolation trench 79, and over the top surface of the contact-level dielectric layer 80 to form a metallic fill material layer. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating layers 32 and the memory stack structures 55 by the metallic barrier layer, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.
A plurality of electrically conductive layers 46 can be formed in the plurality of lateral recesses 43, and a continuous metallic material layer can be formed on the sidewalls of each lateral isolation trench 79 and over the contact-level dielectric layer 80. Each electrically conductive layer 46 includes a portion of the metallic barrier layer and a portion of the metallic fill material layer that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers 32. The continuous metallic material layer includes a continuous portion of the metallic barrier layer and a continuous portion of the metallic fill material layer that are located in the lateral isolation trenches 79 or above the contact-level dielectric layer 80.
The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each lateral isolation trench 79 and from above the contact-level dielectric layer 80 by performing an isotropic etch process that etches the at least one conductive material of the continuous electrically conductive material layer. Each remaining portion of the deposited metallic material in the lateral recesses 43 constitutes an electrically conductive layer 46. Each electrically conductive layer 46 can be a conductive line structure. Thus, the sacrificial material layers 42 are replaced with the electrically conductive layers 46. Generally, the electrically conductive layers 46 can be formed by providing a metallic precursor gas into the lateral isolation trenches 79 and into the lateral recesses 43.
Each electrically conductive layer 46 may be embedded within a respective outer blocking dielectric layer 44, which may comprise a dielectric metal oxide material, such as aluminum oxide. Each outer blocking dielectric layer 44 may have a pair of horizontally-extending portions in contact with a respective one of the insulating layers 32, and a plurality of tubular portions laterally surrounding a respective one of the memory opening fill structures 58 and connecting the pair of horizontally-extending portions. The thickness of each outer blocking dielectric layer 44 may be in a range from 1 nm to 6 nm, although lesser and greater thicknesses may also be employed.
Generally, an assembly of an alternating stack (32, 46) and memory opening fill structures 58 can be formed. The alternating stack (32, 46) comprises a vertically alternating sequence of insulating layers 32 and electrically conductive layers 46. The memory opening fill structures 58 vertically extend through the alternating stack (32, 46). Each of the memory opening fill structures 58 comprises a respective vertical stack of memory elements (which may comprise portions of a memory material layer 54 located at levels of the electrically conductive layers 46), a respective vertical semiconductor channel 60, and a respective drain region 63. At least one uppermost electrically conductive layer 46 may comprise a drain side select gate electrode. At least one bottommost electrically conductive layer 46 may comprise a source side select gate electrode. The remaining electrically conductive layers 46 may comprise word lines. Each word line functions as a common control gate electrode for the plurality of vertical NAND strings (e.g., memory opening fill structures 58).
In one embodiment, the electrically conductive layers 46 may comprise first-type electrically conductive layers 461 and second-type electrically conductive layers 462. The first-type electrically conductive layers 461 comprise a first subset of the electrically conductive layers 46, and the second-type electrically conductive layers 462 comprise a second subset of the electrically conductive layers 46. The first subset of the electrically conductive layers 46 (i.e., layers 461) comprises each electrically conductive layer 46 that does not have any top surface segment that contacts the retro-stepped dielectric material portion 65 in case the outer blocking dielectric layers 44 are not present, or comprises each electrically conductive layer 46 that does not have any top surface segment that is vertically spaced from the retro-stepped dielectric material portion 65 by a distance that equals the thickness of a horizontally-extending portion of an outer blocking dielectric layer 44. The second subset of the electrically conductive layers 46 (i.e., layers 462) comprises each electrically conductive layer 46 that has a top surface segment that contacts the retro-stepped dielectric material portion 65 in case the outer blocking dielectric layers 44 are not present, or comprises each electrically conductive layer 46 that has a top surface segment that is vertically spaced from the retro-stepped dielectric material portion 65 by a distance that equals the thickness of a horizontally-extending portion of a backside blocking dielectric layer 44.
Generally, for each pair of electrically conductive layers 46 having a same lateral extent in a plan view (and thus, having the same area in the plan view), the pair of electrically conductive layers 46 may comprise a first-type electrically conductive layer 461 and a second-type electrically conductive layer 462. In one embodiment, the electrically conductive layers 46 may comprise at least one vertically neighboring pair of a first-type electrically conductive layer 461 and a second-type electrically conductive layer 462 that overlies the first-type electrically conductive layer 461. In one embodiment, the electrically conductive layers 46 may comprise multiple vertically neighboring pairs of a first-type electrically conductive layer 461 and a second-type electrically conductive layer 462 that overlie the first-type electrically conductive layer 461. In this case, the first-type electrically conductive layer 461 underlies the second-type electrically conductive layer 462 in each vertically neighboring pair of the first-type electrically conductive layer 461 and the second-type electrically conductive layer 462.
In one embodiment, upon sequentially numbering all of the electrically conductive layers 46 with positive integers beginning with 1 from bottom to top, each odd-numbered electrically conductive layer 46 may be a first-type electrically conductive layer 461, and each even-numbered electrically conductive layer 46 may be a second-type electrically conductive layer 462.
Referring to
An alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46 can be formed in a memory block area between each neighboring pair of lateral isolation trench fill structures 76. A first subset of the electrically conductive layers 46 can include at least one drain-select-level electrically conductive layer (i.e., at least one drain side select gate electrode) which is employed to activate or deactivate NAND strings (e.g., the memory opening fill structures 58 and adjacent portions of the electrically conductive layers 46) vertically extending through the alternating stack (32, 46). A second subset of the electrically conductive layers 46 that underlies the drain-select-level electrically conductive layers comprises word lines, which comprise control electrodes of the NAND strings. A subset of one or more bottommost electrically conductive layers 46 which underlies the word lines comprises source side select gate electrodes.
Referring to
A second photoresist layer (not shown) can be applied over the contact-level dielectric layer 80, and can be lithographically patterned to form openings in areas of the horizontally-extending surface segments of a stepped bottom surface of the retro-stepped dielectric material portion 65. A second anisotropic etch process can be performed to transfer the pattern of the openings in the second photoresist layer through the contact-level dielectric layer 80 and the retro-stepped dielectric material portion 65. The second anisotropic etch process may have an etch chemistry that etches the materials of the contact-level dielectric layer 80 and the retro-stepped dielectric material portion 65 selective to the material of the electrically conductive layers 46. The etch chemistry of the second anisotropic etch process may optionally also be selective to the material of the outer blocking dielectric layer 44. Layer contact via cavities 85 are formed in the volumes from which the materials of the contact-level dielectric layer 80 and the retro-stepped dielectric material portion 65 are removed.
A layer contact via cavity 85 can be formed for each second-type electrically conductive layer 462. Thus, each second-type electrically conductive layer 462 may have a horizontally-extending surface segment that is physically exposed to a respective overlying layer contact via cavity 85. Each first-type electrically conductive layer 461 underlies a respective second-type electrically conductive layer 462, which is an overlying and neighboring electrically conductive layer 46. Thus, the first-type electrically conductive layers 461 are not physically exposed to any layer contact via cavity 85. The total number of the layer contact via cavities 85 may be the same as the total number of second-type electrically conductive layers 462. The total number of the first-type electrically conductive layers 461 may be the same as, or may be less than, the total number of the second-type electrically conductive layers 462. In one embodiment, the total number of the first-type electrically conductive layers 461 may be the same as the total number of the second-type electrically conductive layers 462. In one embodiment, the height of at least a subset of the vertically extending surface segments of the stepped bottom surface of the retro-stepped dielectric material portion 65 may be twice the pitch of the periodicity along the vertical direction within the alternating stack (32, 46) (without consideration of the variations in the lateral extent of the layers within the alternating stack (32, 46)), i.e., twice the sum of the thickness of an insulating layer 32 and a spacing between a neighboring pair of insulating layers 32. The lateral dimension, such as a diameter, of each layer contact via cavity 85 may be in a range from 150 nm to 1,000 nm, such as from 300 nm to 600 nm, although lesser and greater dimensions may also be employed.
Referring to
An insulating layer 32, which is herein referred to as a first insulating layer 321, is interposed between each neighboring pair of an underlying first-type electrically conductive layer 461 and an overlying second-type electrically conductive layer 462. A top surface segment of a first insulating layer 321 can be physically exposed underneath each layer contact via cavity 85. The second photoresist layer can be subsequently removed, for example, by ashing.
Referring to
The outer metal layer 912 may comprise a metal such a W, Mo, Ti, Ta, Co, Ru, Cu, etc. The outer metal layer 912 may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, or a combination thereof. The thickness of the outer metal layer 912 may be in a range from 5% to 25%, such as from 10% to 20%, of the lateral dimension of each layer contact via cavity 85 as formed at the processing steps of
In one embodiment, the total thickness of the at least one outer metallic material layer (911, 912) may be greater than one half of the lateral dimension (such as the diameter) of each drain contact via cavity 87. In this case, the entire volume of each drain contact via cavity 87 can be filled with the at least one outer metallic material layer (911, 912).
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Thus, physically exposed surfaces of the at least one outer metallic material layer (911, 912) can be laterally recessed selective to the insulating layers 32 and the outer insulating spacer layer 81 by performing a selective isotropic etch process. An annular cavity 85A is formed in each volume from which an annular portion of the at least one outer metallic material layer (911, 912) is removed. Thus, the annular cavity 85A can be formed underneath each vertically-extending tubular portion of the outer insulating spacer layer 81 in a volume from which materials of the at least one outer metallic material layer (911, 912) are etched away. A cylindrical surface segment of the outer metal layer 912 and a cylindrical surface segment of the outer metallic barrier liner 911 can be physically exposed around each annular cavity 85A.
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The inner metallic barrier liner 921 may comprise a metallic barrier material such as TiN, TaN, WN, and/or MoN. The inner metallic barrier liner 921 may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the inner metallic barrier liner 921 may be in a range from 3 nm to 50 nm, although lesser and greater thicknesses may also be employed. The inner metallic barrier liner 921 can be formed directly on each physically exposed horizontal surface of the first-type electrically conductive layers 461, and on each inner cylindrical surface of the inner insulating spacer layer 82. The inner metallic barrier liner 921 may also be formed on physically exposed cylindrical surface segments of the outer blocking dielectric layers 44.
The inner metal layer 922 may comprise a metal, such a W, Mo, Ti, Ta, Co, Ru, Cu, etc. The inner metal layer 922 may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, or a combination thereof. The thickness of the inner metal layer 922 is selected to fill remaining volumes of the voids in the layer contact via cavities 85.
Referring to
Each coaxial double contact via structure 84 includes a combination of an outer layer contact via structure 91, at least one insulating spacer layer (81, 82), and an inner layer contact via structure 92. The coaxial double contact via structure 84 vertically extends through the retro-stepped dielectric material portion 65. Each coaxial double contact via structure 84 is formed on a respective first-type electrically conductive layer 461 and on a respective second-type electrically conductive layer 462 such that the inner layer contact via structure 92 contacts the respective first-type electrically conductive layer 461, the at least one insulating spacer layer (81, 82) laterally surrounds the inner layer contact via structure 92, and the outer layer contact via structure 91 laterally surrounds the at least one insulating spacer layer (81, 82) and contacts the respective second-type electrically conductive layer 462.
In summary, each coaxial double contact via structure 84 vertically extends through a dielectric material portion (such as the retro-stepped dielectric material portion 65) and comprises: an inner layer contact via structure 92 contacting a first-type electrically conductive layer 461; at least one insulating spacer layer (81, 82) comprising a respective tubular insulating portion that laterally surrounds the inner layer contact via structure 92; and an outer layer contact via structure 91 comprising a tubular conductive portion that laterally surrounds the at least one insulating spacer layer (81, 82) and contacting a second-type electrically conductive layer 462. In one embodiment, a bottom surface of the inner layer contact via structure 92 contacts a horizontal surface segment of the first-type electrically conductive layer 461. In one embodiment, the horizontal surface segment of the first-type electrically conductive layer 461 is vertically recessed relative a top surface of the first-type electrically conductive layer 461. In one embodiment, a cylindrical surface segment of an outer sidewall of the outer layer contact via structure 91 contacts a cylindrical surface of the second-type electrically conductive layer 462.
In one embodiment, a first insulating layer 321 of the insulating layers 32 is located between the first-type electrically conductive layer 461 and the second-type electrically conductive layer 462; and a cylindrical surface segment of a sidewall of the inner layer contact via structure 92 contacts a cylindrical sidewall surface of the first insulating layer 321. In one embodiment shown in
In one embodiment, the at least one insulating spacer layer (81, 82) comprises: an inner insulating spacer layer 82; and an outer insulating spacer layer 81 laterally surrounding the inner insulating spacer layer 82. In one embodiment, the inner insulating spacer layer 82 comprises a laterally protruding, annular bottom portion 82A having a cylindrical outer sidewall surface 183 that contacts a lower cylindrical surface segment of an inner sidewall of the outer layer contact via structure 91. In one embodiment, a bottommost surface 184 of the outer insulating spacer layer 81 contacts an annular top surface of the annular bottom portion 82A of the inner insulating spacer layer 82.
In one embodiment, a first insulating layer 321 of the insulating layers 32 is located between the first-type electrically conductive layer 461 and the second-type electrically conductive layer 462; and the outer layer contact via structure 91 comprises an outer metallic barrier liner 911 and an outer metal layer 912, wherein the outer metallic barrier liner 911 contacts a cylindrical sidewall of the second-type electrically conductive layer 462 and an annular surface of the first insulating layer 321. In one embodiment, the outer metal layer 912 contacts a cylindrical surface of the at least one insulating spacer layer (81, 82).
In one embodiment, the inner layer contact via structure 92 comprises an inner metallic barrier liner 921 and an inner metal layer 922, wherein the inner metallic barrier liner 921 contacts a planar surface of the first-type electrically conductive layer and a cylindrical surface of the at least one insulating spacer layer (81, 82). In one embodiment, a contact-level dielectric layer 80 overlies the alternating stack (32, 46) and the dielectric material portion (such as the retro-stepped dielectric material portion 65). A topmost surface of the inner layer contact via structure 92, a topmost surface of the at least one insulating spacer layer (81, 82), and a topmost surface of the outer layer contact via structure 91 are located within a horizontal plane including a top surface of the contact-level dielectric layer 80.
Referring to
Metal bonding pads, which are herein referred to as memory-side bonding pads 988, may be formed at the topmost level of the memory-side dielectric material layers 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structures 980 and various nodes of the three-dimensional memory array including the electrically conductive layers 46 and the memory opening fill structures 58. A memory die 900 can thus be provided.
The memory-side dielectric material layers 960 are formed over the alternating stacks (32, 46). The memory-side metal interconnect structures 980 are embedded in the memory-side dielectric material layers 960. The memory-side bonding pads 988 can be embedded within the memory-side dielectric material layers 960, and specifically, within the topmost layer among the memory-side dielectric material layers 960. The memory-side bonding pads 988 can be electrically connected to the memory-side metal interconnect structures 980.
In one embodiment, the memory die 900 may comprise: a three-dimensional memory array comprising an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46, a two-dimensional array of memory openings 49 vertically extending through the alternating stack (32, 46), and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel 60; and a two-dimensional array of contact via structures (such as the drain contact via structures 88) overlying the three-dimensional memory array and electrically connected to a respective one of the vertical semiconductor channels 60.
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In one embodiment, at least a terminal step of at least one removal process that is employed to remove the carrier substrate 9 may comprise a selective wet etch process that etches the material of the carrier substrate 9 (such as a semiconductor material of the carrier substrate 9) selective to dielectric materials of the memory films 50. In an illustrative example, if the carrier substrate 9 comprises a semiconductor material, the terminal step of the at least one removal process may comprise a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH). The entirety of the carrier substrate 9 can be removed by the selective wet etch process. Backside end surfaces of the support pillar structures 20 can be physically exposed upon removal of the carrier substrate 9.
A sequence of wet etch steps can be performed to sequentially remove portions of the memory film 50 that are exposed on the backside of the alternating stack (32, 46). For example, the blocking dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 (which may be, for example, a tunneling dielectric layer) of each memory film 50 can be removed from a region that is more distal from the bonding interface between the memory die 900 and the logic die 700 than a physically exposed planar surface of the bottommost insulating layer 32B is from the bonding interface.
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A trimmable photoresist layer 97 can be formed over the capping dielectric layer 93 (or over the at least one inner metallic material layer (921, 922)), and can be lithographically patterned into discrete trimmable photoresist material portions. Each discrete photoresist material portion of the trimmable photoresist layer 97 can cover the area of a respective underlying vertically-extending tubular portion of the at least one outer metallic material layer (911, 912). In one embodiment, the entire sidewall of each discrete trimmable photoresist material portion of the trimmable photoresist layer 97 may be laterally offset outward from a cylindrical vertical plane including an outer cylindrical sidewall of a tubular portion of the at least one outer metallic material layer (911, 912).
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In the second exemplary structure, the contact-level dielectric layer 80 overlies the alternating stack (32, 46) and a dielectric material portion (such as the retro-stepped dielectric material portion 65). Each insulating spacer layer (81, 82) comprises a laterally-extending portion (i.e., horizontal portion 280H) that overlies the contact-level dielectric layer 80. Each outer layer contact via structure 91 may comprise a respective annular flange portion (i.e., horizontal portion 91H underlying the respective laterally-extending annular portion (i.e., an annular flange portion) 280H of at least one insulating spacer layer (81, 82).
Each sidewall of an annular flange portion 280H of the at least one insulating spacer layer (81, 82) that overlies the contact-level dielectric layer 80 may be vertically coincident with a sidewall of an annular flange portion 91H of an underlying outer layer contact via structure 91. Each inner layer contact via structure 92 may comprise a respective annular flange portion 92H overlying a respective laterally-extending annular flange portion 280H of at least one insulating spacer layer (81, 82).
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Thus, physically exposed surfaces of the at least one outer metallic material layer (911, 912) can be laterally recessed selective to the insulating layers 32 and the outer insulating spacer layer 81 by performing a selective isotropic etch process. An annular cavity 85A is formed in each volume from which an annular portion of the at least one outer metallic material layer (911, 912) is removed. In summary, the annular cavity 85A can be formed underneath each vertically-extending tubular portion of the outer insulating spacer layer 81 in a volume from which materials of the at least one outer metallic material layer (911, 912) are etched. A cylindrical surface segment of the outer metal layer 912 and a cylindrical surface segment of the outer metallic barrier liner 911 can be physically exposed around each annular cavity 85A.
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The inner metal layer 922 may comprise a metal such a W, Mo, Ti, Ta, Co, Ru, Cu, etc. The inner metal layer 922 may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, or a combination thereof. The thickness of the inner metal layer 922 is selected to fill remaining volumes of the voids in the layer contact via cavities 85.
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Each coaxial double contact via structure 84 includes a combination of an outer layer contact via structure 91, at least one insulating spacer layer (81, 82), and an inner layer contact via structure 92, and vertically extends through the retro-stepped dielectric material portion 65. Each coaxial double contact via structure 84 is formed on a respective first-type electrically conductive layer 461 and on a respective second-type electrically conductive layer 462 such that the inner layer contact via structure 92 contacts the respective first-type electrically conductive layer 461, the at least one insulating spacer layer (81, 82) laterally surrounds the inner layer contact via structure 92, and the outer layer contact via structure 91 laterally surrounds the at least one insulating spacer layer (81, 82) and contacts the respective second-type electrically conductive layer 462.
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Referring collectively to all drawings and according to various aspects of the present disclosure a device structure comprises: an alternating stack (32, 46) of insulating layers 32 and electrically conductive layers 46, wherein the electrically conductive layers 46 comprise a vertically neighboring pair of a first-type electrically conductive layer 461 and a second-type electrically conductive layer 462 that overlies the first-type electrically conductive layer 461; a dielectric material portion (such as the retro-stepped dielectric material portion 65) overlying the alternating stack (32, 46); memory openings 49 vertically extending through the alternating stack (32, 46); memory opening fill structures 58 located in the memory openings 49, wherein each of the memory opening fill structures 58 comprises a respective vertical stack of memory elements (e.g., portions of the memory film 50) and a vertical semiconductor channel 60; and a coaxial double contact via structure 84 vertically extending through the dielectric material portion (such as the retro-stepped dielectric material portion 65) and comprising: an inner layer contact via structure 92 contacting the first-type electrically conductive layer 461; at least one insulating spacer layer (81, 82) comprising a respective tubular insulating portion that laterally surrounds the inner layer contact via structure 92; and an outer layer contact via structure 91 comprising a tubular conductive portion that laterally surrounds the at least one insulating spacer layer (81, 82) and contacting the second-type electrically conductive layer 462.
In one embodiment, a bottom surface of the inner layer contact via structure 92 contacts a horizontal surface segment of the first-type electrically conductive layer 461. In one embodiment, the horizontal surface segment of the first-type electrically conductive layer 461 is vertically recessed relative a top surface of the first-type electrically conductive layer 461. In one embodiment, a cylindrical surface segment of an outer sidewall of the outer layer contact via structure 91 contacts a cylindrical surface of the second-type electrically conductive layer 462.
In one embodiment, a first insulating layer 321 of the insulating layers 32 is located between the first-type electrically conductive layer 461 and the second-type electrically conductive layer 462; and a cylindrical surface segment of a sidewall of the inner layer contact via structure 92 contacts a cylindrical sidewall surface of the first insulating layer 321.
In one embodiment, the at least one insulating spacer layer (81, 82) comprises a stepped annular bottom surface contacting the first insulating layer 321. In one embodiment, the stepped annular bottom surface comprises: an inner annular horizontal surface segment 180; an outer annular horizontal surface segment 181; and a cylindrical vertical surface segment 182 that connects an inner periphery of the outer annular horizontal surface segment 181 to an outer periphery of the inner annular horizontal surface segment 180.
In one embodiment, the at least one insulating spacer layer (81, 82) comprises: an inner insulating spacer layer 82; and an outer insulating spacer layer 81 laterally surrounding the inner insulating spacer layer 82. In one embodiment, the inner insulating spacer layer 82 comprises a laterally protruding annular bottom portion 82A having a cylindrical sidewall surface 183 that contacts a lower cylindrical surface segment of an inner sidewall of the outer layer contact via structure 91. In one embodiment, a bottommost surface 184 of the outer insulating spacer layer 81 contacts an annular top surface of the laterally protruding annular bottom portion 82A of the inner insulating spacer layer 82.
In one embodiment, a first insulating layer 321 of the insulating layers 32 is located between the first-type electrically conductive layer 461 and the second-type electrically conductive layer 462; and the outer layer contact via structure 91 comprises an outer metallic barrier liner 911 and an outer metal layer 912, wherein the outer metallic barrier liner 911 contacts a cylindrical sidewall of the second-type electrically conductive layer 462 and an annular surface of the first insulating layer 321. In one embodiment, the outer metal layer 912 contacts a cylindrical surface of the at least one insulating spacer layer (81, 82).
In one embodiment, the inner layer contact via structure 92 comprises an inner metallic barrier liner 921 and an inner metal layer 922, wherein the inner metallic barrier liner 921 contacts a planar surface of the first-type electrically conductive layer and a cylindrical surface of the at least one insulating spacer layer (81, 82). In one embodiment, a contact-level dielectric layer 80 overlies the alternating stack (32, 46) and the dielectric material portion (such as the retro-stepped dielectric material portion 65).
In the first and third embodiments, a topmost surface of the inner layer contact via structure 92, a topmost surface of the at least one insulating spacer layer (81, 82), and a topmost surface of the outer layer contact via structure 91 are located within a horizontal plane including a top surface of the contact-level dielectric layer 80.
In the second embodiment, the at least one insulating spacer layer (81, 82) comprises a laterally-extending portion 280 that overlies the contact-level dielectric layer 80.
The coaxial double contact via structure 84 is more laterally compact compared to separate contact via structures which are located side by side. The coaxial double contact via structure 84 provides a reduced contact area, which can lead to a reduced memory device area, which increases the number of memory strings which may be formed over the same substrate.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Whenever two or more elements are listed as alternatives in a same paragraph of in different paragraphs, a Markush group including a listing of the two or more elements is also impliedly disclosed. Whenever the auxiliary verb “can” is employed in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device can provide an equivalent result. As such, the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. If publications, patent applications, and/or patents are cited herein, each of such documents is incorporated herein by reference in their entirety.
The present application is a continuation-in-part application of U.S. patent application Ser. No. 17/351,789 that was filed on Jun. 18, 2021, the contents of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17351789 | Jun 2021 | US |
| Child | 18662077 | US |
