Patent Application
20130001699
The present invention relates to a MOSFET technology and, in particular, to a MOSFET with an integrated Schottky diode.
In a typical Pulse-Width-Modulation (PWM) circuit for power converters, a high side Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) and a lower side MOSFET are used for rectifying purpose in order to generate an output voltage when used in a DC-DC convertor. In operating, the lower side (LS) MOSFET usually requires longer time to switch from off state to on state; and, during such time period, a body diode may turn on by a higher voltage at the drain than at the source electrode, which will cause power losses in the high side MOSFET by the current flowing from the drain electrode through the body diode to the high side MOSFET. Therefore, it is very important to prevent the body diode from turning on by using a Schottky diode in parallel with the body diode to eliminate the reverse recover loss of the body diode.
Schottky diode has little or no minority carrier injection in forward conduction, so that it can prevent the body diode to turn on so as to cut down the reverse recover loss of the body diode; it also reduces the forward conduction losses due to its lower forward voltage drop. Therefore, the Schottky diode can reduce power losses and improve power efficiency when it is connected in parallel with the body diode across the drain and the source electrodes of a MOSFET.
As power converter applications continue to ramp up towards higher voltage and faster switching speed; thus how to integrate a Schottky diode into a MOSFET device becomes an important task. An US patent, 2010/0258897, discloses a trench junction barrier Schottky diode which is built within a MOSFET device for achieving this goal. However, the trench junction barrier Schottky diode, disclosed in the US 2010/0258897, is built in the cell region of the MOSFET itself, which has limited shrinking capability for the future device in order to lower down the forward voltage drop efficiently, which is an important issue for some power applications.
Therefore, a need still exists to design a Schottky diode especially integrated with a MOSFET device to improve overall switching speed and to reduce the forward voltage drop even further for higher speed, higher power converter applications.
An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between a Schottky barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.
In one embodiment of this invention, a trench junction barrier Schottky structure with enhanced contact area between the Schottky Barrier metal and the semiconductor substrate is described, wherein at least one trench is built between two MOSFETs with top mesas adjacent to the trench, and a barrier metal is overlaid on the inner surface of the trench extending over the top mesas so that overall contact area at the Schottky junction can be increased.
Furthermore, in order to prevent the leakage current flowing between the two Schottky diodes on the two sidewalls of the trench through the region underneath the bottom of the trench, a second conductivity type is implanted with a predefined concentration into the region underneath the bottom of the trench.
The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the area between two cells of MOSFET with minimum overhead by shrinking the dimension of pitch between two trenches.
In another embodiment of this invention, a method to manufacture the trench junction barrier Schottky structure is described, wherein an insulating layer is formed over the substrate extending over the top mesas between the trenches. In addition, a mask can be used to remove the insulating layer over the top mesas or the insulating layer can be maintained on the top of the mesas without using the mask.
In yet another embodiment of this invention, a MOSFET integrated with a trench junction barrier Schottky structure is described, in which the Schottky structure is built across the source and drain electrodes of the MOSFET.
The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein:
The invention will now be described in greater detail with preferred embodiment and illustrations attached. Nevertheless, it should be recognized that the preferred embodiments of the invention are only for illustrating. Besides the preferred embodiments mentioned here, this present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying claims.
In order to form a Schottky diode, a Schottky barrier metal 107 is overlaid over the inner surface of the trench extending over the first top mesa 104a and the second top mesa 104b, by which a plurality of Schottky junctions are formed at the first top mesa 104a, the second top mesa 104b, the first sidewall 106a, the second sidewall 106b and the bottom mesa 108.
The area of the Schottky barrier metal overlapping with the semiconductor substrate 100 defines the contact area of the Schottky structure at the junction, and the contact area will affect the barrier height of the Schottky junction, which in turn will affect the Schottky forward voltage drop.
The area of junction at the first top mesa 104a and the second top mesa 104b increases the contact area of the Schottky diode.
The total area of the junctions may express in following equation (1):
Area=(t1+2*d+t2+w)*L (1)
wherein t1 is the width of the second top mesa 104b and t2 is the width of the first top mesa 104a, w is the width of the trench 102, d is the depth of the trench 102 and L is length of the contact area for the first top mesa 104a, the second top 104b, the first sidewall 106a and the second 106b as shown in
The overlaid Schottky barrier metal over the inner surface of each sidewall forms a Schottky junction respectively, in order to ensure the two Schottky junctions formed on the two sidewalls are not contacted by the barrier metal itself inside the trench, the thickness of barrier metal 107 is less than the half width w of the trench 102 so that it can save rooms for the contact metal, which will be overlaid over the Schottky barrier metal latter on for creating a metal contact for electrical connection.
The Schottky barrier metal 107 includes, but is not limit to, Ti/TiN, Co/TiN, Pt/TiN, Mo/TiN, Ni/TiN and a combination thereof to form the Schottky junction for different Schottky barrier height.
In another embodiment, referring to
The pinch-off voltage across the PN junction to pinch off the conducting channel underneath the Schottky barrier metal to block all the electronics flowing through this region, which will effectively block all the leakage current flowing between the two sidewalls of the trench through the region underneath the bottom of the trench.
Please refer to
Step S1: providing a semiconductor substrate of a first conductivity type;
Step S2: opening at least one trench in the semiconductor substrate wherein the trench comprises at least one top mesa adjacent to the trench;
Step S3: configuring a region underneath the bottom of the trench with a second conductivity type opposite to the first conductivity type;
Step S4: overlaying a Schottky barrier metal over the inner surface of the trench extending over the top mesa.
The step S1 provides a semiconductor substrate of n-type dopant.
The step S2 opens a trench in the semiconductor substrate by lithography process, and the portion adjacent to the opening of the trench on the substrate will be called top mesa.
The step S3 implants the region underneath the bottom of the trench with a p-type dopant; the detail of concentration of the p-type dopant has been described in the structure embodiment.
The step S4 overlays a Schottky barrier metal on the surface of the trench and the top mesa; and the detail has been described in the structure embodiment.
Please refer to
The trench 202 include a first sidewall 212a, a second sidewall 212b which is opposite to the first sidewall 212a and a bottom mesa 207. The top mesa 214 is adjacent to the trench 202. The Schottky barrier metal 208 overlays the first sidewall 212a and the second sidewall 212b, the bottom mesa 207 and the top mesa 214, and then a contact metal 204 overlays the barrier metal 208 for making electrical connections to outside. A guarded region 210 is implanted with a p-type dopant underneath the bottom mesa 207 to block the leakage current between the first sidewall 212a and the second sidewall 212b underneath the bottom mesa 207.
Please continuously refer to
Area=(p−w)*L*n (4)
wherein p is the pitch between two adjacent trenches, w is the width of the trench 202, n is the number of the top mesas, and L is length of the contact area as illustrated in
A contact metal 204 is deposited on barrier metal 208, which can be used for contact point for making electrical connection to the external signals. The contact metal 204 includes, but it is not limited to, AlCu, Tungsten/Al—Si, or a combination thereof.
Please refer to
Step 11: providing a semiconductor substrate of a first conductivity type with a MOSFET device;
Step 12: forming an insulating layer on the semiconductor substrate;
Step 13: opening at least one trench in open space;
Step 14: configuring a region underneath the bottom of the trench with a second conductivity type opposite to the first conductivity type;
Step 15: removing the insulating layer in the open space;
Step 16: forming a barrier metal overlaying the inner surface of the trench and the top mesa;
Step 17: forming a contact metal overlaying the barrier metal.
The step S11 provides a semiconductor substrate of n-type dopant with a trench gate MOSFET device, wherein the trench gate MOSFET device has source electrode, gate electrode and body well in a cell region in the semiconductor substrate. The region between the cell regions is called open space.
The step S12 deposits an insulating layer on the semiconductor substrate, and the insulating layer includes, but is not limited, low temperature oxide (LTO) or Borphosphorsilikat glass (BPSG).
The step S13 opens a trench in the open space by a lithography process in one embodiment.
The step S14 implants a region underneath the bottom of the trench with a p-type dopant by an implementing process, and the p-type dopant includes, but is not limited to, Boron or BF2.
The step S15 removes the insulating layer in the open space by a lithograph process with a mask.
The step S16 forms a barrier metal overlaying the inner surface of the trench and the top mesa.
The step S17 forms a contact metal on the device, it fills the opening of the trench and overlays the barrier metal on the inner surface of the trench. The contact metal can be, but it is not limited to, AlCu, W/AlCu or a combination thereof.
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In one embodiment, the barrier metal 310 and contact metal 316 can be deposited at the same step.
The contact hole 311 electrically connects the source electrode 308 and barrier metal 310. The thickness of the barrier metal 310 is less than the half width of each trench.
Consequently, the source electrode 308 of the MOSFETs and the Schottky diode device 318 are electrically connected by the contact hole 311; and the drain electrode is connected through the substrate 300.
Please refer to
The step S25 forms a barrier metal without removing the insulating layer in the open space, and the barrier metal is overlaid on the inner surface of the trench and the insulating layer, and then the barrier metal on the insulating layer is removed by CMP or etching process.
Referring to
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In one embodiment, the barrier metal 412 and contact metal 414 can be deposited at the same step.
Consequently, the source electrode 408 of the MOSFETs and the Schottky diode device 418 are electrically connected; and the drain electrode is connected through the substrate 400.
As described above, in the preferred embodiment, the conductivity type of the semiconductor substrate 100, 200, 300 and 400 is n-type, and the conductivity type of the guarded region 110, 210, 307 and 407 is p-type. Alternatively, the conductivity type of the semiconductor substrate 100, 200, 300 and 400 is p-type, and the conductivity type of the guarded region 110, 210, 307 and 407 is n-type.
Although preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described preferred embodiments. Rather, various changes and modifications can be made within the spirit and scope of the present invention, as defined by the following Claims.
