BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic depiction of a cross-sectional view of a portion of a semiconductor wafer during one phase of manufacture in accordance with embodiments of the method of the present invention.
FIG. 2 shows the structure of FIG. 1 following the deposition of a spacer layer within the trench formed during the manufacturing step shown in FIG. 1.
FIG. 3 depicts the structure of FIG. 2 after an etching process to form sidewalls spacers in the trench in accordance with embodiments of the present invention.
FIG. 4 shows the structure of FIG. 3 following the formation of a replacement gate within the trench, in accordance with embodiments of the present invention.
FIG. 5 depicts the structure of FIG. 4 after the removal of the sacrificial layer in accordance with embodiments of the present invention.
FIG. 6 shows the structure FIG. 5 following the removal of the sidewall spacers in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention addresses and solves problems related to the formation of semiconductor devices having raised source/drains, and in particular, the formation process of raised source/drains and the incorporation of this process with replacement gate technology. This is achieved, at least in part, by the present invention in the provision of a blanket deposition of a raised source/drain layer on the substrate, followed by deposition of a sacrificial layer on the raised source/drain layer. The trench is formed in the sacrificial layer and the raised source/drain, and a gate is formed within the trench. The sacrificial layer is then removed, leaving the raised source/drain area and the replacement gate. A blanket deposition of the raised source/drain layer thereby avoids the disadvantages attendant to formation of raised source/drains by selective silicon epitaxy and allows a larger number of materials to be employed as the raised source/drain material.
FIG. 1 is a schematic depiction of a portion of a semiconductor wafer during one phase of manufacture in accordance with embodiments of the present invention. A substrate 10, such as a silicon substrate, is provided. The raised source/drain layer 12 is blanket deposited on the top surface of the substrate 10. The raised source/drain layer 12 may be made of silicon or polysilicon, for example. However, other materials suitable for blanket deposition and for use as a raised source/drain layer may be employed without departing from the scope of the present invention. The thickness of the raised source/drain layer 12 is advantageously made to a final thickness for the raised source/drains that are desired. As an example, the thickness of the raised source/drain layer 12 is between 300-700 ![]()
and in certain preferred embodiments, is approximately 500 ![]()
The sacrificial layer 14 is then deposited on top of the raised source/drain layer 12. The sacrificial layer 14 should comprise material that is preferentially etched to leave the raised source/drain layer 12 intact. An example of a suitable material is silicon dioxide (SiO2). The deposition of the raised source/drain layer 12 and the sacrificial layer 14 may be by any conventional methodology, such as chemical vapor deposition of (CVD). The thickness of the sacrificial layer 14 should be such that the combination of the thickness of the source/drain layer 12 and the sacrificial layer 14 is equal to the desired thickness of the finished gate.
Following the deposition of the raised source/drain layer 12 and the sacrificial layer 14 on the substrate 10, patterning and etching is performed to create a trench 16 in the sacrificial layer 14 and the raised source/drain layer 12, stopping at the substrate 10. A dry etch may be performed, such as a plasma etch. It is advantageous to perform the plasma etch with an etch chemistry that will etch the sacrificial layer 14 and the raised source/drain layer 12 preferentially without significantly etching the substrate 10. An example of such an etch chemistry is silicon tetrachloride/chlorine, for example. However, this is exemplary only, as other etch chemistries may be employed depending upon the materials used in the sacrificial layer 14 on the raised source/drain layer 12.
The width of the trench 16 is such as to accommodate the desired final width of the replacement gate and the desired spacing between the sides of the replacement gate and the raised source/drains. For example, the width of the trench 16 may be between about 80 and about 100 ![]()
for example, although other widths may be provided without departing from the present invention.
FIG. 2 shows the structure of FIG. 1 following the deposition of a spacer layer 18 within the trench 16 and on top of the sacrificial layer 14. The spacer layer 18 may be made of any suitable material, but should be one that is preferentially etchable with respect to the eventual replacement gate material, the raised source/drain material, and the substrate material. In exemplary embodiments, the material formed in the space layer 18 is silicon nitride. An exemplary thickness for the spacer layer 18 is between about 20 and about 40 ![]()
for example.
After the spacer 18 has been deposited, an etching is performed to create sidewall spacers 20 from the spacer layer 18. This is achieved, for example, by an anisotropic etching such as a reactive ion etch. This removes the horizontal surfaces of the silicon layer 18, leaving the vertical sidewall spacers 20. The substrate 10 is exposed within the trench 16.
FIG. 4 shows the structure of FIG. 3 following the deposition of a gate dielectric layer 22 and the formation of the replacement gate 24. This involves the deposition of the replacement gate material, which may be polysilicon, or other suitable conductive or semi conductive material. This is followed a polishing to remove the excess gate material from the top of the sacrificial layer 16. Gate dielectric layer 22 may be a high k gate dielectric material or a more conventional gate dielectric material.
Following the formation of the replacement gate 24, the sacrificial layer 16 is removed, as depicted in FIG. 5. When the sacrificial layer 16 is made of silicon dioxide, for example, the removal process may be preformed by a buffered oxide etch, for example. This leaves the structure of FIG. 5 in which the raised source/drain is provided on either side of sidewall spacers 20 and the replacement gate 24. Heavy doping can then be performed to dope both the raised source/drain regions 12, and the replacement gate 24. The spacers 20 and the replacement gate 24 prevent doping of the substrate 10 underneath these elements.
FIG. 6 depicts the structure of FIG. 5 following the removal of the sidewall spacers 20. When the sidewall spacers 20 are made of silicon nitride, for example, a hot phosphoric etch may be used to remove the sidewall spacers 20. Once the sidewall spacers 20 are removed, a light doping may be performed to create source/drain extension areas 26 in the substrate 10. A conventional implantation process may be used to create the source/drain extensions 26.
As can be seen in FIG. 6, the raised source/drain regions 12 are a defined distance from the replacement gate 24, and may be 30 ![]()
for example. The removal of the sidewall spacers 20 from the final structure allows for their replacement by a lower k dielectric material, among other advantages.
The present invention thus provides an improved process for creating semiconductor devices with raised source/drain regions and a replacement gate that is a defined distance from the raised source/drain regions. This process allows a wider range of materials to be employed as the raised source/drain regions, and overcomes certain disadvantages of epitaxial growth processes.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.
Patent Application
20080070356
