USE OF ALLOYS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION

Abstract

The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and siliciding the NMOS gate electrode to form a silicided gate electrode. This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding.

Description

TECHNICAL FIELD OF THE INVENTION

The invention is directed, in general, to the silicidation of gates and, more specifically, to the use of alloys to provide low defect gate full silicidation.

BACKGROUND OF THE INVENTION

Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today's ever shrinking and changing transistor devices. One of the principal reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is in order to solve problems of poly-depletion. Traditionally, a polysilicon gate electrode with an overlying silicide was used for the gate electrodes in metal oxide semiconductor (MOS) devices. However, as device feature size continues to shrink, poly depletion becomes a serious issue when using polysilicon gate electrodes.

Accordingly, metal gates have been proposed. However, in order to optimize the performance of CMOS devices, the metal gates need dual tunable work functions. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1˜4.4 eV for NMOS and 4.8˜5.1 eV for PMOS (see, B. Cheng, B. Maiti, S. Samayedam, J. Grant, B. Taylor, P. Tobin, J. Mogab, IEEE Intl. SOI Conf. Proc., pp. 91-92, 2001).

Recently, silicided metal gates have been investigated based on the extension of existing self-aligned silicide (SALICIDE) technology. In this approach, polysilicon is deposited over the gate dielectric. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully silicided metal gate, rather than a deposited metal gate. The silicided metal gate provides a metal gate with the least perturbation to the conventional process, and avoids contamination issues.

Nevertheless, one problem associated with this technology is the ability (or inability) to completely react all of the polysilicon in the gate electrode with the metal. For example, if the anneal used to form the silicide is too mild the gate electrodes will not fully react; however, if the anneal used to form the silicide is too aggressive the metal can penetrate into the channel, which is catastrophic to the device.

Accordingly, what is needed is a method for manufacturing silicided metal gate structures that does not experience these and other drawbacks of the prior art methods.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, the disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a p-type metal oxide semiconductor (PMOS) device region and n-type metal oxide semiconductor (NMOS) device region. The method further includes forming a PMOS gate structure including a PMOS gate dielectric and PMOS gate electrode over the substrate in the PMOS device region, and an NMOS gate structure including an NMOS gate dielectric and NMOS gate electrode over the substrate in the NMOS device region. The method, in this embodiment, also includes forming p-type source/drain regions within the substrate in the PMOS device region and proximate the PMOS gate structure, and n-type source/drain regions within the substrate in the NMOS device region proximate the NMOS gate structure. Additionally, the method includes forming a metal alloy layer over the PMOS gate electrode and the NMOS gate electrode. Moreover, the method includes incorporating the metal alloy into the PMOS gate electrode and NMOS gate electrode to form a PMOS gate electrode fully silicided with the metal alloy and an NMOS gate electrode fully silicided with the metal alloy.

The method for manufacturing the semiconductor device, in another embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy.

In an alternative embodiment, the method for manufacturing the semiconductor device includes forming a PMOS gate structure over a substrate, wherein the PMOS gate structure includes a PMOS gate dielectric and a PMOS gate electrode. This alternative method further includes forming p-type source/drain regions within the substrate proximate the PMOS gate structure, and forming a metal alloy layer over the PMOS gate electrode. The metal alloy layer, in this embodiment, includes a first metal and a second different metal, wherein the second different metal is from group 4, group 6, group 7, group 8, or group 9 of the periodic table. The method additionally includes incorporating the metal alloy into the PMOS gate electrode to form a PMOS gate electrode fully silicided with the metal alloy.

In yet another embodiment, the method for manufacturing the semiconductor device includes selecting a metal alloy material based upon a silicidation transient phase of a gate electrode material, forming a layer of the metal alloy material over a layer of the gate electrode material, and incorporating the metal alloy into the layer of gate electrode material to form a layer of gate electrode material fully silicided with the metal alloy.

Also provided is a semiconductor device. The semiconductor device, in this embodiment, includes an NMOS gate structure located over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode fully silicided with a metal alloy. The semiconductor device, in this embodiment, may further include n-type source/drain regions located within the substrate proximate the NMOS gate structure.

In another embodiment, the semiconductor device includes a PMOS gate structure located over a substrate, wherein the PMOS gate structure includes a PMOS gate dielectric and a gate electrode fully silicided with a metal alloy. The metal alloy, in this embodiment, includes a first metal and a second different metal, wherein the second different metal is from group 4, group 6, group 7, group 8, or group 9 of the periodic table. This semiconductor device further includes p-type source/drain regions located within the substrate proximate the PMOS gate structure.

In yet another embodiment, the semiconductor device includes a p-type metal oxide semiconductor (PMOS) device region and n-type metal oxide semiconductor (NMOS) device region located over a substrate. The PMOS device region, in this embodiment, includes 1) a first gate structure located over the substrate, the first gate structure including a first gate dielectric and a first gate electrode fully silicided with a first metal alloy, and 2) p-type source/drain regions located within the substrate on opposing sides of the first gate structure. The NMOS device region, in this embodiment, includes 1) a second gate structure located over the substrate, the second gate structure including a second gate dielectric and a second gate electrode fully silicided with a second metal alloy, and 2) n-type source/drain regions located within the substrate on opposing sides of the second gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a semiconductor device constructed according to one embodiment of the disclosure;

FIGS. 2-12 illustrate detailed steps of one example embodiment for manufacturing a semiconductor device in accordance with this disclosure; and

FIG. 13 illustrates an integrated circuit (IC) having been manufactured using one embodiment of the disclosure.

DETAILED DESCRIPTION

The present disclosure is based, at least in part, on the acknowledgement that certain transient phases that may exist during a typical silicidation process are particularly problematic. The phrase “transient phases”, as used throughout this disclosure, means material phases of the metal silicide that may exist during the process of siliciding a polysilicon material but that do not exist after the process is complete. More specifically, the present disclosure acknowledges that certain ones of these transient phases result in transient stress in the material being silicided. The phrase “transient stress”, as used throughout this disclosure, means stress that exists during the process of siliciding a polysilicon material but that does not exist after the process is complete. Moreover, the present disclosure acknowledges that the transient stresses may, in certain instances, be the cause of metal punchthrough into the channel region of semiconductor devices, and thus ultimate device failure.

Based upon these acknowledgements, as well as substantial experimentation, the present disclosure recognizes that the selection and use of certain metal alloys to silicidize the gate electrode material, reduces or eliminates the formation of the transient phases that tend to cause unwanted transient stress. For example, the present disclosure recognizes that the use of the metal alloy nickel platinum, among others, to silicidize the gate electrode material may reduce or eliminate the formation of the transient phase Ni₃₁Si₁₂ (e.g., also referred to as Ni₅Si₂). Other metal alloys, however, might be used to reduce or prevent the formation of the Ni₃₁Si₁₂, as well as other undesirable transient phases.

FIG. 1 illustrates a semiconductor device 100 constructed according to one embodiment of the disclosure. The semiconductor device 100, depending on the embodiment, may be configured as either a PMOS device or an NMOS device. Both configurations will be discussed with reference to FIG. 1.

The semiconductor device 100 includes a substrate 110. Located within the substrate 110 in the embodiment of FIG. 1 is a well region 120. Depending on whether the device 100 is a PMOS device or NMOS device, the well region 120 might be doped with an n-type dopant or p-type dopant, respectively. Moreover, the well region 120 may or may not exist, for example based upon the specific design of the device 100. From this point forward, those features that would be used within an NMOS device may be referred to as an NMOS feature and those features that would be used within a PMOS device may be referred to as a PMOS feature.

Located over the substrate 110 and well region 120 is a gate structure 130. The gate structure 130 includes a gate dielectric 140 and a gate electrode 150. The gate dielectric 140 may comprise many different materials and remain within the purview of the disclosure. For example, in those embodiments wherein the device 100 is a NMOS device, the gate dielectric 140 may comprise silicon dioxide, silicon oxynitride, a high-k dielectric (e.g., a dielectric material having a dielectric constant greater than silicon dioxide), etc. In those embodiments wherein the device 100 is a PMOS device, the gate dielectric 140 may comprise a similar material, among others.

The gate electrode 150, as shown, is fully silicided. The term “fully silicided”, as used throughout this disclosure, means that all of the silicon within the gate electrode 150 has reacted to form a metal silicide. The gate electrode 150, when constructed in accordance with the disclosure, may comprise a number of different materials. In the given embodiment of FIG. 1, the gate electrode 150 includes a metal alloy selected specifically to reduce transient stress that may form during the silicidation process. This metal alloy may be selected to prevent the formation of Ni₃₁Si₁₂ as a transient phase during silicidation. The metal alloy, however, is not selected based upon only its ability to tune the work function of the gate electrode 150.

In one embodiment the metal alloy includes a first metal and a second different metal collectively selected to reduce transient stress that may form during the silicidation process. The first metal may vary. Nevertheless, in one embodiment it comprises nickel and in another embodiment it comprises platinum. The second different metal may also vary. In those embodiments wherein the device 100 is a PMOS device, the second different metal might be from group 4, group 6, group 7, group 8, or group 9 of the periodic table. For example, the second metal might comprise zirconium, tungsten, molybdenum, rhenium, technetium, iron, ruthenium, iridium, rhodium or alloys thereof, as well as hafnium and its alloys. Alternatively, in those embodiments wherein the device 100 is an NMOS device, the second different metal might be from group 4, group 6, group 7, group 8, group 9 or group 10 of the periodic table. For example, the second different metal in this embodiment might comprise zirconium, tungsten, molybdenum, rhenium, technetium, iron, ruthenium, iridium, rhodium, palladium or alloys thereof, as well as hafnium, platinum and their alloys.

The gate structure 130 further contains gate sidewall spacers 160 on the sides of the gate electrode 150 and gate dielectric 140. The gate sidewall spacers 160 in the embodiment of FIG. 1 each include a number of different layers. For instance the gate sidewall spacers 160, among other layers, each include L-shaped nitride spacers 163 and sidewall oxides 168. The other layers, among other materials, could include a collection of oxides and nitrides. Nevertheless, the gate sidewall spacers 160 may comprise many different types and numbers of layers while staying consistent with the principles taught herein.

The semiconductor device 100 illustrated in FIG. 1 additionally includes source/drain regions 170 located within the substrate 110 and proximate the gate structure 130. The source/drain regions 170 may include both extension implants and source/drain implants. The source/drain regions 170, depending on whether the device 100 is a PMOS device or NMOS device, may comprise a p-type dopant or n-type dopant, respectively.

Located within the source/drain regions 170 are silicided source/drain regions 180. In one embodiment, the silicided source/drain regions 180 act as source/drain contact regions as well as blocking layers (e.g., to protect the source/drain regions 170 from the silicidation material used to silicide the gate electrode 150).

FIGS. 2-12 illustrate detailed steps of one example embodiment for manufacturing a semiconductor device in accordance with this disclosure. FIG. 2 illustrates a semiconductor device 200 at an initial stage of manufacture. The device 200 includes a substrate 210. The substrate 210 may, in one embodiment, be any layer located in the device 200, including a wafer itself or a layer located above the wafer (e.g., epitaxial layer). In the embodiment illustrated in FIG. 2, the substrate 210 is a p-type substrate; however, one skilled in the art understands that the substrate 210 could be an n-type substrate without departing from the disclosure. In such an embodiment, certain ones of the dopant types described throughout the remainder of this document might be reversed. For clarity, no further reference to this opposite scheme will be discussed.

Located within the substrate 210 in the embodiment shown in FIG. 2 is a well region 220. The dopant type for the well region 220 would typically depend on whether the device 200 is a PMOS device or NMOS device. In those embodiments wherein the device 200 is a PMOS device, the well region 220 would include an n-type dopant. In those embodiments wherein the device 200 is an NMOS device, the well region 220 would include a p-type dopant. Those skilled in the art understand that in certain circumstances where the p-type substrate 210 dopant concentration is high enough, and the device 200 comprises an NMOS device, the well region 220 may be excluded. In those embodiments wherein the well region 220 exists, it would likely be ion implanted using a dopant dose ranging from about 1E13 atoms/cm² to about 1E14 atoms/cm² and at an energy ranging from about 100 keV to about 500 keV. This results in the well region 220 having a peak dopant concentration ranging from about 5E17 atoms/cm³ to about 1E9 atoms/cm³.

Located over the substrate 210 in the embodiment of FIG. 2 is a gate structure 230. The gate structure 230 includes a gate dielectric 240 and a gate electrode 250. The gate dielectric 240 may comprise a number of different materials and stay within the scope of the present invention. For example, the gate dielectric 240 may comprise silicon dioxide in one embodiment. In another embodiment, the gate dielectric 240 can be any one of a number of high-K dielectric materials and be within the scope of this disclosure. Such materials include a variety of hafnium and zirconium silicates and their various oxides. For example, in one embodiment the high-k dielectric material might comprise HfSiO; however in other embodiments the high-k dielectric material might comprise HfO₂, HfSiON, HfAlO or HfLaO.

The gate dielectric 240 may additionally be formed to varying thicknesses. For example, in the embodiment wherein the gate dielectric 240 comprises silicon dioxide, it might have a thickness ranging from about 0.5 nm to about 5 nm, and more specifically a thickness ranging from about 1 nm to about 3 nm. In the embodiment wherein the gate dielectric 240 comprises a high-k material, for example a hafnium based material, it might have a thickness ranging from about 1.5 nm to about 5 nm. Other thicknesses could nonetheless also be used.

Any one of a plurality of manufacturing techniques could be used to form the gate dielectric 240. For example, the gate dielectric 240 may be either grown or deposited. Additionally, the growth or deposition steps may require a significant number of different temperatures, pressures, gasses, flow rates, etc. Those skilled in the art understand the skill that may be required to tailor such process conditions.

The gate electrode 250 should comprise a material capable of being silicided. Accordingly, in one embodiment the gate electrode 250 comprises standard polysilicon. In an alternative embodiment, however, the gate electrode 250, or at least a portion thereof, comprises amorphous polysilicon. The amorphous polysilicon embodiment may be particularly useful when a substantially planar upper surface of the gate electrode 250 is desired. Nevertheless, this amorphous polysilicon embodiment will be discussed no further.

The deposition conditions for the gate electrode 250 may vary. However, if the gate electrode 250 were to comprise standard polysilicon, such as the instance in FIG. 2, the gate electrode 250 could be deposited using a pressure ranging from about 100 torr to about 300 torr and a temperature ranging from about 620° C. to about 700° C. Additionally, a SiH₄ or Si₂H₆ gas flow ranging from about 50 sccm to about 150 sccm might be used. Other deposition conditions different from those disclosed could nonetheless also be used. The gate electrode 250 desirably has a thickness ranging from about 50 nm to about 150 nm, among others.

The device 200 of FIG. 2 further includes a protective layer 270 located over the gate electrode 250. In one embodiment, the protective layer 270 is located directly on the gate electrode 250; however, other embodiments exist wherein one or more layers interpose the two. The protective layer 270, which may comprise silicon nitride among other materials, may have a thickness ranging from about 5 nm to about 50 nm. Nevertheless, the protective layer 270 should have a thickness sufficient to adequately protect the gate electrode 250. The protective layer 270, in one embodiment, functions as a hardmask layer. In this embodiment, the protective layer 270 and a lithography process (e.g., including patterned photoresist) could be used to pattern the gate dielectric 240 and gate electrode 250.

FIG. 3 illustrates the device 200 of FIG. 2 after forming portions of gate sidewall spacers 310. The portions of the gate sidewall spacers 310 shown in FIG. 3 include an oxide layer 320 and an offset nitride spacer 330. Nevertheless, other layers may be used for the gate sidewall spacers 310. In the embodiment of FIG. 3, the oxide layer 320 and offset nitride spacer 330 were formed using standard processes. However, other non-standard processes could be used.

FIG. 4 illustrates the device 200 of FIG. 3 after the formation of extension implants 410 within the substrate 210. The extension implants 410 may be conventionally formed and generally have a peak dopant concentration ranging from about 1E19 atoms/cm³ to about 2E20 atoms/cm³. As is standard in the industry, the extension implants 410 have a dopant type opposite to that of the well region 220 they are located within. Thus, in the embodiment wherein the device 200 is a PMOS device the extension implants 410 might comprise a p-type dopant, and in the embodiment wherein the device 200 is an NMOS device the extension implants 410 might comprise an n-type dopant.

FIG. 5 illustrates the device 200 of FIG. 4 after forming remaining portions of the gate sidewall spacers 310. Particularly, a cap oxide 510, L-shaped nitride spacers 520 and sidewall oxides 530 complete the gate sidewall spacers 310. FIG. 5 indicates that an L-shaped scheme is used to complete the gate sidewall spacers. However, other embodiments exist wherein a single bulk spacer, for example comprising an oxide, completes the gate sidewall spacers. The remaining portions of the gate sidewall spacers 310 may be manufactured using, among others, conventional processes.

FIG. 6 illustrates the device 200 of FIG. 5 after the formation of source/drain implants 610 within the substrate 210. The formation of the source/drain implants 610 may, in one embodiment, be conventional. Generally the source/drain implants 610 have a peak dopant concentration ranging from about 1E18 atoms/cm³ to about 1E21 atoms/cm³. The source/drain implants 610 typically have a dopant type opposite to that of the well region 220 they are located within. Thus, in the embodiment wherein the device 200 is a PMOS device the source/drain implants 610 might comprise a p-type dopant, and in the embodiment wherein the device 200 is an NMOS device the source/drain implants 610 might comprise an n-type dopant.

FIG. 7 illustrates the device 200 of FIG. 6 after subjecting it to a source/drain anneal, thereby activating source/drain regions 710. It is believed that a source/drain anneal conducted at a temperature ranging from about 1000° C. to about 1350° C. and a time period ranging from about 1 millisecond to about 5 seconds would be sufficient. It should be noted that other temperatures, times, and processes could be used to activate the source/drain regions 710.

Additionally illustrated in FIG. 7 is the formation of a metal 720 over the exposed portions of the source/drain regions 710 as well as over the gate structure 230. As shown, the metal 720 may cover the entire surface of the device 200. The metal 720 in the embodiment shown in FIG. 7 happens to be a thin cobalt layer; however, other materials that react with silicon to form a silicide could easily be used. For instance, it is known that the metal 720 may also comprise nickel, platinum, titanium, tantalum, molybdenum, tungsten, another similar metal, or any combination thereof while staying within the scope of the present disclosure.

The metal 720 may be formed using a number of different processes, and may be formed to a number of different thicknesses. In one embodiment, the metal 720 is deposited to a thickness ranging from about 3 nm to about 15 nm. Such thicknesses, however, might be used when the metal 720 comprises cobalt. Various other thicknesses could be used if the metal 720 were to comprise one of the different metals disclosed above.

FIG. 8 illustrates the device 200 of FIG. 7 after subjecting it to a first rapid thermal anneal (RTA) and subsequent selective metal strip. This RTA attempts to cause the metal 720 to react with the silicon of the source/drain regions 710 to form silicided source/drain regions 810. In the instance where the metal 720 comprises cobalt, the first RTA causes the cobalt to react with the silicon to form a cobalt silicide.

The first RTA may be conducted using a variety of different temperatures and times. Nonetheless, it is believed that the first RTA, in one embodiment, should be conducted in a rapid thermal processing tool at a temperature ranging from about 350° C. to about 550° C. and a time period ranging from about 10 second to about 100 seconds to accomplish the silicidation, particularly when cobalt is used. The specific temperature and time period are typically based, however, on the ability to form the silicided source/drain regions 810 to a desired depth, as well as the silicide materials selected. A selective wet etch, using for example a mixture of sulfuric acid (H₂SO₄), hydrogen peroxide (H₂O₂) and water (H₂O), may then be used to remove un-reacted metal 720.

Additionally, another optional second RTA step may be used to form a low resistivity phase of the silicide. In the case of using a cobalt metal, the first RTA forms CoSi, while the optional second RTA forms CoSi₂, which has lower resistivity and is more stable. This optional second RTA step is typically performed using a temperature ranging from about 650° C. to about 800° C. for a time period ranging from about 5 to about 60 seconds.

FIG. 9 illustrates the device 200 of FIG. 8 after removing the protective layer 270 from over the gate electrode 250 to form an opening 910. In one embodiment, the etchant used to remove the protective layer 270 is highly selective to the gate electrode 250. Accordingly, this etchant does not substantially affect the gate electrode 250. Those skilled in the art appreciate that the specific etch chosen for the protective layer 270 is highly dependent on the materials for each and the etch selectivities for each.

FIG. 10 illustrates the device 200 of FIG. 9 after depositing a second metal 1010 over the exposed portions of the gate electrode 250, as well as over the remainder of the semiconductor device 200. In this disclosed embodiment, the metal 1010 is designed to silicidize the gate electrode 250. Moreover, the second metal 1010 comprises a metal alloy. For example, the second metal 1010 includes a metal alloy selected specifically to reduce transient stress that may form during the following silicidation process. This metal alloy may be selected to prevent the formation of Ni₃₁Si₁₂ as a transient phase during silicidation. The metal alloy, however, is not selected based upon only its ability to tune the work function of the gate electrode 250.

In one embodiment the metal 1010 includes a first metal and a second different metal collectively selected to reduce transient stress that may form during the silicidation process. As indicated above, the first metal may vary. Nevertheless, in one embodiment it comprises nickel and in another embodiment it comprises platinum. The second different metal may also vary. In those embodiments wherein the device 200 is a PMOS device, the second different metal might be from group 4, group 6, group 7, group 8, or group 9 of the periodic table. For example, the second metal might comprise zirconium, tungsten, molybdenum, rhenium, technetium, iron, ruthenium, iridium, rhodium or alloys thereof, as well as hafnium and its alloys. Alternatively, in those embodiments wherein the device 200 is an NMOS device, the second different metal might be from group 4, group 6, group 7, group 8, group 9 or group 10 of the periodic table. For example, the second different metal in this embodiment might comprise zirconium, tungsten, molybdenum, rhenium, technetium, iron, ruthenium, iridium, rhodium, palladium or alloys thereof, as well as hafnium, platinum and their alloys. All that being said, in the embodiment of FIG. 10 the metal 1010 comprises nickel platinum.

The thickness of the metal 1010 will vary. For example, the thickness of the metal 1010 will depend on what alloys are used therefore, as well as the rate upon which those alloys consume the polysilicon of the gate electrode 250. In the embodiment wherein the second metal 1010 comprises nickel platinum, the second metal 1010 would be deposited to a thickness sufficient to silicide the gate electrode 250. Therefore, in this embodiment the thickness of the metal 1010 should range from approximately 30 nm to about 90 nm.

FIG. 11 illustrates the device 200 of FIG. 10 after subjecting the gate electrode 250 and metal 1010 to a silicidation process, thus forming a silicided gate electrode 1110. The resulting silicided gate electrode 1110, in the example embodiment shown, is not fully silicided. However, other embodiments may exist wherein it is fully silicided. Therefore, in the embodiment of FIG. 11, unreacted polysilicon remains therein. The silicided gate electrode 1110 includes the selected metal, in this embodiment nickel. If the metal 1010 were to comprise a different metal or alloy, the silicided gate electrode 1110 would comprise different elements.

Those skilled in the art understand the silicidation process, including subjecting the gate electrode 250 and metal layer 1010 to another anneal (e.g., a third RTA in this embodiment). This third RTA is designed to convert the gate electrode 250 to the silicided gate electrode 1110. Advantageous to the disclosure, the selection and use of the metal alloy for the metal 1010 reduces (if not eliminates) the formation of undesirable transient phases, and thus reduces (if not eliminates) the aforementioned transient stress.

The third RTA temperature typically depends on the metal being used. For example, when nickel is the first metal it is believed that the third RTA may be conducted at a temperature ranging from about 350° C. to about 550° C. and a time period ranging from about 10 second to about 100 seconds. It should be noted that other temperatures, times, and processes could be used if another metal were used.

After completing the silicided gate electrode 1110, the device 200 may be subjected to a selective removal process. For instance, in one embodiment the device 200 could be subjected to an etch recipe consisting of sulfuric acid (H₂SO₄), hydrogen peroxide (H₂O₂) and water (H₂O). This specific etch recipe has a high degree of selectivity and could easily remove any remaining portions of the metal 1010 without harming the silicided gate electrode 1110.

FIG. 12 illustrates the device 200 of FIG. 11 after subjecting the silicided gate electrode 1110 to an additional anneal (e.g., a fourth RTA in this embodiment) to form a fully silicided gate electrode 1210. The fully silicided gate electrode 1210 comprises a different phase of the metal silicide than the silicided gate electrode 1110. The fully silicided gate electrode 1210, as expected, also includes the metal alloy, nickel platinum in this embodiment.

Those skilled in the art understand this fourth RTA process. Nevertheless, in one embodiment this fourth RTA may be conducted at a higher temperature, for example one ranging from about 400° C. to about 750° C. Moreover, this fourth RTA might be conducted for a time period ranging from about 10 second to about 100 seconds. It should be noted that other temperatures, times, and processes could be used. After completing the fourth RTA, the manufacture of the device 200 would typically continue in a conventional manner, optimally resulting in a device similar to the semiconductor device 100 illustrated in FIG. 1.

It should be noted that the method for manufacturing a semiconductor device as illustrated in FIGS. 2-12 represents only one embodiment of the present disclosure. In another embodiment the exact order of the steps illustrated with respect to FIGS. 2-12 might change depending on the process flow. In yet another embodiment, various other steps could be added to the description of FIGS. 2-12.

Other more significant modifications to the process of FIGS. 2-12 also exist. For instance, other embodiments exist where the silicided source/drain regions 810 are not formed until after siliciding the gate electrode 250 to form the silicided gate electrodes 1110, 1210. Those skilled in the art understand the steps that could be used to accomplish this, as well as the steps used to accomplish other variations of that which is currently claimed.

FIG. 13 illustrates an integrated circuit (IC) 1300 having been manufactured using one embodiment of the disclosure. The IC 1300 may include devices, such as transistors used to form CMOS devices, BiCMOS devices, Bipolar devices, as well as capacitors or other types of devices. The IC 1300 may further include passive devices, such as inductors or resistors, or it may also include optical devices or optoelectronic devices. Those skilled in the art are familiar with these various types of devices and their manufacture. In the particular embodiment illustrated in FIG. 13, the IC 1300 includes NMOS devices 1310 and PMOS devices 1315. For instance, in one embodiment the NMOS devices 1310 and PMOS devices 1315 illustrated in FIG. 13 are manufactured using similar processes as described above with respect to FIGS. 2-12, and thus may both contain the metal alloy (e.g., nickel platinum in one embodiment). Located over the devices 1310, 1315 are interlevel dielectric layers 1320. Located within the interlevel dielectric layers 1320 and contacting the devices 1310, 1315 are interconnects 1330. The resulting IC 1300 is optimally configured as an operational integrated circuit.

An IC, such as the IC 1300 of FIG. 13, might be formed by providing a substrate having a p-type metal oxide semiconductor (PMOS) device region and n-type metal oxide semiconductor (NMOS) device region. Thereafter a PMOS gate structure including a PMOS gate dielectric and PMOS gate electrode could be formed over the substrate in the PMOS device region. Additionally, an NMOS gate structure including an NMOS gate dielectric and NMOS gate electrode could be formed over the substrate in the NMOS device region. Additionally, p-type source/drain regions could be formed within the substrate in the PMOS device region and proximate the PMOS gate structure, and n-type source/drain regions could be formed within the substrate in the NMOS device region proximate the NMOS gate structure. Moreover, a metal alloy layer could be formed over the PMOS gate electrode and the NMOS gate electrode. Thereafter, the metal alloy layer could be subjected to an anneal, thereby siliciding the PMOS gate electrode and the NMOS gate electrode. In one embodiment, the metal alloy layer is configured to reduce a silicidation transient stress. The siliciding ultimately results in a fully silicided PMOS gate electrode and a fully silicided NMOS gate electrode.

The phrase “providing a substrate”, as used herein, means that the substrate may be obtained from a party having already manufactured it, or alternatively may mean manufacturing the substrate themselves and providing it for its intended purpose.

Those skilled in the art to which the present disclosure relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the disclosure's scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate;patterning the layer of gate electrode material and the layer of gate dielectric material to form an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode;forming n-type source/drain regions within the substrate proximate the NMOS gate structure;siliciding the NMOS gate electrode to form a silicided gate electrode; andplacing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with the siliciding.

2. The method of claim 1 wherein placing the p-type dopant includes implanting the layer of gate electrode material with the p-type dopant.

3. The method of claim 1 wherein placing the p-type dopant includes implanting the NMOS gate electrode with the p-type dopant.

4. The method of claim 1 wherein placing the p-type dopant includes siliciding the NMOS gate electrode using a layer of metal including the p-type dopant.

5. The method of claim 1 wherein siliciding includes forming a layer of metal over the NMOS gate electrode and subjecting the layer of metal and the NMOS gate electrode to an anneal, and further wherein placing the p-type dopant includes implanting the p-type dopant into the NMOS gate electrode through the layer of metal prior to the anneal.

6. The method of claim 1 wherein the silicided gate electrode includes the p-type dopant.

7. The method of claim 1 wherein the p-type dopant is boron.

8. The method of claim 1 wherein siliciding the NMOS gate electrode includes siliciding the NMOS gate electrode using nickel.

9. A method for manufacturing a semiconductor device, comprising: forming a layer of gate electrode material over a layer of high-k gate dielectric material, wherein the layer of high-k gate dielectric material is positioned over a substrate;patterning the layer of gate electrode material and the layer of gate dielectric material to form a gate structure, wherein the gate structure includes a gate dielectric and a gate electrode;forming source/drain regions within the substrate proximate the gate structure;siliciding the gate electrode to form a silicided gate electrode; andplacing a p-type dopant within the layer of gate electrode material or the gate electrode prior to or concurrently with the siliciding.

10. The method of claim 9 wherein the gate structure is a PMOS gate structure and further wherein forming source/drain regions includes forming p-type source/drain regions.

11. The method of claim 9 wherein placing the p-type dopant includes implanting the layer of gate electrode material with the p-type dopant.

12. The method of claim 9 wherein placing the p-type dopant includes implanting the gate electrode with the p-type dopant.

13. The method of claim 9 wherein placing the p-type dopant includes siliciding the gate electrode using a layer of metal including the p-type dopant.

14. The method of claim 9 wherein siliciding includes forming a layer of metal over the gate electrode and subjecting the layer of metal and the gate electrode to an anneal, and further wherein placing the p-type dopant includes implanting the p-type dopant into the gate electrode through the layer of metal prior to the anneal.

15. The method of claim 9 wherein the silicided gate electrode includes the p-type dopant.

16. The method of claim 9 wherein the p-type dopant is boron.

17. The method of claim 9 wherein siliciding the gate electrode includes siliciding the gate electrode using nickel.

18. A method for manufacturing a semiconductor device, comprising: selecting a dopant based upon an ability to reduce a formation of high-stress transient silicide phases within a gate electrode material; andsiliciding a layer of the gate electrode material in a presence of the dopant, the dopant reducing a silicidation transient stress.

19. The method of claim 18 wherein the dopant is a p-type dopant.

20. The method of claim 19 wherein the p-type dopant is boron.

21. The method of claim 18 further including forming n-type source/drain regions in a substrate below the layer of the gate electrode material.

22. The method of claim 18 wherein the layer of the gate electrode material is located over a layer of high-k gate dielectric material formed over a substrate, and further including forming p-type source/drain regions in the substrate below the layer of the gate electrode material.

23. The method of claim 18 wherein selecting includes selecting the dopant to reduce the formation of Ni31Si12 during the siliciding.

24. The method of claim 18 wherein selecting includes selecting the dopant to eliminate the formation of Ni31Si12 during the siliciding.

25. A semiconductor device, comprising: an NMOS gate structure located over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and a fully silicided NMOS gate electrode including a p-type dopant; andn-type source/drain regions located within the substrate proximate the NMOS gate structure.

26. The semiconductor device of claim 25 wherein the p-type dopant is boron.

27. The semiconductor device of claim 25 wherein the fully silicided gate electrode includes nickel.

28. The semiconductor device of claim 25 further including interlevel dielectric layers located over the NMOS gate structure, wherein the interlevel dielectric layers include interconnects therein for contacting the NMOS gate structure.

29. A semiconductor device, comprising: a gate structure located over a substrate, wherein the gate structure includes a high-k gate dielectric and a fully silicided gate electrode having a p-type dopant; andsource/drain regions located within the substrate proximate the gate structure.

30. The semiconductor device of claim 29 wherein the p-type dopant is boron.

31. The semiconductor device of claim 29 wherein the fully silicided gate electrode includes nickel.

32. The semiconductor device of claim 29 wherein the source/drain regions are p-type source/drain regions.

33. The semiconductor device of claim 29 further including interlevel dielectric layers located over the gate structure, wherein the interlevel dielectric layers include interconnects therein for contacting the gate structure.