Patent Application
20250167191
The present disclosure relates generally to chip stacking architectures, and more particularly to a chip stacking architecture with a logic chip that communicates with the substrate using through-silicon vias located in the memory chip.
Chip stacking is a method of attaching integrated circuiits (commonly referred to as simply “chips”) vertically to increase efficiency and make better use of the available space. An integrated circuit is a set of electronic circuits on one small flat piece (or “chip”) of semiconductor material, usually silicon. The vertical assemblies can involve chips of the same size or different sizes. When the chips are different in size, they are stacked offset one on top of another, usually three or four die (small block of semiconducting material on which a given functional circuit is fabricated). They are connected to each other typically by a film adhesive, and electrically, by wire bonding or flip chip methods. The stack is then connected to the substrate in the same manner. If the chips are the same size, invariably they have a staggered arrangement.
Currently, chip stacking typically consists of stacked high bandwidth memory (HBM) chips, packaged on a common substrate next to a logic chip. HBM is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI (artificial intelligence) ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays), etc.
HBM achieves higher bandwidth while using less power by stacking up to eight DRAM (dynamic random-access memory) dies and an optional base die which can include buffer circuitry and test logic. The stack is often connected to a memory controller on a GPU (graphic processing unit) or a CPU (central processing unit) through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack, the die are vertically interconnected by through-silicon vias (TSVs) and microbumps.
As discussed above, chip stacking typically consists of stacked HBM chips, packaged on a common substrate next to a logic chip. In such an architecture, heat can be evacuated from the top of the memory stack without overheating the chips located at the bottom of the memory stack because the memory chips produce relatively little heat. In such cases, where the logic chip is located on the substrate besides the stack of memory chips, the bandwidth is constrained by the limited wiring capacity in the substrate. Higher memory bandwidth can be obtained by placing the logic and memory chips in the same vertical stack with the memory chips located on top of the logic chip. With the memory chips being located on top of the logic chip, the memory chips serve as a thermal insulator limiting the amount of heat that a top-contact cooling structure can remove from the bottom located logic chip. In addition to thermal difficulties, an arrangement with the memory chips stacked on top of the logic chip requires the logic chip designer to include through-silicon vias (TSVs) in the logic chip in order to pass power and signal connections from the logic chip both upwards to the memory chips and downwards to the interconnect substrate. If the logic chip was to be a high-power density processor using linewidth chip fabrication technology, then there would be a high cost to reserving space in the logic chip for TSVs. Not only would there be a large number of logic circuits lost for every TSV added to the logic chip, but such a design would also require a custom logic chip design that would be different from the current standard logic chip.
As a result, currently designed chip stacking architectures are not effective in cooling a higher-power logic chip as well as effectively providing power and signal connections and high bandwidth to the logic chip.
In one embodiment of the present disclosure, an integrated circuit device comprises a substrate and one or more memory chips stacked on top of the substrate. The integrated circuit device further comprises a logic chip stacked on top of the one or more memory chips, where the logic chip communicates with the substrate via through-silicon vias located in the one or more memory chips.
Additionally, in one embodiment of the present disclosure, the through-silicon vias are utilized for power connections.
Furthermore, in one embodiment of the present disclosure, the through-silicon vias are utilized for signaling connections.
Additionally, in one embodiment of the present disclosure, the one or more memory chips correspond to high bandwidth memory chips.
Furthermore, in one embodiment of the present disclosure, a first portion of the through-silicon vias terminate on one of the one or more memory chips.
Additionally, in one embodiment of the present disclosure, the first portion of the through-silicon vias are used to communicate with the one of the one or more memory chips.
Furthermore, in one embodiment of the present disclosure, a second portion of the through-silicon vias are electronically disconnected from a specific memory chip of the one or more memory chips.
Additionally, in one embodiment of the present disclosure, the second portion of the through-silicon vias are used for enabling the logic chip to communicate with the substrate.
Furthermore, in one embodiment of the present disclosure, the logic chip comprises a processor.
Additionally, in one embodiment of the present disclosure, the logic chip comprises a buffer.
Furthermore, in one embodiment of the present disclosure, the logic chip is stacked on top of the one or more memory chips via decoupling capacitors.
Additionally, in one embodiment of the present disclosure, the logic chip is stacked on top of the one or more memory chips via a voltage regulator.
Furthermore, in one embodiment of the present disclosure, the one or more memory chips are stacked on top of the substrate via a silicon spreader.
Additionally, in one embodiment of the present disclosure, a first portion of the through-silicon vias are connected to a first core logic domain within the one or more memory chips at a first voltage level. Furthermore, in one embodiment of the present disclosure, a second portion of the through-silicon vias are connected to a second core logic domain within the one or more memory chips at a second voltage level, where the second voltage level is higher than the first voltage level.
Furthermore, in one embodiment of the present disclosure, the logic chip comprises a step-down switched capacitor power converter circuit.
Additionally, in one embodiment of the present disclosure, the step-down switched capacitor power converter circuit corresponds to a 2:1 step-down converter.
Furthermore, in one embodiment of the present disclosure, the step-down switched capacitor power converter circuit produces a regulated voltage that is at a lower voltage level than a voltage level of the one or more memory chips.
Additionally, in one embodiment of the present disclosure, a portion of contacts of the through-silicon vias in the one or more memory chips are connected to the substrate using a redistribution layer process.
Furthermore, in one embodiment of the present disclosure, the redistribution layer process is used to expand a contact pitch.
Additionally, in one embodiment of the present disclosure, one of the one or more memory chips is used as a quad-level cell flash memory.
Accordingly, embodiments of the present disclosure provide a high-performance, cost-effective chip stacking architecture while cools a high-power logic chip, provides power and signal connections to the logic chip through the memory chips and provides high bandwidth between the logic chip and the memory chips.
The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present disclosure in order that the detailed description of the present disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter which may form the subject of the claims of the present disclosure.
A better understanding of the present disclosure can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:
In one embodiment of the present disclosure, an integrated circuit device comprises a substrate and one or more memory chips stacked on top of the substrate. The integrated circuit device further comprises a logic chip stacked on top of the one or more memory chips, where the logic chip communicates with the substrate via through-silicon vias located in the one or more memory chips.
In this manner, a high-performance, cost-effective chip stacking architecture is provided which cools a high-power logic chip, provides power and signal connections to the logic chip through the memory chips and provides high bandwidth between the logic chip and the memory chips.
Additionally, in one embodiment of the present disclosure, the through-silicon vias are utilized for power connections.
In this manner, power connections are provided to the logic chip through the memory chips.
Furthermore, in one embodiment of the present disclosure, the through-silicon vias are utilized for signaling connections.
In this manner, signaling connections are provided to the logic chip through the memory chips.
Additionally, in one embodiment of the present disclosure, the one or more memory chips correspond to high bandwidth memory chips.
In this manner, the memory chips provide high bandwidth and low power consumption.
Furthermore, in one embodiment of the present disclosure, a first portion of the through-silicon vias terminate on one of the one or more memory chips.
In this manner, communication can be established with the memory chip upon which the through-silicon vias terminate.
Additionally, in one embodiment of the present disclosure, the first portion of the through-silicon vias are used to communicate with the one of the one or more memory chips.
In this manner, communication with the memory chips can be established.
Furthermore, in one embodiment of the present disclosure, a second portion of the through-silicon vias are electronically disconnected from a specific memory chip of the one or more memory chips.
In this manner, communication between the logic chip and the substrate can be established.
Additionally, in one embodiment of the present disclosure, the second portion of the through-silicon vias are used for enabling the logic chip to communicate with the substrate.
In this manner, the logic chip is able to communicate with the substrate via a portion of the through-silicon vias in the memory chips.
Furthermore, in one embodiment of the present disclosure, the logic chip comprises a processor.
In this manner, the processor to substrate power and signal connections may be established.
Additionally, in one embodiment of the present disclosure, the logic chip comprises a buffer.
In this manner, the current capacity of the signal is boosted so as to be able to drive a load.
Furthermore, in one embodiment of the present disclosure, the logic chip is stacked on top of the one or more memory chips via decoupling capacitors.
In this manner, one part of a circuit may be isolated or decoupled from another.
Additionally, in one embodiment of the present disclosure, the logic chip is stacked on top of the one or more memory chips via a voltage regulator.
In this manner, a steady constant voltage supply is ensured through all operational conditions.
Furthermore, in one embodiment of the present disclosure, the one or more memory chips are stacked on top of the substrate via a silicon spreader.
In this manner, the wetting, spreading, and penetration of chemicals is improved.
Additionally, in one embodiment of the present disclosure, a first portion of the through-silicon vias are connected to a first core logic domain within the one or more memory chips at a first voltage level. Furthermore, in one embodiment of the present disclosure, a second portion of the through-silicon vias are connected to a second core logic domain within the one or more memory chips at a second voltage level, where the second voltage level is higher than the first voltage level.
In this manner, different voltage levels may be utilized for powering different elements.
Furthermore, in one embodiment of the present disclosure, the logic chip comprises a step-down switched capacitor power converter circuit.
In this manner, a high voltage power is converted into a lower voltage power.
Additionally, in one embodiment of the present disclosure, the step-down switched capacitor power converter circuit corresponds to a 2:1 step-down converter.
In this manner, the voltage level may be converted into a lower voltage power by a factor of two.
Furthermore, in one embodiment of the present disclosure, the step-down switched capacitor power converter circuit produces a regulated voltage that is at a lower voltage level than a voltage level of the one or more memory chips.
In this manner, a voltage level is produced that is lower than the voltage level of the memory chips.
Additionally, in one embodiment of the present disclosure, a portion of contacts of the through-silicon vias in the one or more memory chips are connected to the substrate using a redistribution layer process.
In this manner, an extra metal layer is established that makes its I/O pads available in other locations of the substrate for better access to the pads where necessary.
Furthermore, in one embodiment of the present disclosure, the redistribution layer process is used to expand a contact pitch.
In this manner, the distance from the center of one contact to the center of the next contact on the substrate is expanded.
Additionally, in one embodiment of the present disclosure, one of the one or more memory chips is used as a quad-level cell flash memory.
In this manner, 4 bits of data per memory cell can be stored.
As stated above, currently, chip stacking typically consists of stacked high bandwidth memory (HBM) chips, packaged on a common substrate next to a logic chip. HBM is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI (artificial intelligence) ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays), etc.
HBM achieves higher bandwidth while using less power by stacking up to eight DRAM (dynamic random-access memory) dies and an optional base die which can include buffer circuitry and test logic. The stack is often connected to a memory controller on a GPU (graphic processing unit) or a CPU (central processing unit) through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack, the die are vertically interconnected by through-silicon vias (TSVs) and microbumps.
As discussed above, chip stacking typically consists of stacked HBM chips, packaged on a common substrate next to a logic chip. In such an architecture, heat can be evacuated from the top of the memory stack without overheating the chips located at the bottom of the memory stack because the memory chips produce relatively little heat. In such cases, where the logic chip is located on the substrate besides the stack of memory chips, the bandwidth is constrained by the limited wiring capacity in the substrate. Higher memory bandwidth can be obtained by placing the logic and memory chips in the same vertical stack with the memory chips located on top of the logic chip. With the memory chips being located on top of the logic chip, the memory chips serve as a thermal insulator limiting the amount of heat that a top-contact cooling structure can remove from the bottom located logic chip. In addition to thermal difficulties, an arrangement with the memory chips stacked on top of the logic chip requires the logic chip designer to include through-silicon vias (TSVs) in the logic chip in order to pass power and signal connections from the logic chip both upwards to the memory chips and downwards to the interconnect substrate. If the logic chip was to be a high-power density processor using linewidth chip fabrication technology, then there would be a high cost to reserving space in the logic chip for TSVs. Not only would there be a large number of logic circuits lost for every TSV added to the logic chip, but such a design would also require a custom logic chip design that would be different from the current standard logic chip.
As a result, currently designed chip stacking architectures are not effective in cooling a higher-power logic chip as well as effectively providing power and signal connections and high bandwidth to the logic chip.
The embodiments of the present disclosure provide a means for a chip stacking architecture that is effective in cooling a higher-power logic chip as well as effectively providing power and signal connections and high bandwidth to the logic chip. In one embodiment, an integrated circuit device includes a chip stacking architecture that includes a substrate, one or more memory chips stacked on top of the substrate and a logic chip stacked on top of the one or more memory chips, where the logic chip communicates with the substrate via through-silicon vias located in the memory chip(s). A portion of the through-silicon vias in the memory chip(s) are electronically disconnected from a specific memory chip and therefore are able to be used to enable the logic chip to communicate with the substrate. In this manner, such a chip stacking architecture provides a high-performance, cost-effective chip stacking architecture, which cools a high-power logic chip, provides power and signal connections to the logic chip through the stack of one or more memory chips and provides high bandwidth between the logic chip and the memory chip(s). A further description of these and other features will be provided below.
Referring now to the Figures in detail,
In one embodiment, such memory chips 102 correspond to high bandwidth memory (HBM) chips, which utilize a 3D stacking technology, which enables various layers of memory chips 102 to be stacked on top of each other by vertical channels, referred to herein as through-silicon vias 103 (“TSVs”).
TSVs 103, as used herein, refer to vertical electrical connections (vias) that pass completely through the stack of memory chips 102. TSVs 103 are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits.
In one embodiment, as shown in
As discussed above, currently designed chip stacking architectures are not effective in cooling a higher-power logic chip as well as effectively providing power and signal connections and high bandwidth to the logic chip. Embodiments of the present disclosure provide a means for a chip stacking architecture, such as illustrated in
In one embodiment, as discussed above, memory chips 102 correspond to high bandwidth memory (HBM) chips. In such an embodiment, memory chips 102 include hundreds to thousands of TSVs 103 arranged in logical quadrants. In one embodiment, in a given memory chip 102, a portion (e.g., one-fourth) of the signal TSVs 103 terminate on that specific memory chip 102 (e.g., memory chip 102A) and are used to communicate with that memory chip 102 (e.g., memory chip 102A). A “signal TSV 103,” as used herein, refers to a TSV that transmits signals. The other portion (e.g., three quarters) of the signal TSVs 103 (e.g., 750 TSVs 103) are electrically disconnected from that specific memory chip 102 (e.g., memory chip 102A). In one embodiment, such locally unconnected signal TSVs 103 in an HBM memory chip 102 are used to pass general nonmemory signals between logic chip 104, such as a processor 106 of logic chip 104, and substrate 101. That is, such locally unconnected signal TSVs 103 are used for enabling logic chip 104, such as processor 106, to communicate with substrate 101. Examples of processor 106 include Intel Xeon Phi® processor, AI (artificial intelligence) processor, Sapphire Rapids Xeon SP processor, etc.
In one embodiment, memory chip TSVs 103 supply power to logic chip 104. In one embodiment, memory chip 102 has hundreds or thousands of power TSVs 103. A “power TSV 103,” as used herein, refers to a TSV that transmits power. In one embodiment, a first portion of power TSVs 103 are connected to a core logic domain within memory chip 102 at a first voltage level, such as 1.2 V. A second portion of power TSVs 103 are connected to a core logic domain within memory chip 102 at a second voltage level, which is higher than the first voltage level. In one embodiment, the second portion of TSVs 103 is smaller than the first portion of TSVs 103. In this manner, different voltage levels may be utilized for powering different elements.
An illustration of TSVs 103 in memory chips 102 being used to communicate with memory chips 102 as well as enabling logic chip 104 to communicate with substrate 101 is provided in
Referring to
As illustrated in
Furthermore, a portion of TSVs 103, such as signal or power TSVs, are electrically disconnected from memory chips 102 and are used by logic chip 104 to communicate with substrate 101. For example, TSVs 103A, 103B, 103E, and 103F are used for connecting logic chip 104 and substrate 101. TSVs 103A-103H may collectively or individually be referred to as TSVs 103 or TSV 103, respectively.
While
Returning to
In one embodiment, such a step-down switched capacitor power converter circuit 107 provides a roughly 0.6 V core voltage logic domain to logic chip 104 using the 1.2 V power TSVs 103. In one embodiment, the higher-voltage power TSVs 103 are used for phased locked loops, input/output (I/O) drivers or other functions in logic chip 104 with no power conversion. In one embodiment, some of memory chip's 102 unconnected signal TSVs 103 are used to provide additional voltages to logic chip 104 instead of being used for signal connections.
In one embodiment, step-down switched capacitor power converter circuit 107 produces a regulated voltage that is at a lower voltage level than a voltage level of memory chips 102. In this manner, a voltage level is produced that is lower than the voltage level of memory chips 102.
In one embodiment, the lateral pitch (minimum center-to-center distance between interconnect lines) of memory chip TSVs 103 is smaller in comparison to the contact pitches (the distance from the center of one contact to the center of the next contact) on substrate 101. A contact, as used herein, refers to a tiny and distinct structure that forms an electrical pathway, such as between a first interconnect layer and a transistor. In such an embodiment, the contacts of the bottom located TSVs 103, such as in memory chip 102A, are connected to substrate 101 below the stack. In one embodiment, the contacts of such TSVs 103 are connected to substrate 101 below the stack using a redistribution layer process, which is used to expand the contact pitch. A redistribution layer, as used herein, refers to an extra metal layer that makes its I/O pads available in other locations of substrate 101 for better access to the pads where necessary.
Alternatively, in one embodiment, fine pitch build-up layers are added to the top of substrate 101 to address the lateral pitch of memory chip TSVs 103 being smaller in comparison to the contact pitches on substrate 101
An alternative embodiment of integrated circuit device 100 is shown in
Referring to
As shown in
Furthermore, as illustrated in
In one embodiment, the regulator of element 302 is configured to regulate from a voltage level of memory chips 102 to the voltage level of logic chip 104.
“Decoupling capacitors,” as used herein, refer to capacitors that are used to isolate or decouple one part of a circuit from another.
“Interconnects 303,” as used herein, refer to structures that connect two or more circuit elements together electrically.
Furthermore, as illustrated in
Additionally, as illustrated in
Furthermore, in one embodiment, one of memory chips 102, such as memory chip 102A, may be used as a quad-level cell flash memory. A quad-level cell flash memory, as used herein, refers to a form of NAND flash memory that can store up to 4 bits of data per memory cell.
In this manner, such a chip stacking architecture provides a high-performance, cost-effective chip stacking architecture, which cools a high-power logic chip, provides power and signal connections to the logic chip through the stack of one or more memory chips and provides high bandwidth between the logic chip and the memory chip(s).
Furthermore, the principles of the present disclosure improve the technology or technical field involving chip stacking architectures.
As discussed above, currently, chip stacking typically consists of stacked high bandwidth memory (HBM) chips, packaged on a common substrate next to a logic chip. HBM is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI (artificial intelligence) ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays), etc. HBM achieves higher bandwidth while using less power by stacking up to eight DRAM (dynamic random-access memory) dies and an optional base die which can include buffer circuitry and test logic. The stack is often connected to a memory controller on a GPU (graphic processing unit) or a CPU (central processing unit) through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack, the die are vertically interconnected by through-silicon vias (TSVs) and microbumps. As discussed above, chip stacking typically consists of stacked HBM chips, packaged on a common substrate next to a logic chip. In such an architecture, heat can be evacuated from the top of the memory stack without overheating the chips located at the bottom of the memory stack because the memory chips produce relatively little heat. In such cases, where the logic chip is located on the substrate besides the stack of memory chips, the bandwidth is constrained by the limited wiring capacity in the substrate. Higher memory bandwidth can be obtained by placing the logic and memory chips in the same vertical stack with the memory chips located on top of the logic chip. With the memory chips being located on top of the logic chip, the memory chips serve as a thermal insulator limiting the amount of heat that a top-contact cooling structure can remove from the bottom located logic chip. In addition to thermal difficulties, an arrangement with the memory chips stacked on top of the logic chip requires the logic chip designer to include through-silicon vias (TSVs) in the logic chip in order to pass power and signal connections from the logic chip both upwards to the memory chips and downwards to the interconnect substrate. If the logic chip was to be a high-power density processor using linewidth chip fabrication technology, then there would be a high cost to reserving space in the logic chip for TSVs. Not only would there be a large number of logic circuits lost for every TSV added to the logic chip, but such a design would also require a custom logic chip design that would be different from the current standard logic chip. As a result, currently designed chip stacking architectures are not effective in cooling a higher-power logic chip as well as effectively providing power and signal connections and high bandwidth to the logic chip.
Embodiments of the present disclosure improve such technology by fabricating an integrated circuit device with a chip stacking architecture that includes a substrate, one or more memory chips stacked on top of the substrate and a logic chip stacked on top of the one or more memory chips, where the logic chip communicates with the substrate via through-silicon vias located in the memory chip(s). A portion of the through-silicon vias in the memory chip(s) are electronically disconnected from a specific memory chip and therefore are able to be used to enable the logic chip to communicate with the substrate. In this manner, such a chip stacking architecture provides a high-performance, cost-effective chip stacking architecture, which cools a high-power logic chip, provides power and signal connections to the logic chip through the stack of one or more memory chips and provides high bandwidth between the logic chip and the memory chip(s). Furthermore, in this manner, there is an improvement in the technical field involving chip stacking architectures.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
