Patent Application
20210223314
The present invention relates to testing of electronic circuits.
In designing and producing integrated circuits (IC's), today's semiconductor manufacturers have very sophisticated tools to analyze their designs via computer simulations and analysis. These tools allow the engineers to present information to their design and see if it reacts in the way that is expected. And these tools have reached capabilities that without them, the chips that are in our cell phones for example, would be impossible to make work.
However, those simulations are not the actual IC operating. The analysis of the actual performance of the IC is left to the “Test Team”. This team, which typically includes design and test engineers, utilize today's automatic IC test systems to both stimulate the IC and measure its response.
However, the visibility into the functionality of the majority of circuits on an IC is limited. From the normal connections to the IC, test engineers can only directly stimulate and measure a small portion of the circuits. These circuits, known collectively as the input/output pins, give access to less than 5% of the total circuits on the IC and many times less than 1%.
Test structures such as JTAG are added to IC designs so the test teams can load information into the inter-circuits, test their functionality and then “shift” the data out for analysis. These JTAG circuits are used only for test and typically have nothing to do with the functionality of the IC. They are also limited in that the JTAG data shows the engineers information that changed many digital steps earlier. Very little information is provided about the dynamic operation of those circuits.
In one aspect, a technique is disclosed for analyzing the inter-workings of an integrated circuit by measuring the current being consumed by that integrated circuit at selected points in a functional test. The technique requires the proper algorithm, a computer system, measurement hardware and a graphical analysis tool to provide insight into the data accumulated and the functioning of the integrated circuit.
In another aspect, a method for testing an integrated circuit (IC) includes: instructing the test system to run a repetitive loop using a selected functional test as the stimulus; at selected steps in the functional test, measuring and recording one or more currents being consumed by the IC.
In another aspect, systems and methods are disclosed for testing a device under test (DUT) by receiving a test pattern for a functional test, wherein the test pattern includes a test vector, an expected test result, and an expected power consumption; instructing the test system to run a repetitive loop using a selected functional test as the stimulus; at selected steps in the functional test, measuring power consumption of the DUT; and validating the DUT based on validating the test vector and the power consumption with one or more expected test result patterns and expected power consumption patterns. For example, in implementations, the power may be consumed by one or more pins on the IC. The system tracks the current of multiple supplies, at various voltages, as part of the measurement.
Advantages of the system may include one or more of the following. The system gives professional integrated circuit designers and their teams an effective tool to look inside today's ultra-complex circuits—discovering and confirming what is really going on. The system's capability can have positive impact on yet another aspect of the semiconductor industry. There is often fear that during design and fabrication, unauthorized circuits could be added to the design that would give certain individuals ways to usurp any security precautions. Semiconductor designers and manufacturers can use the device profiles generated by the instant system to make sure that any unexpected operation of the chip indicative of unwanted circuitry or tampering attempt is detected and analyzed.
Other advantages of the present system may include one or more of the following. The system enhances test performance and decrease the test time and error ratio and cost of the products. In contrast to the “rack-n-stack” instruments available for the engineering bench or after thought add-ons to an existing test system, the blades are carefully architected to assure precise synchronization, short test times and production worthy stability. Rather than accept general-purpose solutions trying to solve a wide set of generic needs, Cobra blades focus on the key issues that minimize the real cost of each test challenge. This maximizes the utilization of the purchased capital, directly lowering the Cost Of Test for the user.
The system's centralized power distribution system assures that all instruments have the precise set of voltages and currents desired, in a low-noise environment. This arrangement provides a simplified power distribution to provide a more reliable ATE system by limiting the diversity of bulk power supplies to one voltage. The custom-tailored power requirements for now and the future based upon a single voltage reference provided to all major components of Automatic Test Equipment. Power distribution of a single voltage reference has been historically impractical to implement given the circuit demands of Automatic Test Equipment, but this is made possible using the centralized power distribution of the present system.
Another advantage of the system is offered through the “Central Reference Clock” subsystem. A stable, precision oscillator provides the “heartbeat” for test functions and is broadcasted to all instruments. This reference clock is physically connected at the center of the Cobra Motherboard—an origin point that facilitates a clock distribution that approaches “Zero Clock Skew”.
In the following description, details of various implementations are set forth to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring embodiments of the present invention. In addition, features of the different embodiments described hereinafter may be combined with each other, unless specifically noted otherwise.
One embodiment called VectorEyes expands the engineers' visibility into the operation of integrated circuits (ICs). VectorEyes does this by instructing the test system to run a repetitive loop using a selected functional test as the stimulus. Then, at selected steps in the functional test, measure and record the supply current being consumed by the IC. The power may be consumed by one or more pins on the IC. The system tracks the current of multiple supplies, at various voltages, as part of the measurement.
The term Vector, as used herein and commonly used in the IC test industry, refers to the pattern of 1's and 0's that are either being sent to the IC being tested (known as the DUT for device under test), or expected back from the DUT. Each vector represents one step in a functional test pattern. Production IC tests may contain one or more of these “vector patterns” with each pattern containing one or more vectors. Million step patterns are not uncommon. The pattern used herein includes over 600,000 vectors.
These vector patterns are developed during the design simulations and represent the engineering team's “best effort” at insuring proper IC performance. Best effort referring to the fact that exhaustive testing of today's IC's would take many millions of years to complete. Note that a circuit with only 55 transistors would take 1.13 years at 10 GHz to exhaustively test. Today's circuits have million and even billions of transistors.
The VectorEyes Process is detailed next. The software application and the test hardware allow the user to select any valid vector pattern as the digital stimulus for the test. The user can also select which of the IC's power supplies will be part of the test.
The user then directs the system which sections of the functional test pattern should be used for the measurement portion of the testing. This allows engineers to focus on certain areas of interest, without waiting for data from areas of the vector pattern of less concern.
The user can set:
As well, the software allows the user to select the number of current measurements to make at each vector being measured. While currents can be seen by a single measurement, fixturing noise makes interpretation of the data difficult, if not impossible. But, by utilizing the “Law of Large Numbers” first described by Italian mathematician Gerolamo Cardano (1501-1576), measurements that peer down through the noise to see the real information are possible with impressive resolution and stability.
By making hundreds or even thousands of measurements at each measurement point, any random noise is averaged away. And, for every doubling in the number of samples, the resolution of the test hardware is increase by 0.41% or doubled every factor of four. For example, making 1024 measurements allows a 16-bit measurement system to measure with 21 bit or 0.0000476% resolution, while decreasing the noise by a factor of 32.
There are two other considerations regarding the actual current measurement and both involve time. The test system utilized herein can stop the pattern at a measurement point and make a first measurement in under 50 uS with subsequent multi-sample measurements made every 37 uS. As well, the user can select additional delay times (microseconds to seconds) before starting the first measurement. Both the time to make a measurement and the optional delay can affect the results.
As the time from the last vector execution increases, observed waveforms can very dependent on the network associated with the power pin of the device under test and what circuits on the DUT are consuming power.
Test fixtures normally have lumped capacitance very near the actual device power pin to smooth out the power supply fluctuations caused during its normal operation. When the device is used in its eventual customer's product circuit, that circuit will also include similar lumped or “bypass” capacitance. Values of 0.1 ufd to 1.0 ufd are common. The effects of these bypass capacitors must be taken into consideration when interpreting the VectorEyes data.
The vector pattern is presented to the device under test in a repetitive loop in one of two sequences. The first type, dynamic, starts at the first vector and then executes vectors until the next measurement point. It makes a measurement and then returns to the first vector and re-executes the pattern up to the last measurement point plus the vector steps between measurements. It does this until it is at or beyond the stop vector.
The dynamic vector address sequence for a pattern starting at 0, for 8 vectors, stepping by two vectors would be: 0, 1, M, 0, 1, 2, 3, M, 0, 1, 2, 3, 4, 5, M, 0, 1, 2, 3, 4, 5, 6, 7, M (the M's indicate when the current measurement is made).
The static sequence is simpler. It starts at the first address and increments that address to the next measurement point. It continues this until it is at the stop address. The static address sequence for the same parameters above would be: 0, 1, M, 2, 3, M, 4, 5, M, 6, 7, M.
There are two primary considerations for the user's choice of the dynamic or static address sequence. First is the dynamic sequence makes each current measurement right after all the vectors in the pattern between the start and this measure point have just run. In that way, any nodes in the circuit under test that are subject to decay are still valid during the actual measurement. However, for large patterns, the dynamic sequence can be billions of cycles long requiring extensive test times.
The static sequence measures each current after executing only the vectors between measurement points. This makes large patterns run much faster. However, measurements at the end of large patterns, may be made seconds after the vectors in the first part of the pattern were run. Any dynamic nodes in the IC will have become invalid. However, circuits based on static logic will be measured correctly and quickly.
The computer collects all the data at each measurement point, calculates the average and then writes the vector address and averaged value to the disk. The data is formatted such that any web language such as HTML5 can be used and a compatible device can view and manipulate the information once the test has completed.
The test system used to make these measurements includes the following features:
The test system supporting VectorEyes has the capability to start a new vector pattern within 20 uS and make a supply current measurement every 37 uSec. A 1000 step vector pattern, running the dynamic sequence, stopping at every vector and making 1024 measurement can complete the task and plot the results in under 30 seconds. Tools that take hours and hours to run have limited use to an engineering team.
In
Security
The VectorEyes capability can have positive impact on yet another aspect of the semiconductor industry. There is often fear that during design and fabrication, unauthorized circuits could be added to the design that would give certain individuals ways to usurp any security precautions. Semiconductor designers and manufacturers can use VectorEyes profiles to make sure that any unexpected operation of the chip is detected and analyzed. As one test expert stated, “You can't fool current.”
In one embodiment, the Cobra Test-head has 24 “slots” where tester's blades can be inserted into to add functionality to the Test-head. The Test-head supports a multitude of configurations with presently up to 1920 digital channels in a 900 mm×550 mm cylindrical package. The cylindrical nature of the system benefits the user by providing the shortest possible path between tester functions and the device under test (DUT). Each blade is contained in it own metal chassis with local cooling, mechanical support systems, and shields the electronics from EMF noise. Each Cobra test system will include a TIB chassis in all slots. Slots without active blades will hold “Dummy” blade chassis that maintain balance in the system. The system operates with any number of active blades from 1 to 24. The chassis protects the blade during shipping and handling, also makes a very user-friendly replaceable module. Each of the blades contained in the test head is electrically isolated from the other instruments or any other source. This “Floating” power system assures that each instrument is in the best possible “electrical noise environment” supporting high fidelity, high stability operation of all tester functions. Combined with the shielding provided by the instrument chassis, Cobra is one of the quietest test systems ever constructed. To support the high-density packaging embodied in the Test-head, the cooling system utilizes a computer controlled set of redundant, magnetically floating fans. Changes in room temperature or power duty cycles are managed by altering fan speeds and turning on heaters near critical instrument circuits—assuring stable temperatures and predictable instrument performance. The cooling controllers also monitor the 48 volt system supply to assure overall proper system performance. Should the temperature or the system supply be found faulty, the controller signals an “Alarm” and causes a system shut down. The controller also has a “Red or Green” indicator light which signals when the instruments are operating correctly or when there is a problem and the blade module needs replacement.
One implementation of the Cobra instruments contains various standard features in addition to the circuits required to provide their specific functions, among others:
The Testhead provides the TIBs: mechanical support, power distribution, cooling, high-speed communications, advanced clocking and coherent synchronization. It is designed to provide a benevolent, supportive environment for optimized performance. A stable, low-noise electronic environment is necessary to fully assure the quality of microelectronic circuits during the test process, this is the core of The Cobra Test System. From its computer controlled cooling, to its ultra-low-noise power distribution process and isolated communications bus, Cobra is the rock-solid reference point demanded by integrated circuit engineering and manufacturing.
1. Most Instruments will have an Isolated Digital and an Isolated Analog. These will need to be tied together at the DUT.
2. The USB_GND will also need to be tied to the DUT ground if used.
3. The Slot #1 CAL ground signals on Ardent Block “A” pins A1 and A2 should only be required for Calibration and are not required to be tied to the DUT ground.
4. The User Sync associated Isolated Digital ground Ardent Block “B” pins B25 and B26 is only provided for a Scope sync. This signal is only available from selected Digital Instruments and should not be tied to the DUT ground. The User Sync signal and the grounds should go to a set of test points.
5. The GND_POWER on the 25th Connector pins 4, 5, and 6 is only used when controller device V48LB is required to generate special voltages on the DUT card. It should not be tied to the DUT ground.
Further embodiments of the present invention provide a method for testing a device under test. In a first step, an input signal is received from the device under test and information describing the input signal is written to a memory. In a second step, the information describing the input signal is read from the memory and an output signal is provided for the device under test based on the information describing the input signal read from the memory.
Further embodiments of the present invention provide an apparatus for configuring the ATE. The apparatus is adapted to configure the automatic test equipment to receive an input signal from a device under test and to write information describing the input signal to a memory. The apparatus is further adapted to configure the automatic test equipment to read the information describing the input signal from the memory 16 and to provide an output signal for the device under test based on the information describing the input signal read from the memory.
Further embodiments of the present invention provide a method for configuring the automatic test equipment. In a first step, the automatic test equipment is configured to receive an input signal from a device under test and to write information describing the input signal to a memory. In a second step, the automatic test equipment is configured to read the information describing the input signal from the memory and to provide an output signal for the device under test based on the information describing the input signal read from the memory. Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be executed by (or using) a hardware apparatus, like for example, a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some one or more of the most important method steps may be executed by such an apparatus.
Depending on certain implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a Blu-Ray, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Therefore, the digital storage medium may be computer readable.
Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.
Generally, embodiments of the present invention can be implemented as a computer program product with a program code, the program code being operative for performing one of the methods when the computer program product runs on a computer. The program code may for example be stored on a machine readable carrier.
Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.
In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.
A further embodiment of the inventive methods is, therefore, a data carrier (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium or the recorded medium are typically tangible and/or non-transitionary.
A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may for example be configured to be transferred via a data communication connection, for example via the Internet.
A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein.
A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.
A further embodiment according to the invention comprises an apparatus or a system configured to transfer (for example, electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may, for example, be a computer, a mobile device, a memory device or the like. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver.
In some embodiments, a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware apparatus.
The above described embodiments are merely illustrative for the principles of the present invention. It is understood that modifications and variations of the arrangements and the details described herein will be apparent to others skilled in the art. It is the intent, therefore, to be limited only by the scope of the impending patent claims and not by the specific details presented by way of description and explanation of the embodiments herein.
