Patent Application
20100289145
The present invention relates generally to a system and method for integrated circuit packaging, and more particularly to a structure and method which enhances the performance of wafer chip scale packages.
Integrated circuit (IC) packaging plays a vital role in the continued development of integrated circuits. The IC device can include a semiconductor chip (chip, wafer section), and some form of packaging which protects the chip. Packaging can be a significant factor in the overall performance and desirability of the IC for a specific use. The size of the IC package which contains the chip, in part, dictates the final size of the electronic device containing the IC. Further miniaturizing semiconductor packages is a continuing goal of design engineers.
Various package designs have been developed in an attempt to minimize the size of the completed device. For example, one embodiment of a quad flat no-lead (QFN) device includes a semiconductor chip having an inactive (back) surface attached to a leadframe with chip attach material. An active (front, circuit) side of the chip faces away from the leadframe. Interconnect terminals (in this instance, bond pads) on the active surface of the chip are wire bonded to leads of the leadframe. The chip, chip pad, and a portion of the leads are encapsulated in plastic resin or other encapsulation material. To minimize device size of the QFN device, the leadframe leads exposed on the outer surface of the device are flush with surfaces of the encapsulated package. The leads can then be surface mounted to lands of a printed circuit board (PCB) or other substrate using solder or other conductive material.
The leadframe of a QFN device can also include an exposed thermal pad formed as a lower surface of the chip pad which is exposed by the encapsulation material. The exposed thermal pad can be attached to a ground land of a PCB or other substrate to function as a heat sink to draw heat away from the chip and package during operation.
Another type of package design which provides a small device footprint is wafer chip scale packaging (WCSP). WCSP offers a compact package for integrated circuits as a resin encapsulation is not required. With a WCSP device, solder balls (or similarly, solder bumps, posts, and so forth) can be directly attached to interconnect terminals of the semiconductor chip. Solder ball pitch can be as small as 500 micrometers or less. The active surface of the semiconductor chip is protected by a patterned passivation layer which can include, for example, various polymers, organic materials, etc., which protects the active surface of the semiconductor chip. The chip and solder balls are placed active-side down on a PCB or other substrate in a flip chip style attachment, and the solder balls are reflowed to electrically couple the bond pads on the chip with conductive lands on the PCB. Because they are not encapsulated, but instead use a thinner passivation layer for protection, WCSP devices also have the advantage of being thermally efficient. One (or more) solder ball can be connected to a PCB land, the land is connected with a trace, which is in turn connected to a via, and the via can be coupled with a plane, such as a ground plane, of the PCB. If more than one solder ball is coupled with the ground plane, these grounded solder balls can be designed and located at various sites around the active surface of the chip. Vias which are placed near or under a device are often referred to as “thermal vias,” even though their function is often for electrical as well as thermal conductivity. A “via” or “thermal via” generally refers to a conductor at least partially through a supporting substrate such as a PCB which can connect to at least one other conductive structure.
In contemplating conventional semiconductor device packages, the inventors have realized that while devices formed as wafer chip scale packages (WCSP) are thermally efficient, they are not able to take advantage of a structure such as an exposed thermal pad as used with quad flat no-lead (QFN) devices. The exposed thermal pad of a QFN device is formed as a part of the leadframe chip pad, and thus a conventional exposed thermal pad formed from a leadframe cannot be provided with a WCSP device.
Even so, the inventors have realized that improved thermal efficiency may be desired with future WCSP devices. Consumer electronics and other device components and subsystems are continually being miniaturized and formed with ever-decreasing profiles. As such, the flow of heat away from operating devices becomes more difficult, and heat-related device problems may increase with future component designs, even with the use of thermally-efficient WCSP packages. Further, devices with higher power dissipation are not able to take advantage of WCSP packages because even WCSP thermal efficiency can be insufficient when used with these chip types. High power devices therefore typically include packaging in a QFN or quad flat package (QFP). These packages, however, have a larger footprint and thus do not achieve the degree of miniaturization that a WCSP package offers.
Packages such as ball grid array (BGA) devices can include the use of solder balls or bumps as thermal connections to ground planes of a supporting substrate such as a printed circuit board (PCB). With a BGA device, which includes an encapsulated chip, solder balls or bumps on the package contact thermal vias on the PCB to draw heat away from the functioning chip. BGA devices have larger package sizes compared with a WCSP device, and the heat can be more easily dissipated. In a conventional device, placing a WCSP solder ball over a thermal via on a PCB can deplete the solder of the solder ball as the solder flows into an opening in the center of the via, resulting in increased electrical resistance or an electrical open, and thus these types of thermal connections are not an option for WCSP devices which have a moderate or high power dissipation. To overcome solder depletion, filled vias on the PCB can be used, but this is an expensive technique and can increase the difficulty in manufacturing the PCB. Laser microvias can also be used to decrease solder depletion, but this is also an expensive process and is thus only used on high-end PCB's.
A conventional WCSP device may contain a plurality of interconnect terminals each connected to a ground plane, but these interconnect terminals can be located at various sites around the active surface of the chip. In contemplating a way to allow a WCSP package to connect to conventional thermal vias in a supporting substrate, the inventors have realized that a thermal connection having a mass larger than a mass of a solder ball can be formed between the active surface of the chip and the supporting substrate to which it is attached. The mass provided can be larger in the X/Y directions and maintain a thickness in the Z direction similar to a solder ball so that spacing between the WCSP device and a PCB to which it is attached is not altered. Grouping the grounded interconnect terminals together on the surface of the chip, for example at the center of the chip, would provide a way to form a large thermal connection. A pad metallization structure can be formed over an area of the chip, and one (or more) mass of thermally and/or electrically conductive material (a “conductive mass”) can be formed either on the pad metallization structure on the active surface of the chip or on a supporting substrate to contact the pad metallization structure on the active surface of the chip. The conductive mass can contact one (or more) thermal or ground land on the PCB, which in turn contacts one or more vias to a ground plane within the PCB, thus providing a structure which can be used to dissipate heat from an operating WCSP device. Further, because the volume of the conductive mass is larger than the volume of a solder ball or other conductive interconnect, solder depletion is reduced or eliminated.
Various embodiments of the invention as described below can provide a method and structure for one or more thermal vias from a WCSP package to a grounding structure of a supporting substrate such as a PCB.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the figures:
It should be noted that some details of the FIGS. have been simplified and are drawn to facilitate understanding of the inventive embodiments rather than to maintain strict structural accuracy, detail, and scale.
Reference will now be made in detail to the present embodiments (exemplary embodiments) of the invention, an examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
To connect the solder balls 14 with interconnect lands 28, 29, the solder balls can be placed in physical contact with lands 28, 29, then the solder balls are reflowed, for example using the application of heat, to provide electrical, mechanical, and thermal coupling between the WCSP semiconductor device 10 and the PCB. In the conventional implementation of
To accommodate the use of a conductive mass which, in an embodiment, can function as a heat sink for the chip, a WCSP structure similar to that depicted in the plan view of
The solder balls can be in the range of from about 20 micrometers (μm) to about 500 μm in diameter, with a pitch of between about 50 μm and about 1,000 μm. Various metals and alloys would function sufficiently for the solder balls, such as a tin-lead alloy, a high-tin alloy, silver, and copper. In the
For simplicity of explanation, inventive embodiments are described with reference to the use of solder balls, but it is to be understood that conductive interconnects other than solder balls, such as bumps, posts, pillars, etc. manufactured from metals (gold, silver, copper, etc.), metal alloys (solder such as tin-lead solder, etc.), or other conductive materials (conductive paste such as silver-filled paste, etc.) are contemplated. In one alternative to solder balls, conductive posts such as copper posts can be formed, for example using a process similar to that described in U.S. Pat. No. 6,914,332, commonly assigned with the present application to Texas Instruments, Inc.
The pad metallization layer on the active surface of the chip which connects to the conductive mass 38 can be formed from an interconnect terminal metallization layer or another metallization layer such as a metal redistribution layer used for plural purposes, or from a separate metallization redistribution layer used specifically for connection with the conductive mass 38. To enhance thermal efficiency, the metallization layer can occupy as much of the active surface as possible, while avoiding electrical shorting or signal interference with the operating device.
In a device formed conventionally, six of 20 interconnect terminals might be connected with a ground plane. In the conventional device of
As depicted in the
Subsequent to contacting the solder balls 36 and conductive mass 38 with conductive lands or traces on the PCB, the solder can be heated and flowed to provide an electrical and mechanical attachment between the WCSP device and the supporting substrate.
With some chip designs and uses, less than six of 20 conventional interconnect terminals may be connected with a ground plane. The device of
Various other device arrangements which encompass an embodiment of the invention are contemplated. For example, more than one pad metallization 64 can be formed on the active surface of the chip 60, and more than one conductive mass 56 can be formed. The pad metallization and conductive mass can be formed at other locations on the chip, other than at the center as previously described.
Further, the conductive mass can be formed on a supporting structure land, similar to land 50 in
Additionally, the solder balls, bumps, posts, etc., can be formed from a first material, while the conductive mass is formed from a second, different material. The two materials can have, for example, different flow temperatures or other manufacturing or operating characteristics. In one embodiment, the balls, bumps, posts, etc. can be formed from solder while the conductive mass is formed from a material having a higher melting temperature than solder such as copper.
To form a copper pad metallization on the chip, a process similar to that described in U.S. Pat. No. 6,914,332, referenced above, can be used. In this use, a solder conductive mass (or thinner solder layer, whichever is needed based on the thickness of the copper pad metallization) can be formed on the supporting substrate such as a PCB rather than on the pad metallization of previous embodiments. As with previous embodiments, the solder balls can be formed on the interconnect terminals of the chip. The solder balls can be placed in contact with lands of the PCB, which results in contact between the copper conductive mass on the metallization pad and the solder on the PCB land. Next, the solder can be flowed to physically and electrically couple the WCSP device with the PCB.
In another embodiment, a conductive interconnect can be formed on the interconnect terminals of the chip, and a copper conductive mass can be formed on the pad metallization of the chip. These structures can also be formed using a process similar to that described in U.S. Pat. No. 6,914,332, which has been referenced above. In this embodiment, the copper bumps, pillars, or posts are formed on the interconnect terminals, and a copper conductive mass can be formed on the pad metallization of the chip. A conductive material such as solder, a conductive paste, or other conductive material can be used to physically and electrically couple the copper structures to lands of a supporting substrate such as a PCB. This can be performed using known techniques for applying a conductive material such as solder to the PCB in advance of receiving the chip. For example,
To determine the effectiveness of a conductive mass formed in accordance with an embodiment of the invention, a series of thermal simulations was performed. In one of these simulations, a WCSP device including the conductive mass in accordance with one embodiment had a temperature decrease of more than 19% over a similar device formed according to a conventional design. Further, the inventive device has a smaller footprint than a device such as a QFN package and thus is more desirable with regard to space considerations.
For purposes of the present invention, “encapsulation” is contrasted with “passivation” in that passivation can include openings to expose interconnect terminals on the wafer section. A passivation layer is also formed to be a thinner layer an encapsulation. For example, while a passivation layer can be in the range of between about 0.1 μm to about 15 μm, a thickness of an encapsulation layer is typically at least 300 μm thick. Because of its minimum thickness, a passivation layer has little or no effect on the thermal properties of the package. In contrast, an encapsulation layer restricts heat flow away from the encapsulated die and therefore has a negative effect on the thermal property of the package. A passivation layer is typically applied to the entire wafer and cured before any die singulation, for example using a wafer saw, while encapsulation is conventionally applied to each individual die and cured after singulation and some level of assembly processing such as wire bonding or flip chip interconnection. Further, a passivation layer is often used in conjunction with redistribution layers.
The volume of the conductive mass applied to the pad metallization relative to the volume of solder of a solder ball, bump, post, etc., depends on the number of solder balls the conductive mass is replacing, the pitch of the solder balls it is replacing, and the size of the solder balls it is replacing. In the
An embodiment of the inventive device can be used, for example, when it is desirable to place a conductive interconnect of small dimensions on a thermal via of a supporting substrate such as a PCB. A thermal via can be formed by mechanical drilling and metal plating. In conventional structures, the pitch and volume of these small conductive interconnects is not conducive to placement on a thermal via. For example, the volume of the small conductive interconnect can be depleted by the thermal via, thereby resulting in an increased electrical resistance or an electrical open of the conductive interconnect. By grouping plural conductive interconnects into one (or more) large conductive mass, the volume of material is increased, volume depletion is reduced, and no device functionality has been compromised.
An embodiment of the inventive device can also be used, for example (with reference to
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5. In certain cases, the numerical values as stated for the parameter can take on negative values. In this case, the example value of range stated as “less that 10” can assume negative values, e.g. −1, −2, −3, −10, −20, −30, etc.
While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Further, in the discussion and claims herein, the term “on” used with respect to two materials, one “on” the other, means at least some contact between the materials, while “over” means the materials are in proximity, but possibly with one or more additional intervening materials such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
