Patent Application
20170256470
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2016-043014, filed Mar. 7, 2016, the entire contents of which are incorporated herein by reference.
Field of the Invention
The present invention relates to a wiring substrate that is formed by laminating multiple conductive layers and multiple insulating layers, and relates to a method for manufacturing the wiring substrate.
Description of Background Art
Japanese Patent Laid-Open Publication No. 2006-059992 describes a wiring substrate in which a semiconductor element is embedded. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a wiring substrate includes insulating layers including a first insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and has an accommodating portion penetrating through the first insulating layer, conductive layers laminated on the insulating layers and including a first conductive layer formed on one end side of the first insulating layer in the lamination direction and a second conductive layer formed on the opposite side of the first insulating layer with respect to the one end side in the lamination direction, and a semiconductor element accommodated in the accommodating portion of the first insulating layer. The insulating layers include the first insulating layer including a reinforcing material and a second insulating layer laminated on the first insulating layer such that the second insulating layer is covering the second conductive layer and the semiconductor element and filling a gap formed between the first insulating layer and the semiconductor element in the accommodating portion and does not contain a reinforcing material.
According to another aspect of the present invention, a method for manufacturing a wiring substrate includes forming, on a support member, insulating layers including a first insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and has an accommodating portion penetrating through the first insulating layer, and conductive layers laminated on the insulating layers and including a first conductive layer formed on one end side of the first insulating layer in the lamination direction and a second conductive layer formed on the opposite side of the first insulating layer with respect to the one end side in the lamination direction, and removing the support member from the insulating and conductive layers. The forming of the insulation and conductive layers includes forming the first conductive layer on the support member, forming the first insulating layer on the support member such that the first insulating layer covers the first conductive layer on the support member, forming the accommodating portion in the first insulating layer such that the accommodating portion penetrates through the first insulating layer, accommodating a semiconductor element in the accommodating portion of the first insulating layer such that the semiconductor element is positioned in the accommodating portion of the first insulating layer, forming the second conductive layer on the first insulating layer such that the second conductive layer is formed on the opposite side of the first insulating layer with respect to the first conductive layer, and forming the second insulation on the first insulating layer such that the second insulating layer covers the second conductive layer and the semiconductor element, fills a gap formed between the first insulating layer and the semiconductor element in the accommodating portion and does not contain a reinforcing material, the removing of the support member includes removing the support member from the first insulating layer such that the semiconductor element is accommodated in the accommodating portion of the first insulating layer before the support member is removed from the first insulating layer, and the insulating layers include the first insulating layer including a reinforcing material.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
In the following, a first embodiment of the present invention is described with reference to
Among the multiple insulating resin layers (11, 14, 16) of the build-up layer 24, the first insulating resin layer 11 according to an embodiment of the present invention is formed at one end in a lamination direction. The second conductive layer 13 is laminated on a primary surface (11A) of the first insulating resin layer 11, the primary surface (11A) being a surface on an opposite side of the one end in the lamination direction. On the other hand, the first conductive layer 12 is formed on a secondary surface (11B) side of the first insulating resin layer 11, the secondary surface (11B) being on an opposite side of the primary surface (11A). The first conductive layer 12 is embedded on the secondary surface (11B) side of the first insulating resin layer 11 and is partially exposed on the secondary surface (11B). Further, a surface of the first conductive layer 12 on the secondary surface (11B) side of the first insulating resin layer 11 is positioned on an inner side of the secondary surface (11B) of the first insulating resin layer 11. In the present embodiment, a direction from the secondary surface (11B) toward the primary surface (11A) of the first insulating resin layer 11 is defined as “upward.”
Further, via holes (11H) and a cavity 20 (corresponding to an “accommodating part” according to an embodiment of the present invention) are formed in the first insulating resin layer 11. The via holes (11H) each have a tapered shape that is gradually reduced in diameter from the primary surface (11A) side toward the secondary surface (11B) side. The via holes (11H) are filled with plating and via conductors (11D) are formed. Then, due to the via conductors (11D) of the first insulating resin layer 11, the first conductive layer 12 and the second conductive layer 13 are connected to each other.
The cavity 20 has a truncated pyramid-shaped space that is gradually reduced in diameter from the primary surface (11A) side toward the secondary surface (11B), and penetrates the first insulating resin layer 11. Further, a portion of the first conductive layer 12 below the cavity 20 is a plane portion 18. An upper surface of the plane portion 18 is exposed as a bottom surface in the cavity 20.
A semiconductor element 30 is accommodated in the cavity 20. The semiconductor element 30 has an active surface (30C) on the primary surface (11A) side of the first insulating resin layer 11 and a non-active surface (30D) on the secondary surface (11B) side of the first insulating resin layer 11, terminals (30A, 30A) being provided on the active surface (30C) and no terminal being provided on the non-active surface (30D). The non-active surface (30D) is bonded to the plane portion 18 by an adhesive 31. Further, the semiconductor element 30 slightly protrudes from the cavity 20, and upper surfaces of the terminals (30A, 30A) are substantially flush with an upper surface of the second conductive layer 13.
The second insulating resin layer 14 covering the second conductive layer 13 is laminated on the primary surface (11A) of the first insulating resin layer 11. A portion of the second insulating resin layer 14 enters a gap between the semiconductor element 30 and an inner side surface of the cavity 20, and covers the semiconductor element 30. Further, the third conductive layer 15, the third insulating resin layer 16, and the fourth conductive layer 17 are formed in this order on an upper surface of the second insulating resin layer 14.
Multiple via holes (14H, 16H) are formed in the second and third insulating layers (14, 16). The via holes (14H, 16H) are filled with plating and multiple via conductors (14D, 16D) are formed. Then, due to the via conductors (14D) of the second insulating resin layer 14, the second conductive layer 13 and the third conductive layer 15 are connected to each other and the terminals (30A, 30A) of the semiconductor element 30 and the third conductive layer 15 are connected to each other; and, due to the via conductors (16D) of the third insulating resin layer 16, the third conductive layer 15 and the fourth conductive layer 17 are connected to each other.
A solder resist layer 25 is laminated on the outermost fourth conductive layer 17 of the build-up layer 24. Multiple pad holes are formed in the solder resist layer 25. Portions of the fourth conductive layer 17 that are respectively exposed from the pad holes become pads 26. A metal film 27 including a nickel layer, a palladium layer and a gold layer is formed on each of the pads 26.
The insulating resin layers (11, 14, 16) are all each formed from a resin sheet of a B-stage (for example, a prepreg, an insulating film for a build-up substrate, and the like). Here, in the wiring substrate 10 of the present embodiment, among the multiple insulating resin layers (11, 14, 16), the first insulating resin layer 11 contains a fibrous or cloth-like reinforcing material 19 such as a glass cloth (see
Further, among the via conductors (14D) of the second insulating resin layer 14, the via conductors (14D) (corresponding to “third vias” according to an embodiment of the present invention) that connect between the second conductive layer 13 and the third conductive layer 15 each have a top diameter substantially the same as that of each of the via conductors (11D) (corresponding to “second vias” according to an embodiment of the present invention) of the first insulating resin layer 11, whereas, among the via conductors (14D) of the second insulating resin layer 14, the via conductors (14D) (corresponding to “first vias” according to an embodiment of the present invention) that connect between the terminals (30A, 30A) of the semiconductor element 30 and the third conductive layer 15 each have a top diameter smaller than that of each of the via conductors (11D) of the first insulating resin layer 11. Along with that the second insulating resin layer 14 is thinner than the first insulating resin layer 11, the via conductors (14D) that connect between the second conductive layer 13 and the third conductive layer 15 are shorter than the via conductors (11D) of the first insulating resin layer 11 and each have a larger bottom diameter.
Next, a method for manufacturing the wiring substrate 10 of the present embodiment is described.
(1) As illustrated in
Since the same processing is performed on the carrier 34 on the F surface (50F) side of the support substrate 50 and on the carrier 34 on the B surface (50B) side of the support substrate 50, hereinafter, processing performed on the carrier 34 on the F surface (50F) side is described as an example.
(2) As illustrated in
(3) As illustrated in
(4) The plating resist 35 is peeled off. As illustrated in
(5) As illustrated in
(6) As illustrated in
(7) An electroless plating treatment is performed. An electroless plating film (not illustrated in the drawings) is formed on the first insulating resin layer 11 and in the via holes (11H).
(8) As illustrated in
(9) An electrolytic plating treatment is performed. As illustrated in
(10) The plating resist 40 is removed, and the electroless plating film (not illustrated in the drawings) under the plating resist 40 is removed. As illustrated in FIG. 5B, the second conductive layer 13 is formed on the first insulating resin layer 11 by the remaining electrolytic plating film 41 and electroless plating film. Then, the first conductive layer 12 and the second conductive layer 13 are connected to each other by the via conductors (11D).
(11) As illustrated in
(12) As illustrated in
(13) As illustrated in
(14) As illustrated in
(15) As illustrated in
(16) An electroless plating treatment is performed. An electroless plating film (not illustrated in the drawings) is formed on the second insulating resin layer 14 and in the via holes (14H).
(17) As illustrated in
(18) An electrolytic plating treatment is performed. As illustrated in
(19) The plating resist 42 is removed, and the electroless plating film (not illustrated in the drawings) under the plating resist 42 is removed. As illustrated in
(20) By the processes as the above described (13)-(19), as illustrated in
(21) As illustrated in
(22) As illustrated in
(23) On each of the pads 26, a nickel layer, a palladium layer and a gold layer are laminated in this order and a metal film 27 illustrated in
(24) As illustrated in
(25) The carrier 34 and the Ni plating layer 36 are respectively removed by etching. As a result, the wiring substrate 10 illustrated in
The description about the structure and the manufacturing method of the wiring substrate 10 of the present embodiment is as given above. Next, an example of use and an operation effect of the wiring substrate 10 are described. For example, as illustrated in
However, in the wiring substrate 10 of the present embodiment, the multiple insulating resin layers (11, 14, 16) include one insulating layer (the first insulating resin layer 11) that is formed by a resin sheet containing a reinforcing material 19. Therefore, as compared to a case where all insulating resin layers are each formed by a resin sheet that does not contain a reinforcing material 19, strength can be improved.
Here, it is also conceivable to allow all insulating resin layers to be each formed from a resin sheet containing a reinforcing material 19. However, in a resin sheet containing a reinforcing material 19, it is difficult to reduce a diameter of a via conductor as compared to a resin sheet without a reinforcing material 19, and thus it is likely to be difficult to form a dense (fine) wiring pattern. Along with this, when all the insulating resin layers are each formed from a resin sheet containing a reinforcing material 19, a problem can occur that the thickness of the wiring substrate is increased.
In contrast, in the wiring substrate 10 of the present embodiment, among the multiple insulating resin layers (11, 14, 16), only the first insulating resin layer 11 contains the reinforcing material 19. Therefore, the strength can be improved, and an increase in diameter of the via conductors and a decrease in density of the wiring pattern can be minimized. As a result, the top diameter of each of the via conductors (14D) that connect between the semiconductor element 30 and the third conductive layer 15 can be made smaller than the top diameter of each of the via conductors (11D) of the first insulating resin layer 11. Further, an increase in total thickness of the wiring substrate 10 can also be prevented.
In addition, the first insulating resin layer 11 that accommodates the semiconductor element 30 is selected as the insulating resin layer containing the reinforcing material 19. Therefore, strength of a surrounding portion of the semiconductor element 30 can be improved and occurrence of a failure in the semiconductor element 30 can be prevented. Further, the insulating resin layer accommodating the semiconductor element 30 is likely to be thicker than other insulating resin layers. Therefore, by allowing the relatively thick insulating resin layer to contain the reinforcing material 19, improvement in strength can be further achieved.
Further, in the wiring substrate 10 of the present embodiment, the first conductive layer 12 is embedded in the first insulating resin layer 11. Therefore, as compared to a case where the first conductive layer 12 is formed on the secondary surface (11B) of the first insulating resin layer 11, the total thickness of the wiring substrate 10 can be reduced. Further, the lower surface of the first conductive layer 12 is positioned on an inner side of the secondary surface (11B) of the first insulating resin layer 11. Therefore, unnecessary contact between the first conductive layer 12 and the electronic component 95 can be suppressed.
A wiring substrate (10V) of a second embodiment is different from the above wiring substrate 10 of the first embodiment in that the second insulating resin layer 14 has a two-layer structure. Specifically, as illustrated in
The cavity 20 of the present embodiment penetrates both the first insulating resin layer 11 and the first layer (14A) of the second insulating resin layer 14, and the second layer (14B) of the second insulating resin layer 14 enters the cavity 20 and covers the semiconductor element 30. In the present embodiment, of the cavity 20, a portion formed in the first insulating resin layer 11 corresponds to an “accommodating part” according to an embodiment of the present invention, and a portion formed in the second layer (14B) of the second insulating resin layer 14 corresponds to a “through hole” according to an embodiment of the present invention.
In the following, with respect to a method for manufacturing the wiring substrate (10V) of the present embodiment, a difference from the above first embodiment is mainly described.
(1) Following the process (10) of the manufacturing method of the first embodiment, as illustrated in
(2) As illustrated in
(3) As illustrated in
(4) As illustrated in
(5) Processes same as the processes (14)-(25) of the manufacturing method of the first embodiment are performed. As a result, the wiring substrate (10V) of the present embodiment illustrated in
According to the present embodiment, the second conductive layer 13 is covered by the first layer (14A) before the formation of the cavity 20. Therefore, for example, after the formation of the cavity 20, when resin residues on the plane portion 18 are removed, that a part of the second conductive layer 13 is erroneously removed can be prevented.
The present invention is not limited to the above-described embodiments. For example, embodiments described below are also included in the technical scope of the present invention. Further, in addition to the embodiments described below, the present invention can also be embodied in various modified forms within the scope without departing from the spirit of the present invention.
In the above embodiments, one semiconductor element 30 is accommodated in one cavity 20. However, it is also possible that multiple semiconductor elements 30 are accommodated in one cavity 20.
In the above embodiments, the first insulating resin layer 11 is thicker than the second and third insulating resin layers (14, 16). However, it is also possible that the second and third insulating resin layers (14, 16) are thick, or the two have the same thickness.
In the above embodiments, the top diameter of each of the via conductors (14D) that connect between the second conductive layer 13 and the third conductive layer 15 is substantially the same as the top diameter of each of the via conductors (11D) of the first insulating resin layer 11. However, it is also possible that the top diameter of each of the via conductors (14D) that connect between the second conductive layer 13 and the third conductive layer 15 is smaller than the top diameter of each of the via conductors (11D) of the first insulating resin layer 11.
In the above embodiments, the wiring substrate is used by connecting the fourth conductive layer 17 side to the motherboard 90 and mounting the electronic component 95 such as a CPU on the first conductive layer 12 side. However, it is also possible that the positions of the motherboard 90 and the electronic component 95 are reversed.
In the above embodiments, the copper plating layer 37 that becomes the first conductive layer 12 is formed after the Ni plating layer 36 is formed on the carrier 34. However, it is also possible that the copper plating layer 37 that becomes the first conductive layer 12 is directly formed.
In the above embodiments, three insulating resin layers are provided. However, it is also possible that two insulating resin layers are provided, or four or more insulating resin layers are provided.
In the above embodiments, a conductive layer is not formed on the first layer of the second insulating resin layer 14. However, it is also possible that a conductive layer is formed on the first layer.
In the above embodiments, the first conductive layer 12 is embedded in the first insulating resin layer 11. However, it is also possible that the first conductive layer 12 is laminated on the first insulating resin layer 11.
In the above embodiments, the plane portion 18 to which the semiconductor element 30 is provided in the first conductive layer 12. However, as illustrated in
In the above embodiments, only the first insulating resin layer 11 is an insulating resin layer that is formed from a resin sheet containing a reinforcing material 19. However, it is also possible that the third insulating resin layer 16 is also formed from a resin sheet containing a reinforcing material 19.
In the above embodiments, the “fibrous or cloth-like reinforcing material” is a glass cloth. However, the present invention is not limited to this. It is also possible that the “fibrous or cloth-like reinforcing material” is a carbon fiber, a glass non-woven fabric, an aramid cloth, an aramid non-woven fabric, or the like, or a combination of these.
A wiring substrate according to an embodiment of the present invention is formed by laminating multiple conductive layers and multiple insulating layers, the conductive layers each including a conductive path and being insulated from each other by the insulating layer. The wiring substrate includes: a first insulating layer that is formed at one end in a lamination direction among the multiple insulating layers, and contains a fibrous or cloth-like reinforcing material; an accommodating part that penetrates the first insulating layer; a semiconductor element that is accommodated in the accommodating part; a first conductive layer that is formed on a secondary surface side of the first insulating layer, the secondary surface being a surface of the first insulating layer on the one end side in the lamination direction; a second conductive layer that is formed on a primary surface side of the first insulating layer, the primary surface being a surface on an opposite side of the one end in the lamination direction; and a second insulating layer that is laminated on the first insulating layer and covers the second conductive layer and the semiconductor element, and is filled in a gap between an inner surface of the accommodating part and the semiconductor element, and does not contain a fibrous or cloth-like reinforcing material.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-043014 | Mar 2016 | JP | national |
