E. Ajith Amerasekera

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electrostatic discharge device and method
- Patent number 7,456,477
- Issue date Nov 25, 2008
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for electrostatic discharge protection using late...
- Patent number 6,628,493
- Issue date Sep 30, 2003
- Texas Instruments Incorporated
- Zhiliang Julian Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated ESD protection circuit using a substrate triggered later...
- Patent number 6,469,353
- Issue date Oct 22, 2002
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge device and method
- Patent number 6,433,392
- Issue date Aug 13, 2002
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip ESD protection in dual voltage CMOS
- Patent number 6,143,594
- Issue date Nov 7, 2000
- Texas Instruments Incorporated
- Alwin J. Tsao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip ESD protection in dual voltage CMOS
- Patent number 6,137,144
- Issue date Oct 24, 2000
- Texas Instruments Incorporated
- Alwin J. Tsao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral SCR structure for ESD protection in trench isolated technol...
- Patent number 6,081,002
- Issue date Jun 27, 2000
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EOS/ESD protection for high density integrated circuits
- Patent number 6,040,968
- Issue date Mar 21, 2000
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection for high density DRAMs using triple-well technology
- Patent number 5,949,094
- Issue date Sep 7, 1999
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cascoded-MOS ESD protection circuits for mixed voltage chips
- Patent number 5,930,094
- Issue date Jul 27, 1999
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated lateral structure for ESD protection in CMOS/BiCMOS tech...
- Patent number 5,804,860
- Issue date Sep 8, 1998
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for designing shallow junction, salicided NMOS transistors w...
- Patent number 5,793,083
- Issue date Aug 11, 1998
- Texas Instruments Incorporated
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Electrostatic discharge device and method
- Publication number 20030034527
- Publication date Feb 20, 2003
- E. Ajith Amerasekera
- H01 - BASIC ELECTRIC ELEMENTS

E. Ajith Amerasekera

Person

Patents Grantslast 30 patents

Electrostatic discharge device and method

System and method for electrostatic discharge protection using late...

Integrated ESD protection circuit using a substrate triggered later...

Electrostatic discharge device and method

On-chip ESD protection in dual voltage CMOS

On-chip ESD protection in dual voltage CMOS

Lateral SCR structure for ESD protection in trench isolated technol...

EOS/ESD protection for high density integrated circuits

ESD protection for high density DRAMs using triple-well technology

Cascoded-MOS ESD protection circuits for mixed voltage chips

Integrated lateral structure for ESD protection in CMOS/BiCMOS tech...

Method for designing shallow junction, salicided NMOS transistors w...

Patents Applicationslast 30 patents

Electrostatic discharge device and method