James P. Baukus

Person

Westlake Village, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Always-on FinFET with camouflaged punch stop implants for protectin...
- Patent number 11,664,332
- Issue date May 30, 2023
- RAMBUS INC.
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically isolated gate contact in FINFET technology for camoufl...
- Patent number 11,637,076
- Issue date Apr 25, 2023
- RAMBUS INC.
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Physically unclonable camouflage structure and methods for fabricat...
- Patent number 11,264,990
- Issue date Mar 1, 2022
- RAMBUS INC.
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure logic locking and configuration with camouflaged programmabl...
- Patent number 11,163,930
- Issue date Nov 2, 2021
- RAMBUS INC.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Camouflaged FinFET and method for producing same
- Patent number 10,923,596
- Issue date Feb 16, 2021
- RAMBUS INC.
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for camouflaging an integrated circuit using v...
- Patent number 10,817,638
- Issue date Oct 27, 2020
- Rambus Inc.
- Bryan J. Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure logic locking and configuration with camouflaged programmabl...
- Patent number 10,691,860
- Issue date Jun 23, 2020
- Rambus Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically unclonable camouflage structure and methods for fabricat...
- Patent number 10,574,237
- Issue date Feb 25, 2020
- VERIMATRIX
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for camouflaging a standard cell based integra...
- Patent number 9,940,425
- Issue date Apr 10, 2018
- Inside Secure S.A.
- Bryan Jason Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically unclonable camouflage structure and methods for fabricat...
- Patent number 9,735,781
- Issue date Aug 15, 2017
- Syphermedia International, Inc.
- Ronald P. Cocchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for camouflaging a standard cell based integra...
- Patent number 9,542,520
- Issue date Jan 10, 2017
- Syphermedia International, Inc.
- Bryan Jason Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for camouflaging a standard cell based integra...
- Patent number 9,355,199
- Issue date May 31, 2016
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of silicide block process to camouflage a false transistor
- Patent number 8,679,908
- Issue date Mar 25, 2014
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit modification using well implants
- Patent number 8,524,553
- Issue date Sep 3, 2013
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for camouflaging a standard cell based integra...
- Patent number 8,510,700
- Issue date Aug 13, 2013
- Syphermedia International, Inc.
- Ronald P. Cocchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for camouflaging a standard cell based integra...
- Patent number 8,418,091
- Issue date Apr 9, 2013
- SypherMedia International, Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 8,258,583
- Issue date Sep 4, 2012
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Camouflaging a standard cell based integrated circuit
- Patent number 8,151,235
- Issue date Apr 3, 2012
- SypherMedia International, Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Building block for a secure CMOS logic cell library
- Patent number 8,111,089
- Issue date Feb 7, 2012
- Syphermedia International, Inc.
- Ronald P. Cocchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 7,888,213
- Issue date Feb 15, 2011
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Covert transformation of transistor properties as a circuit protect...
- Patent number 7,541,266
- Issue date Jun 2, 2009
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit modification using well implants
- Patent number 7,514,755
- Issue date Apr 7, 2009
- HRL Laboratories LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of silicon block process step to camouflage a false transistor
- Patent number 7,344,932
- Issue date Mar 18, 2008
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits protected against reverse engineering and metho...
- Patent number 7,294,935
- Issue date Nov 13, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Covert transformation of transistor properties as a circuit protect...
- Patent number 7,217,977
- Issue date May 15, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implanted hidden interconnections in a semiconductor device for pre...
- Patent number 7,166,515
- Issue date Jan 23, 2007
- HRL Laboratories, LLC
- William M. Clark, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 7,049,667
- Issue date May 23, 2006
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reverse engineering protection
- Patent number 7,008,873
- Issue date Mar 7, 2006
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of silicon block process step to camouflage a false transistor
- Patent number 6,979,606
- Issue date Dec 27, 2005
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory with a bit line block and/or a word line block for preventin...
- Patent number 6,940,764
- Issue date Sep 6, 2005
- HRL Laboratories LLC
- William M. Clark, Jr.
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ALWAYS-ON FINFET WITH CAMOUFLAGED PUNCH STOP IMPLANTS FOR PROTECTIN...
- Publication number 20210249364
- Publication date Aug 12, 2021
- Rambus Inc.
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY ISOLATED GATE CONTACT IN FINFET TECHNOLOGY FOR CAMOUFL...
- Publication number 20210249363
- Publication date Aug 12, 2021
- Rambus Inc.
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SECURE LOGIC LOCKING AND CONFIGURATION WITH CAMOUFLAGED PROGRAMMABL...
- Publication number 20210004515
- Publication date Jan 7, 2021
- Rambus Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING AN INTEGRATED CIRCUIT USING V...
- Publication number 20200311222
- Publication date Oct 1, 2020
- INSIDE SECURE
- Bryan J. Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...
- Publication number 20200295763
- Publication date Sep 17, 2020
- RAMBUS INC.
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBFUSCATED SHIFT REGISTERS FOR INTEGRATED CIRCUITS
- Publication number 20200285719
- Publication date Sep 10, 2020
- Bryan J. Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAMOUFLAGED FINFET AND METHOD FOR PRODUCING SAME
- Publication number 20200287040
- Publication date Sep 10, 2020
- INSIDE SECURE
- Lap Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR OBFUSCATING AN INTEGRATED CIRCUIT WITH CAM...
- Publication number 20190258766
- Publication date Aug 22, 2019
- INSIDE SECURE
- Bryan J. Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE LOGIC LOCKING AND CONFIGURATION WITH CAMOUFLAGED PROGRAMMABL...
- Publication number 20180341737
- Publication date Nov 29, 2018
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...
- Publication number 20170359071
- Publication date Dec 14, 2017
- SYPHERMEDIA INTERNATIONAL, INC.
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...
- Publication number 20170091368
- Publication date Mar 30, 2017
- SypherMedia International, Inc.
- Bryan Jason Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...
- Publication number 20160197616
- Publication date Jul 7, 2016
- SYPHERMEDIA INTERNATIONAL, INC.
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...
- Publication number 20130300454
- Publication date Nov 14, 2013
- Bryan Jason Wang DiMarzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...
- Publication number 20130191803
- Publication date Jul 25, 2013
- SypherMedia International, Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...
- Publication number 20120139582
- Publication date Jun 7, 2012
- SYPHERMEDIA INTERNATIONAL, INC.
- Ronald P. Cocchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY
- Publication number 20100301903
- Publication date Dec 2, 2010
- SYPHERMEDIA INTERNATIONAL, INC.
- Ronald P. Cocchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for camouflaging a printed circuit board
- Publication number 20100213974
- Publication date Aug 26, 2010
- SypherMedia Interational, Inc.,
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...
- Publication number 20100218158
- Publication date Aug 26, 2010
- SypherMedia International, Inc.
- Lap Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS
- Publication number 20090170255
- Publication date Jul 2, 2009
- HRL LABORATORIES, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Use of silicon block process step to camouflage a false transistor
- Publication number 20070243675
- Publication date Oct 18, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Covert transformation of transistor properties as a circuit protect...
- Publication number 20070224750
- Publication date Sep 27, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive channel pseudo block process and circuit to inhibit reve...
- Publication number 20060157803
- Publication date Jul 20, 2006
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Covert transformation of transistor properties as a circuit protect...
- Publication number 20050230787
- Publication date Oct 20, 2005
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with reverse engineering protection
- Publication number 20050161748
- Publication date Jul 28, 2005
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Permanently on transistor implemented using a double polysilicon la...
- Publication number 20040164361
- Publication date Aug 26, 2004
- HRL Laboratories, LLC
- James P. Baukus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit modification using well implants
- Publication number 20040144998
- Publication date Jul 29, 2004
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multilayered integrated circuit with extraneous conductive traces
- Publication number 20040119165
- Publication date Jun 24, 2004
- James P. Baukus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Use of silicon block process step to camouflage a false transistor
- Publication number 20040099912
- Publication date May 27, 2004
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive channel pseudo block process and circuit to inhibit reve...
- Publication number 20040061186
- Publication date Apr 1, 2004
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory with a bit line block and/or a word line block for preventin...
- Publication number 20040047188
- Publication date Mar 11, 2004
- William M. Clark ,Jr
- G11 - INFORMATION STORAGE

James P. Baukus

Person

Patents Grantslast 30 patents

Always-on FinFET with camouflaged punch stop implants for protectin...

Electrically isolated gate contact in FINFET technology for camoufl...

Physically unclonable camouflage structure and methods for fabricat...

Secure logic locking and configuration with camouflaged programmabl...

Camouflaged FinFET and method for producing same

Method and apparatus for camouflaging an integrated circuit using v...

Secure logic locking and configuration with camouflaged programmabl...

Physically unclonable camouflage structure and methods for fabricat...

Method and apparatus for camouflaging a standard cell based integra...

Physically unclonable camouflage structure and methods for fabricat...

Method and apparatus for camouflaging a standard cell based integra...

Method and apparatus for camouflaging a standard cell based integra...

Use of silicide block process to camouflage a false transistor

Integrated circuit modification using well implants

Method and apparatus for camouflaging a standard cell based integra...

Method and apparatus for camouflaging a standard cell based integra...

Conductive channel pseudo block process and circuit to inhibit reve...

Camouflaging a standard cell based integrated circuit

Building block for a secure CMOS logic cell library

Conductive channel pseudo block process and circuit to inhibit reve...

Covert transformation of transistor properties as a circuit protect...

Integrated circuit modification using well implants

Use of silicon block process step to camouflage a false transistor

Integrated circuits protected against reverse engineering and metho...

Covert transformation of transistor properties as a circuit protect...

Implanted hidden interconnections in a semiconductor device for pre...

Conductive channel pseudo block process and circuit to inhibit reve...

Integrated circuit with reverse engineering protection

Use of silicon block process step to camouflage a false transistor

Memory with a bit line block and/or a word line block for preventin...

Patents Applicationslast 30 patents

ALWAYS-ON FINFET WITH CAMOUFLAGED PUNCH STOP IMPLANTS FOR PROTECTIN...

ELECTRICALLY ISOLATED GATE CONTACT IN FINFET TECHNOLOGY FOR CAMOUFL...

SECURE LOGIC LOCKING AND CONFIGURATION WITH CAMOUFLAGED PROGRAMMABL...

METHOD AND APPARATUS FOR CAMOUFLAGING AN INTEGRATED CIRCUIT USING V...

PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...

OBFUSCATED SHIFT REGISTERS FOR INTEGRATED CIRCUITS

CAMOUFLAGED FINFET AND METHOD FOR PRODUCING SAME

METHOD AND APPARATUS FOR OBFUSCATING AN INTEGRATED CIRCUIT WITH CAM...

SECURE LOGIC LOCKING AND CONFIGURATION WITH CAMOUFLAGED PROGRAMMABL...

PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...

PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICAT...

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...

BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY

Method and apparatus for camouflaging a printed circuit board

METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRA...

INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS

Use of silicon block process step to camouflage a false transistor

Covert transformation of transistor properties as a circuit protect...

Conductive channel pseudo block process and circuit to inhibit reve...

Covert transformation of transistor properties as a circuit protect...

Integrated circuit with reverse engineering protection

Permanently on transistor implemented using a double polysilicon la...

Integrated circuit modification using well implants

Multilayered integrated circuit with extraneous conductive traces

Use of silicon block process step to camouflage a false transistor

Conductive channel pseudo block process and circuit to inhibit reve...

Memory with a bit line block and/or a word line block for preventin...